\n
address_offset : 0x0 Bytes (0x0)
size : 0xDE0 byte (0x0)
mem_usage : registers
protection : not protected
CTX[2]-CTX[1]-CTX[0]-CTX_RGD_W0
CTX[2]-CTX[1]-CTX[0]-CTX_RGD_W1
CTX[3]-CTX[2]-CTX[1]-CTX[0]-CTX_RGD_W0
CTX[3]-CTX[2]-CTX[1]-CTX[0]-CTX_RGD_W1
CTX[3]-CTX[2]-CTX[1]-CTX[0]-CTX_CTR1
CTX[3]-CTX[2]-CTX[1]-CTX[0]-CTX_KEY3
AES Key Word
address_offset : 0x1A00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEY : AES Key
bits : 0 - 31 (32 bit)
access : read-write
AES Counter Word
address_offset : 0x1A20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTR : AES Counter
bits : 0 - 31 (32 bit)
access : read-write
AES Region Descriptor Word0
address_offset : 0x1A58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRTADDR : Start Address
bits : 10 - 31 (22 bit)
access : read-write
AES Region Descriptor Word1
address_offset : 0x1A5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VLD : Valid
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
Context is invalid.
0x1 : VLD_1
Context is valid.
End of enumeration elements list.
ADE : AES Decryption Enable.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : ADE_0
Bypass the fetched data.
0x1 : ADE_1
Perform the CTR-AES128 mode decryption on the fetched data.
End of enumeration elements list.
RO : Read-Only
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : RO_0
The context registers can be accessed normally (as defined by SR[RRAM]).
0x1 : RO_1
The context registers are read-only and accesses may be further restricted based on SR[RRAM].
End of enumeration elements list.
ENDADDR : End Address
bits : 10 - 31 (22 bit)
access : read-write
AES Key Word
address_offset : 0x2704 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEY : AES Key
bits : 0 - 31 (32 bit)
access : read-write
AES Counter Word
address_offset : 0x2734 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTR : AES Counter
bits : 0 - 31 (32 bit)
access : read-write
AES Region Descriptor Word0
address_offset : 0x27D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRTADDR : Start Address
bits : 10 - 31 (22 bit)
access : read-write
AES Region Descriptor Word1
address_offset : 0x27DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VLD : Valid
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
Context is invalid.
0x1 : VLD_1
Context is valid.
End of enumeration elements list.
ADE : AES Decryption Enable.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : ADE_0
Bypass the fetched data.
0x1 : ADE_1
Perform the CTR-AES128 mode decryption on the fetched data.
End of enumeration elements list.
RO : Read-Only
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : RO_0
The context registers can be accessed normally (as defined by SR[RRAM]).
0x1 : RO_1
The context registers are read-only and accesses may be further restricted based on SR[RRAM].
End of enumeration elements list.
ENDADDR : End Address
bits : 10 - 31 (22 bit)
access : read-write
AES Key Word
address_offset : 0x340C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEY : AES Key
bits : 0 - 31 (32 bit)
access : read-write
AES Counter Word
address_offset : 0x3474 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTR : AES Counter
bits : 0 - 31 (32 bit)
access : read-write
AES Region Descriptor Word0
address_offset : 0x3598 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRTADDR : Start Address
bits : 10 - 31 (22 bit)
access : read-write
AES Region Descriptor Word1
address_offset : 0x359C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VLD : Valid
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
Context is invalid.
0x1 : VLD_1
Context is valid.
End of enumeration elements list.
ADE : AES Decryption Enable.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : ADE_0
Bypass the fetched data.
0x1 : ADE_1
Perform the CTR-AES128 mode decryption on the fetched data.
End of enumeration elements list.
RO : Read-Only
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : RO_0
The context registers can be accessed normally (as defined by SR[RRAM]).
0x1 : RO_1
The context registers are read-only and accesses may be further restricted based on SR[RRAM].
End of enumeration elements list.
ENDADDR : End Address
bits : 10 - 31 (22 bit)
access : read-write
AES Key Word
address_offset : 0x4118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEY : AES Key
bits : 0 - 31 (32 bit)
access : read-write
AES Counter Word
address_offset : 0x41F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTR : AES Counter
bits : 0 - 31 (32 bit)
access : read-write
AES Key Word
address_offset : 0x4E58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEY : AES Key
bits : 0 - 31 (32 bit)
access : read-write
AES Counter Word
address_offset : 0x4FB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTR : AES Counter
bits : 0 - 31 (32 bit)
access : read-write
AES Key Word
address_offset : 0x5BD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEY : AES Key
bits : 0 - 31 (32 bit)
access : read-write
AES Key Word
address_offset : 0x6998 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEY : AES Key
bits : 0 - 31 (32 bit)
access : read-write
Control Register
address_offset : 0xC00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLDM : Force Logically Disabled Mode
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : FLDM_0
No effect on the operating mode.
0x1 : FLDM_1
Force entry into LDM after a write with this data bit set. SR[MODE] signals the operating mode.
End of enumeration elements list.
RRAE : Restricted Register Access Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : RRAE_0
Register access is fully enabled. The OTFAD programming model registers can be accessed "normally".
0x1 : RRAE_1
Register access is restricted and only the CR, SR and optional MDPC registers can be accessed; others are treated as RAZ/WI.
End of enumeration elements list.
GE : Global OTFAD Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : GE_0
OTFAD has decryption disabled. All data fetched by the FLEXSPI bypasses OTFAD processing.
0x1 : GE_1
OTFAD has decryption enabled, and processes data fetched by the FLEXSPI as defined by the hardware configuration.
End of enumeration elements list.
Status Register
address_offset : 0xC04 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MDPCP : MDPC Present
bits : 1 - 1 (1 bit)
access : read-only
MODE : Operating Mode
bits : 2 - 3 (2 bit)
access : read-only
Enumeration:
0 : MODE_0
Operating in Normal mode (NRM)
0x1 : MODE_1
Unused (reserved)
0x2 : MODE_2
Unused (reserved)
0x3 : MODE_3
Operating in Logically Disabled Mode (LDM)
End of enumeration elements list.
NCTX : Number of Contexts
bits : 4 - 7 (4 bit)
access : read-only
HRL : Hardware Revision Level
bits : 24 - 27 (4 bit)
access : read-only
RRAM : Restricted Register Access Mode
bits : 28 - 28 (1 bit)
access : read-only
Enumeration:
0 : RRAM_0
Register access is fully enabled. The OTFAD programming model registers can be accessed "normally".
0x1 : RRAM_1
Register access is restricted and only the CR, SR and optional MDPC registers can be accessed; others are treated as RAZ/WI.
End of enumeration elements list.
GEM : Global Enable Mode
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : GEM_0
OTFAD is disabled. All data fetched by the FLEXSPI bypasses OTFAD processing.
0x1 : GEM_1
OTFAD is enabled, and processes data fetched by the FLEXSPI as defined by the hardware configuration.
End of enumeration elements list.
AES Region Descriptor Word0
address_offset : 0xD18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRTADDR : Start Address
bits : 10 - 31 (22 bit)
access : read-write
AES Region Descriptor Word1
address_offset : 0xD1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VLD : Valid
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : VLD_0
Context is invalid.
0x1 : VLD_1
Context is valid.
End of enumeration elements list.
ADE : AES Decryption Enable.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : ADE_0
Bypass the fetched data.
0x1 : ADE_1
Perform the CTR-AES128 mode decryption on the fetched data.
End of enumeration elements list.
RO : Read-Only
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : RO_0
The context registers can be accessed normally (as defined by SR[RRAM]).
0x1 : RO_1
The context registers are read-only and accesses may be further restricted based on SR[RRAM].
End of enumeration elements list.
ENDADDR : End Address
bits : 10 - 31 (22 bit)
access : read-write
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