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NVIC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xE04 byte (0x0)
mem_usage : registers
protection : not protected

Registers

NVICISER0

NVICISPR0

NVICISPR1

NVICISPR2

NVICISPR3

NVICICPR0

NVICICPR1

NVICICPR2

NVICICPR3

NVICIABR0

NVICIABR1

NVICIABR2

NVICIABR3

NVICIP0

NVICIP1

NVICIP2

NVICIP3

NVICIP4

NVICIP5

NVICIP6

NVICIP7

NVICIP8

NVICIP9

NVICIP10

NVICIP11

NVICIP12

NVICIP13

NVICIP14

NVICIP15

NVICIP16

NVICIP17

NVICIP18

NVICIP19

NVICIP20

NVICIP21

NVICIP22

NVICIP23

NVICIP24

NVICIP25

NVICIP26

NVICIP27

NVICIP28

NVICIP29

NVICIP30

NVICIP31

NVICIP32

NVICIP33

NVICIP34

NVICIP35

NVICIP36

NVICIP37

NVICIP38

NVICIP39

NVICIP40

NVICIP41

NVICIP42

NVICIP43

NVICIP44

NVICIP45

NVICIP46

NVICIP47

NVICIP48

NVICIP49

NVICIP50

NVICIP51

NVICIP52

NVICIP53

NVICIP54

NVICIP55

NVICIP56

NVICIP57

NVICIP58

NVICIP59

NVICIP60

NVICIP61

NVICIP62

NVICIP63

NVICIP64

NVICISER1

NVICISER2

NVICICER0

NVICICER1

NVICICER2

NVICICER3

NVICISER3

NVICSTIR


NVICISER0

Interrupt Set Enable Register n
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICISER0 NVICISER0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETENA

SETENA : Interrupt set enable bits
bits : 0 - 31 (32 bit)
access : read-write


NVICISPR0

Interrupt Set Pending Register n
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICISPR0 NVICISPR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETPEND

SETPEND : Interrupt set-pending bits
bits : 0 - 31 (32 bit)
access : read-write


NVICISPR1

Interrupt Set Pending Register n
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICISPR1 NVICISPR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETPEND

SETPEND : Interrupt set-pending bits
bits : 0 - 31 (32 bit)
access : read-write


NVICISPR2

Interrupt Set Pending Register n
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICISPR2 NVICISPR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETPEND

SETPEND : Interrupt set-pending bits
bits : 0 - 31 (32 bit)
access : read-write


NVICISPR3

Interrupt Set Pending Register n
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICISPR3 NVICISPR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETPEND

SETPEND : Interrupt set-pending bits
bits : 0 - 31 (32 bit)
access : read-write


NVICICPR0

Interrupt Clear Pending Register n
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICICPR0 NVICICPR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRPEND

CLRPEND : Interrupt clear-pending bits
bits : 0 - 31 (32 bit)
access : read-write


NVICICPR1

Interrupt Clear Pending Register n
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICICPR1 NVICICPR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRPEND

CLRPEND : Interrupt clear-pending bits
bits : 0 - 31 (32 bit)
access : read-write


NVICICPR2

Interrupt Clear Pending Register n
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICICPR2 NVICICPR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRPEND

CLRPEND : Interrupt clear-pending bits
bits : 0 - 31 (32 bit)
access : read-write


NVICICPR3

Interrupt Clear Pending Register n
address_offset : 0x18C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICICPR3 NVICICPR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRPEND

CLRPEND : Interrupt clear-pending bits
bits : 0 - 31 (32 bit)
access : read-write


NVICIABR0

Interrupt Active bit Register n
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICIABR0 NVICIABR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACTIVE

ACTIVE : Interrupt active flags
bits : 0 - 31 (32 bit)
access : read-write


NVICIABR1

Interrupt Active bit Register n
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICIABR1 NVICIABR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACTIVE

ACTIVE : Interrupt active flags
bits : 0 - 31 (32 bit)
access : read-write


NVICIABR2

Interrupt Active bit Register n
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICIABR2 NVICIABR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACTIVE

ACTIVE : Interrupt active flags
bits : 0 - 31 (32 bit)
access : read-write


NVICIABR3

Interrupt Active bit Register n
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICIABR3 NVICIABR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACTIVE

ACTIVE : Interrupt active flags
bits : 0 - 31 (32 bit)
access : read-write


NVICIP0

Interrupt Priority Register 0
address_offset : 0x300 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICIP0 NVICIP0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI0

PRI0 : Priority of the INT_DMA0 interrupt 0
bits : 0 - 7 (8 bit)
access : read-write


NVICIP1

Interrupt Priority Register 1
address_offset : 0x301 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICIP1 NVICIP1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI1

PRI1 : Priority of the INT_DMA1 interrupt 1
bits : 0 - 7 (8 bit)
access : read-write


NVICIP2

Interrupt Priority Register 2
address_offset : 0x302 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICIP2 NVICIP2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI2

PRI2 : Priority of the INT_DMA2 interrupt 2
bits : 0 - 7 (8 bit)
access : read-write


NVICIP3

Interrupt Priority Register 3
address_offset : 0x303 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICIP3 NVICIP3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI3

PRI3 : Priority of the INT_DMA3 interrupt 3
bits : 0 - 7 (8 bit)
access : read-write


NVICIP4

Interrupt Priority Register 4
address_offset : 0x304 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICIP4 NVICIP4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI4

PRI4 : Priority of the INT_DMA4 interrupt 4
bits : 0 - 7 (8 bit)
access : read-write


NVICIP5

Interrupt Priority Register 5
address_offset : 0x305 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICIP5 NVICIP5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI5

PRI5 : Priority of the INT_DMA5 interrupt 5
bits : 0 - 7 (8 bit)
access : read-write


NVICIP6

Interrupt Priority Register 6
address_offset : 0x306 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICIP6 NVICIP6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI6

PRI6 : Priority of the INT_DMA6 interrupt 6
bits : 0 - 7 (8 bit)
access : read-write


NVICIP7

Interrupt Priority Register 7
address_offset : 0x307 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICIP7 NVICIP7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI7

PRI7 : Priority of the INT_DMA7 interrupt 7
bits : 0 - 7 (8 bit)
access : read-write


NVICIP8

Interrupt Priority Register 8
address_offset : 0x308 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICIP8 NVICIP8 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI8

PRI8 : Priority of the INT_DMA8 interrupt 8
bits : 0 - 7 (8 bit)
access : read-write


NVICIP9

Interrupt Priority Register 9
address_offset : 0x309 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICIP9 NVICIP9 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI9

PRI9 : Priority of the INT_DMA9 interrupt 9
bits : 0 - 7 (8 bit)
access : read-write


NVICIP10

Interrupt Priority Register 10
address_offset : 0x30A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICIP10 NVICIP10 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI10

PRI10 : Priority of the INT_DMA10 interrupt 10
bits : 0 - 7 (8 bit)
access : read-write


NVICIP11

Interrupt Priority Register 11
address_offset : 0x30B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICIP11 NVICIP11 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI11

PRI11 : Priority of the INT_DMA11 interrupt 11
bits : 0 - 7 (8 bit)
access : read-write


NVICIP12

Interrupt Priority Register 12
address_offset : 0x30C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICIP12 NVICIP12 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI12

PRI12 : Priority of the INT_DMA12 interrupt 12
bits : 0 - 7 (8 bit)
access : read-write


NVICIP13

Interrupt Priority Register 13
address_offset : 0x30D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICIP13 NVICIP13 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI13

PRI13 : Priority of the INT_DMA13 interrupt 13
bits : 0 - 7 (8 bit)
access : read-write


NVICIP14

Interrupt Priority Register 14
address_offset : 0x30E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICIP14 NVICIP14 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI14

PRI14 : Priority of the INT_DMA14 interrupt 14
bits : 0 - 7 (8 bit)
access : read-write


NVICIP15

Interrupt Priority Register 15
address_offset : 0x30F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICIP15 NVICIP15 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI15

PRI15 : Priority of the INT_DMA15 interrupt 15
bits : 0 - 7 (8 bit)
access : read-write


NVICIP16

Interrupt Priority Register 16
address_offset : 0x310 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICIP16 NVICIP16 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI16

PRI16 : Priority of the INT_DMA_Error interrupt 16
bits : 0 - 7 (8 bit)
access : read-write


NVICIP17

Interrupt Priority Register 17
address_offset : 0x311 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICIP17 NVICIP17 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI17

PRI17 : Priority of the INT_MCM interrupt 17
bits : 0 - 7 (8 bit)
access : read-write


NVICIP18

Interrupt Priority Register 18
address_offset : 0x312 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICIP18 NVICIP18 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI18

PRI18 : Priority of the INT_FTFL interrupt 18
bits : 0 - 7 (8 bit)
access : read-write


NVICIP19

Interrupt Priority Register 19
address_offset : 0x313 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICIP19 NVICIP19 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI19

PRI19 : Priority of the INT_Read_Collision interrupt 19
bits : 0 - 7 (8 bit)
access : read-write


NVICIP20

Interrupt Priority Register 20
address_offset : 0x314 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICIP20 NVICIP20 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI20

PRI20 : Priority of the INT_LVD_LVW interrupt 20
bits : 0 - 7 (8 bit)
access : read-write


NVICIP21

Interrupt Priority Register 21
address_offset : 0x315 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICIP21 NVICIP21 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI21

PRI21 : Priority of the INT_LLWU interrupt 21
bits : 0 - 7 (8 bit)
access : read-write


NVICIP22

Interrupt Priority Register 22
address_offset : 0x316 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICIP22 NVICIP22 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI22

PRI22 : Priority of the INT_WDOG_EWM interrupt 22
bits : 0 - 7 (8 bit)
access : read-write


NVICIP23

Interrupt Priority Register 23
address_offset : 0x317 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICIP23 NVICIP23 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI23

PRI23 : Priority of the INT_RNG interrupt 23
bits : 0 - 7 (8 bit)
access : read-write


NVICIP24

Interrupt Priority Register 24
address_offset : 0x318 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICIP24 NVICIP24 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI24

PRI24 : Priority of the INT_I2C0 interrupt 24
bits : 0 - 7 (8 bit)
access : read-write


NVICIP25

Interrupt Priority Register 25
address_offset : 0x319 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICIP25 NVICIP25 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI25

PRI25 : Priority of the INT_I2C1 interrupt 25
bits : 0 - 7 (8 bit)
access : read-write


NVICIP26

Interrupt Priority Register 26
address_offset : 0x31A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICIP26 NVICIP26 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI26

PRI26 : Priority of the INT_SPI0 interrupt 26
bits : 0 - 7 (8 bit)
access : read-write


NVICIP27

Interrupt Priority Register 27
address_offset : 0x31B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICIP27 NVICIP27 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI27

PRI27 : Priority of the INT_SPI1 interrupt 27
bits : 0 - 7 (8 bit)
access : read-write


NVICIP28

Interrupt Priority Register 28
address_offset : 0x31C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICIP28 NVICIP28 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI28

PRI28 : Priority of the INT_I2S0_Tx interrupt 28
bits : 0 - 7 (8 bit)
access : read-write


NVICIP29

Interrupt Priority Register 29
address_offset : 0x31D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICIP29 NVICIP29 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI29

PRI29 : Priority of the INT_I2S0_Rx interrupt 29
bits : 0 - 7 (8 bit)
access : read-write


NVICIP30

Interrupt Priority Register 30
address_offset : 0x31E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICIP30 NVICIP30 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI30

PRI30 : Priority of interrupt 30
bits : 0 - 7 (8 bit)
access : read-write


NVICIP31

Interrupt Priority Register 31
address_offset : 0x31F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICIP31 NVICIP31 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI31

PRI31 : Priority of the INT_UART0_RX_TX interrupt 31
bits : 0 - 7 (8 bit)
access : read-write


NVICIP32

Interrupt Priority Register 32
address_offset : 0x320 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICIP32 NVICIP32 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI32

PRI32 : Priority of the INT_UART0_ERR interrupt 32
bits : 0 - 7 (8 bit)
access : read-write


NVICIP33

Interrupt Priority Register 33
address_offset : 0x321 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICIP33 NVICIP33 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI33

PRI33 : Priority of the INT_UART1_RX_TX interrupt 33
bits : 0 - 7 (8 bit)
access : read-write


NVICIP34

Interrupt Priority Register 34
address_offset : 0x322 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICIP34 NVICIP34 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI34

PRI34 : Priority of the INT_UART1_ERR interrupt 34
bits : 0 - 7 (8 bit)
access : read-write


NVICIP35

Interrupt Priority Register 35
address_offset : 0x323 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICIP35 NVICIP35 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI35

PRI35 : Priority of the INT_UART2_RX_TX interrupt 35
bits : 0 - 7 (8 bit)
access : read-write


NVICIP36

Interrupt Priority Register 36
address_offset : 0x324 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICIP36 NVICIP36 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI36

PRI36 : Priority of the INT_UART2_ERR interrupt 36
bits : 0 - 7 (8 bit)
access : read-write


NVICIP37

Interrupt Priority Register 37
address_offset : 0x325 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICIP37 NVICIP37 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI37

PRI37 : Priority of the INT_UART3_RX_TX interrupt 37
bits : 0 - 7 (8 bit)
access : read-write


NVICIP38

Interrupt Priority Register 38
address_offset : 0x326 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICIP38 NVICIP38 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI38

PRI38 : Priority of the INT_UART3_ERR interrupt 38
bits : 0 - 7 (8 bit)
access : read-write


NVICIP39

Interrupt Priority Register 39
address_offset : 0x327 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICIP39 NVICIP39 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI39

PRI39 : Priority of the INT_ADC0 interrupt 39
bits : 0 - 7 (8 bit)
access : read-write


NVICIP40

Interrupt Priority Register 40
address_offset : 0x328 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICIP40 NVICIP40 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI40

PRI40 : Priority of the INT_CMP0 interrupt 40
bits : 0 - 7 (8 bit)
access : read-write


NVICIP41

Interrupt Priority Register 41
address_offset : 0x329 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICIP41 NVICIP41 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI41

PRI41 : Priority of the INT_CMP1 interrupt 41
bits : 0 - 7 (8 bit)
access : read-write


NVICIP42

Interrupt Priority Register 42
address_offset : 0x32A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICIP42 NVICIP42 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI42

PRI42 : Priority of the INT_FTM0 interrupt 42
bits : 0 - 7 (8 bit)
access : read-write


NVICIP43

Interrupt Priority Register 43
address_offset : 0x32B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICIP43 NVICIP43 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI43

PRI43 : Priority of the INT_FTM1 interrupt 43
bits : 0 - 7 (8 bit)
access : read-write


NVICIP44

Interrupt Priority Register 44
address_offset : 0x32C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICIP44 NVICIP44 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI44

PRI44 : Priority of the INT_FTM2 interrupt 44
bits : 0 - 7 (8 bit)
access : read-write


NVICIP45

Interrupt Priority Register 45
address_offset : 0x32D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICIP45 NVICIP45 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI45

PRI45 : Priority of the INT_CMT interrupt 45
bits : 0 - 7 (8 bit)
access : read-write


NVICIP46

Interrupt Priority Register 46
address_offset : 0x32E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICIP46 NVICIP46 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI46

PRI46 : Priority of the INT_RTC interrupt 46
bits : 0 - 7 (8 bit)
access : read-write


NVICIP47

Interrupt Priority Register 47
address_offset : 0x32F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICIP47 NVICIP47 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI47

PRI47 : Priority of the INT_RTC_Seconds interrupt 47
bits : 0 - 7 (8 bit)
access : read-write


NVICIP48

Interrupt Priority Register 48
address_offset : 0x330 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICIP48 NVICIP48 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI48

PRI48 : Priority of the INT_PIT0 interrupt 48
bits : 0 - 7 (8 bit)
access : read-write


NVICIP49

Interrupt Priority Register 49
address_offset : 0x331 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICIP49 NVICIP49 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI49

PRI49 : Priority of the INT_PIT1 interrupt 49
bits : 0 - 7 (8 bit)
access : read-write


NVICIP50

Interrupt Priority Register 50
address_offset : 0x332 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICIP50 NVICIP50 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI50

PRI50 : Priority of the INT_PIT2 interrupt 50
bits : 0 - 7 (8 bit)
access : read-write


NVICIP51

Interrupt Priority Register 51
address_offset : 0x333 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICIP51 NVICIP51 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI51

PRI51 : Priority of the INT_PIT3 interrupt 51
bits : 0 - 7 (8 bit)
access : read-write


NVICIP52

Interrupt Priority Register 52
address_offset : 0x334 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICIP52 NVICIP52 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI52

PRI52 : Priority of the INT_PDB0 interrupt 52
bits : 0 - 7 (8 bit)
access : read-write


NVICIP53

Interrupt Priority Register 53
address_offset : 0x335 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICIP53 NVICIP53 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI53

PRI53 : Priority of interrupt 53
bits : 0 - 7 (8 bit)
access : read-write


NVICIP54

Interrupt Priority Register 54
address_offset : 0x336 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICIP54 NVICIP54 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI54

PRI54 : Priority of interrupt 54
bits : 0 - 7 (8 bit)
access : read-write


NVICIP55

Interrupt Priority Register 55
address_offset : 0x337 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICIP55 NVICIP55 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI55

PRI55 : Priority of interrupt 55
bits : 0 - 7 (8 bit)
access : read-write


NVICIP56

Interrupt Priority Register 56
address_offset : 0x338 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICIP56 NVICIP56 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI56

PRI56 : Priority of the INT_DAC0 interrupt 56
bits : 0 - 7 (8 bit)
access : read-write


NVICIP57

Interrupt Priority Register 57
address_offset : 0x339 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICIP57 NVICIP57 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI57

PRI57 : Priority of the INT_MCG interrupt 57
bits : 0 - 7 (8 bit)
access : read-write


NVICIP58

Interrupt Priority Register 58
address_offset : 0x33A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICIP58 NVICIP58 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI58

PRI58 : Priority of the INT_LPTMR0 interrupt 58
bits : 0 - 7 (8 bit)
access : read-write


NVICIP59

Interrupt Priority Register 59
address_offset : 0x33B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICIP59 NVICIP59 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI59

PRI59 : Priority of the INT_PORTA interrupt 59
bits : 0 - 7 (8 bit)
access : read-write


NVICIP60

Interrupt Priority Register 60
address_offset : 0x33C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICIP60 NVICIP60 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI60

PRI60 : Priority of the INT_PORTB interrupt 60
bits : 0 - 7 (8 bit)
access : read-write


NVICIP61

Interrupt Priority Register 61
address_offset : 0x33D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICIP61 NVICIP61 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI61

PRI61 : Priority of the INT_PORTC interrupt 61
bits : 0 - 7 (8 bit)
access : read-write


NVICIP62

Interrupt Priority Register 62
address_offset : 0x33E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICIP62 NVICIP62 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI62

PRI62 : Priority of the INT_PORTD interrupt 62
bits : 0 - 7 (8 bit)
access : read-write


NVICIP63

Interrupt Priority Register 63
address_offset : 0x33F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICIP63 NVICIP63 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI63

PRI63 : Priority of the INT_PORTE interrupt 63
bits : 0 - 7 (8 bit)
access : read-write


NVICIP64

Interrupt Priority Register 64
address_offset : 0x340 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICIP64 NVICIP64 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI64

PRI64 : Priority of the INT_SWI interrupt 64
bits : 0 - 7 (8 bit)
access : read-write


NVICISER1

Interrupt Set Enable Register n
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICISER1 NVICISER1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETENA

SETENA : Interrupt set enable bits
bits : 0 - 31 (32 bit)
access : read-write


NVICISER2

Interrupt Set Enable Register n
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICISER2 NVICISER2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETENA

SETENA : Interrupt set enable bits
bits : 0 - 31 (32 bit)
access : read-write


NVICICER0

Interrupt Clear Enable Register n
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICICER0 NVICICER0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRENA

CLRENA : Interrupt clear-enable bits
bits : 0 - 31 (32 bit)
access : read-write


NVICICER1

Interrupt Clear Enable Register n
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICICER1 NVICICER1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRENA

CLRENA : Interrupt clear-enable bits
bits : 0 - 31 (32 bit)
access : read-write


NVICICER2

Interrupt Clear Enable Register n
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICICER2 NVICICER2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRENA

CLRENA : Interrupt clear-enable bits
bits : 0 - 31 (32 bit)
access : read-write


NVICICER3

Interrupt Clear Enable Register n
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICICER3 NVICICER3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRENA

CLRENA : Interrupt clear-enable bits
bits : 0 - 31 (32 bit)
access : read-write


NVICISER3

Interrupt Set Enable Register n
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICISER3 NVICISER3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETENA

SETENA : Interrupt set enable bits
bits : 0 - 31 (32 bit)
access : read-write


NVICSTIR

Software Trigger Interrupt Register
address_offset : 0xE00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVICSTIR NVICSTIR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTID

INTID : Interrupt ID of the interrupt to trigger, in the range 0-239. For example, a value of 0x03 specifies interrupt IRQ3.
bits : 0 - 8 (9 bit)
access : read-write



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