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DMAMUX

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CHCFG0

CHCFG1

CHCFG2

CHCFG3


CHCFG0

Channel Configuration register
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCFG0 CHCFG0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SOURCE TRIG ENBL

SOURCE : DMA Channel Source (Slot)
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

#0 : 0

Disable_Signal

#10 : 2

UART0_Rx_Signal

#11 : 3

UART0_Tx_Signal

#100 : 4

UART1_Rx_Signal

#101 : 5

UART1_Tx_Signal

#110 : 6

UART2_Rx_Signal

#111 : 7

UART2_Tx_Signal

#1100 : 12

I2S0_Rx_Signal

#1101 : 13

I2S0_Tx_Signal

#1110 : 14

SPI0_Rx_Signal

#1111 : 15

SPI0_Tx_Signal

#10000 : 16

SPI1_Signal

#10010 : 18

I2C0_Signal

#10011 : 19

I2C1_Signal

#10100 : 20

FTM0_Channel0_Signal

#10101 : 21

FTM0_Channel1_Signal

#10110 : 22

FTM0_Channel2_Signal

#10111 : 23

FTM0_Channel3_Signal

#11000 : 24

FTM0_Channel4_Signal

#11001 : 25

FTM0_Channel5_Signal

#11010 : 26

FTM0_Channel6_Signal

#11011 : 27

FTM0_Channel7_Signal

#11100 : 28

FTM1_Channel0_Signal

#11101 : 29

FTM1_Channel1_Signal

#11110 : 30

FTM2_Channel0_Signal

#11111 : 31

FTM2_Channel1_Signal

#101000 : 40

ADC0_Signal

#101001 : 41

ADC1_Signal

#101010 : 42

CMP0_Signal

#101011 : 43

CMP1_Signal

#101101 : 45

DAC0_Signal

#110000 : 48

PDB_Signal

#110001 : 49

PortA_Signal

#110010 : 50

PortB_Signal

#110011 : 51

PortC_Signal

#110100 : 52

PortD_Signal

#110101 : 53

PortE_Signal

#111010 : 58

LPUART0_Rx_Signal

#111011 : 59

LPUART0_Tx_Signal

#111100 : 60

AlwaysOn60_Signal

#111101 : 61

AlwaysOn61_Signal

#111110 : 62

AlwaysOn62_Signal

#111111 : 63

AlwaysOn63_Signal

End of enumeration elements list.

TRIG : DMA Channel Trigger Enable
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)

#1 : 1

Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode.

End of enumeration elements list.

ENBL : DMA Channel Enable
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel.

#1 : 1

DMA channel is enabled

End of enumeration elements list.


CHCFG1

Channel Configuration register
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCFG1 CHCFG1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SOURCE TRIG ENBL

SOURCE : DMA Channel Source (Slot)
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

#0 : 0

Disable_Signal

#10 : 2

UART0_Rx_Signal

#11 : 3

UART0_Tx_Signal

#100 : 4

UART1_Rx_Signal

#101 : 5

UART1_Tx_Signal

#110 : 6

UART2_Rx_Signal

#111 : 7

UART2_Tx_Signal

#1100 : 12

I2S0_Rx_Signal

#1101 : 13

I2S0_Tx_Signal

#1110 : 14

SPI0_Rx_Signal

#1111 : 15

SPI0_Tx_Signal

#10000 : 16

SPI1_Signal

#10010 : 18

I2C0_Signal

#10011 : 19

I2C1_Signal

#10100 : 20

FTM0_Channel0_Signal

#10101 : 21

FTM0_Channel1_Signal

#10110 : 22

FTM0_Channel2_Signal

#10111 : 23

FTM0_Channel3_Signal

#11000 : 24

FTM0_Channel4_Signal

#11001 : 25

FTM0_Channel5_Signal

#11010 : 26

FTM0_Channel6_Signal

#11011 : 27

FTM0_Channel7_Signal

#11100 : 28

FTM1_Channel0_Signal

#11101 : 29

FTM1_Channel1_Signal

#11110 : 30

FTM2_Channel0_Signal

#11111 : 31

FTM2_Channel1_Signal

#101000 : 40

ADC0_Signal

#101001 : 41

ADC1_Signal

#101010 : 42

CMP0_Signal

#101011 : 43

CMP1_Signal

#101101 : 45

DAC0_Signal

#110000 : 48

PDB_Signal

#110001 : 49

PortA_Signal

#110010 : 50

PortB_Signal

#110011 : 51

PortC_Signal

#110100 : 52

PortD_Signal

#110101 : 53

PortE_Signal

#111010 : 58

LPUART0_Rx_Signal

#111011 : 59

LPUART0_Tx_Signal

#111100 : 60

AlwaysOn60_Signal

#111101 : 61

AlwaysOn61_Signal

#111110 : 62

AlwaysOn62_Signal

#111111 : 63

AlwaysOn63_Signal

End of enumeration elements list.

TRIG : DMA Channel Trigger Enable
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)

#1 : 1

Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode.

End of enumeration elements list.

ENBL : DMA Channel Enable
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel.

#1 : 1

DMA channel is enabled

End of enumeration elements list.


CHCFG2

Channel Configuration register
address_offset : 0x3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCFG2 CHCFG2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SOURCE TRIG ENBL

SOURCE : DMA Channel Source (Slot)
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

#0 : 0

Disable_Signal

#10 : 2

UART0_Rx_Signal

#11 : 3

UART0_Tx_Signal

#100 : 4

UART1_Rx_Signal

#101 : 5

UART1_Tx_Signal

#110 : 6

UART2_Rx_Signal

#111 : 7

UART2_Tx_Signal

#1100 : 12

I2S0_Rx_Signal

#1101 : 13

I2S0_Tx_Signal

#1110 : 14

SPI0_Rx_Signal

#1111 : 15

SPI0_Tx_Signal

#10000 : 16

SPI1_Signal

#10010 : 18

I2C0_Signal

#10011 : 19

I2C1_Signal

#10100 : 20

FTM0_Channel0_Signal

#10101 : 21

FTM0_Channel1_Signal

#10110 : 22

FTM0_Channel2_Signal

#10111 : 23

FTM0_Channel3_Signal

#11000 : 24

FTM0_Channel4_Signal

#11001 : 25

FTM0_Channel5_Signal

#11010 : 26

FTM0_Channel6_Signal

#11011 : 27

FTM0_Channel7_Signal

#11100 : 28

FTM1_Channel0_Signal

#11101 : 29

FTM1_Channel1_Signal

#11110 : 30

FTM2_Channel0_Signal

#11111 : 31

FTM2_Channel1_Signal

#101000 : 40

ADC0_Signal

#101001 : 41

ADC1_Signal

#101010 : 42

CMP0_Signal

#101011 : 43

CMP1_Signal

#101101 : 45

DAC0_Signal

#110000 : 48

PDB_Signal

#110001 : 49

PortA_Signal

#110010 : 50

PortB_Signal

#110011 : 51

PortC_Signal

#110100 : 52

PortD_Signal

#110101 : 53

PortE_Signal

#111010 : 58

LPUART0_Rx_Signal

#111011 : 59

LPUART0_Tx_Signal

#111100 : 60

AlwaysOn60_Signal

#111101 : 61

AlwaysOn61_Signal

#111110 : 62

AlwaysOn62_Signal

#111111 : 63

AlwaysOn63_Signal

End of enumeration elements list.

TRIG : DMA Channel Trigger Enable
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)

#1 : 1

Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode.

End of enumeration elements list.

ENBL : DMA Channel Enable
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel.

#1 : 1

DMA channel is enabled

End of enumeration elements list.


CHCFG3

Channel Configuration register
address_offset : 0x6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCFG3 CHCFG3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SOURCE TRIG ENBL

SOURCE : DMA Channel Source (Slot)
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

#0 : 0

Disable_Signal

#10 : 2

UART0_Rx_Signal

#11 : 3

UART0_Tx_Signal

#100 : 4

UART1_Rx_Signal

#101 : 5

UART1_Tx_Signal

#110 : 6

UART2_Rx_Signal

#111 : 7

UART2_Tx_Signal

#1100 : 12

I2S0_Rx_Signal

#1101 : 13

I2S0_Tx_Signal

#1110 : 14

SPI0_Rx_Signal

#1111 : 15

SPI0_Tx_Signal

#10000 : 16

SPI1_Signal

#10010 : 18

I2C0_Signal

#10011 : 19

I2C1_Signal

#10100 : 20

FTM0_Channel0_Signal

#10101 : 21

FTM0_Channel1_Signal

#10110 : 22

FTM0_Channel2_Signal

#10111 : 23

FTM0_Channel3_Signal

#11000 : 24

FTM0_Channel4_Signal

#11001 : 25

FTM0_Channel5_Signal

#11010 : 26

FTM0_Channel6_Signal

#11011 : 27

FTM0_Channel7_Signal

#11100 : 28

FTM1_Channel0_Signal

#11101 : 29

FTM1_Channel1_Signal

#11110 : 30

FTM2_Channel0_Signal

#11111 : 31

FTM2_Channel1_Signal

#101000 : 40

ADC0_Signal

#101001 : 41

ADC1_Signal

#101010 : 42

CMP0_Signal

#101011 : 43

CMP1_Signal

#101101 : 45

DAC0_Signal

#110000 : 48

PDB_Signal

#110001 : 49

PortA_Signal

#110010 : 50

PortB_Signal

#110011 : 51

PortC_Signal

#110100 : 52

PortD_Signal

#110101 : 53

PortE_Signal

#111010 : 58

LPUART0_Rx_Signal

#111011 : 59

LPUART0_Tx_Signal

#111100 : 60

AlwaysOn60_Signal

#111101 : 61

AlwaysOn61_Signal

#111110 : 62

AlwaysOn62_Signal

#111111 : 63

AlwaysOn63_Signal

End of enumeration elements list.

TRIG : DMA Channel Trigger Enable
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)

#1 : 1

Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode.

End of enumeration elements list.

ENBL : DMA Channel Enable
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel.

#1 : 1

DMA channel is enabled

End of enumeration elements list.



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