\n
address_offset : 0x0 Bytes (0x0)
size : 0x8C byte (0x0)
mem_usage : registers
protection : not protected
Module Configuration Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HALT : Halt
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Start transfers.
#1 : 1
Stop transfers.
End of enumeration elements list.
SMPL_PT : Sample Point
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
0 protocol clock cycles between SCK edge and SIN sample
#01 : 01
1 protocol clock cycle between SCK edge and SIN sample
#10 : 10
2 protocol clock cycles between SCK edge and SIN sample
End of enumeration elements list.
CLR_RXF : CLR_RXF
bits : 10 - 10 (1 bit)
access : write-only
Enumeration:
#0 : 0
Do not clear the RX FIFO counter.
#1 : 1
Clear the RX FIFO counter.
End of enumeration elements list.
CLR_TXF : Clear TX FIFO
bits : 11 - 11 (1 bit)
access : write-only
Enumeration:
#0 : 0
Do not clear the TX FIFO counter.
#1 : 1
Clear the TX FIFO counter.
End of enumeration elements list.
DIS_RXF : Disable Receive FIFO
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
RX FIFO is enabled.
#1 : 1
RX FIFO is disabled.
End of enumeration elements list.
DIS_TXF : Disable Transmit FIFO
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
TX FIFO is enabled.
#1 : 1
TX FIFO is disabled.
End of enumeration elements list.
MDIS : Module Disable
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enables the module clocks.
#1 : 1
Allows external logic to disable the module clocks.
End of enumeration elements list.
DOZE : Doze Enable
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Doze mode has no effect on the module.
#1 : 1
Doze mode disables the module.
End of enumeration elements list.
PCSIS0 : Peripheral Chip Select x Inactive State
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
The inactive state of PCSx is low.
#1 : 1
The inactive state of PCSx is high.
End of enumeration elements list.
PCSIS1 : Peripheral Chip Select x Inactive State
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
The inactive state of PCSx is low.
#1 : 1
The inactive state of PCSx is high.
End of enumeration elements list.
PCSIS2 : Peripheral Chip Select x Inactive State
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
The inactive state of PCSx is low.
#1 : 1
The inactive state of PCSx is high.
End of enumeration elements list.
PCSIS3 : Peripheral Chip Select x Inactive State
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
The inactive state of PCSx is low.
#1 : 1
The inactive state of PCSx is high.
End of enumeration elements list.
PCSIS4 : Peripheral Chip Select x Inactive State
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
The inactive state of PCSx is low.
#1 : 1
The inactive state of PCSx is high.
End of enumeration elements list.
PCSIS5 : Peripheral Chip Select x Inactive State
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
The inactive state of PCSx is low.
#1 : 1
The inactive state of PCSx is high.
End of enumeration elements list.
ROOE : Receive FIFO Overflow Overwrite Enable
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Incoming data is ignored.
#1 : 1
Incoming data is shifted into the shift register.
End of enumeration elements list.
PCSSE : Peripheral Chip Select Strobe Enable
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
PCS5/ PCSS is used as the Peripheral Chip Select[5] signal.
#1 : 1
PCS5/ PCSS is used as an active-low PCS Strobe signal.
End of enumeration elements list.
MTFE : Modified Transfer Format Enable
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Modified SPI transfer format disabled.
#1 : 1
Modified SPI transfer format enabled.
End of enumeration elements list.
FRZ : Freeze
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not halt serial transfers in Debug mode.
#1 : 1
Halt serial transfers in Debug mode.
End of enumeration elements list.
DCONF : SPI Configuration.
bits : 28 - 29 (2 bit)
access : read-only
Enumeration:
#00 : 00
SPI
End of enumeration elements list.
CONT_SCKE : Continuous SCK Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Continuous SCK disabled.
#1 : 1
Continuous SCK enabled.
End of enumeration elements list.
MSTR : Master/Slave Mode Select
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enables Slave mode
#1 : 1
Enables Master mode
End of enumeration elements list.
Transmit FIFO Registers
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXDATA : Transmit Data
bits : 0 - 15 (16 bit)
access : read-only
TXCMD_TXDATA : Transmit Command or Transmit Data
bits : 16 - 31 (16 bit)
access : read-only
Receive FIFO Registers
address_offset : 0x178 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXDATA : Receive Data
bits : 0 - 31 (32 bit)
access : read-only
Clock and Transfer Attributes Register (In Master Mode)
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : SPI1
reset_Mask : 0x0
BR : Baud Rate Scaler
bits : 0 - 3 (4 bit)
access : read-write
DT : Delay After Transfer Scaler
bits : 4 - 7 (4 bit)
access : read-write
ASC : After SCK Delay Scaler
bits : 8 - 11 (4 bit)
access : read-write
CSSCK : PCS to SCK Delay Scaler
bits : 12 - 15 (4 bit)
access : read-write
PBR : Baud Rate Prescaler
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#00 : 00
Baud Rate Prescaler value is 2.
#01 : 01
Baud Rate Prescaler value is 3.
#10 : 10
Baud Rate Prescaler value is 5.
#11 : 11
Baud Rate Prescaler value is 7.
End of enumeration elements list.
PDT : Delay after Transfer Prescaler
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
#00 : 00
Delay after Transfer Prescaler value is 1.
#01 : 01
Delay after Transfer Prescaler value is 3.
#10 : 10
Delay after Transfer Prescaler value is 5.
#11 : 11
Delay after Transfer Prescaler value is 7.
End of enumeration elements list.
PASC : After SCK Delay Prescaler
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
#00 : 00
Delay after Transfer Prescaler value is 1.
#01 : 01
Delay after Transfer Prescaler value is 3.
#10 : 10
Delay after Transfer Prescaler value is 5.
#11 : 11
Delay after Transfer Prescaler value is 7.
End of enumeration elements list.
PCSSCK : PCS to SCK Delay Prescaler
bits : 22 - 23 (2 bit)
access : read-write
Enumeration:
#00 : 00
PCS to SCK Prescaler value is 1.
#01 : 01
PCS to SCK Prescaler value is 3.
#10 : 10
PCS to SCK Prescaler value is 5.
#11 : 11
PCS to SCK Prescaler value is 7.
End of enumeration elements list.
LSBFE : LSB First
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Data is transferred MSB first.
#1 : 1
Data is transferred LSB first.
End of enumeration elements list.
CPHA : Clock Phase
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Data is captured on the leading edge of SCK and changed on the following edge.
#1 : 1
Data is changed on the leading edge of SCK and captured on the following edge.
End of enumeration elements list.
CPOL : Clock Polarity
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
The inactive state value of SCK is low.
#1 : 1
The inactive state value of SCK is high.
End of enumeration elements list.
FMSZ : Frame Size
bits : 27 - 30 (4 bit)
access : read-write
DBR : Double Baud Rate
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
The baud rate is computed normally with a 50/50 duty cycle.
#1 : 1
The baud rate is doubled with the duty cycle depending on the Baud Rate Prescaler.
End of enumeration elements list.
Receive FIFO Registers
address_offset : 0x1FC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXDATA : Receive Data
bits : 0 - 31 (32 bit)
access : read-only
Clock and Transfer Attributes Register (In Master Mode)
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : SPI1
reset_Mask : 0x0
BR : Baud Rate Scaler
bits : 0 - 3 (4 bit)
access : read-write
DT : Delay After Transfer Scaler
bits : 4 - 7 (4 bit)
access : read-write
ASC : After SCK Delay Scaler
bits : 8 - 11 (4 bit)
access : read-write
CSSCK : PCS to SCK Delay Scaler
bits : 12 - 15 (4 bit)
access : read-write
PBR : Baud Rate Prescaler
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#00 : 00
Baud Rate Prescaler value is 2.
#01 : 01
Baud Rate Prescaler value is 3.
#10 : 10
Baud Rate Prescaler value is 5.
#11 : 11
Baud Rate Prescaler value is 7.
End of enumeration elements list.
PDT : Delay after Transfer Prescaler
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
#00 : 00
Delay after Transfer Prescaler value is 1.
#01 : 01
Delay after Transfer Prescaler value is 3.
#10 : 10
Delay after Transfer Prescaler value is 5.
#11 : 11
Delay after Transfer Prescaler value is 7.
End of enumeration elements list.
PASC : After SCK Delay Prescaler
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
#00 : 00
Delay after Transfer Prescaler value is 1.
#01 : 01
Delay after Transfer Prescaler value is 3.
#10 : 10
Delay after Transfer Prescaler value is 5.
#11 : 11
Delay after Transfer Prescaler value is 7.
End of enumeration elements list.
PCSSCK : PCS to SCK Delay Prescaler
bits : 22 - 23 (2 bit)
access : read-write
Enumeration:
#00 : 00
PCS to SCK Prescaler value is 1.
#01 : 01
PCS to SCK Prescaler value is 3.
#10 : 10
PCS to SCK Prescaler value is 5.
#11 : 11
PCS to SCK Prescaler value is 7.
End of enumeration elements list.
LSBFE : LSB First
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Data is transferred MSB first.
#1 : 1
Data is transferred LSB first.
End of enumeration elements list.
CPHA : Clock Phase
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Data is captured on the leading edge of SCK and changed on the following edge.
#1 : 1
Data is changed on the leading edge of SCK and captured on the following edge.
End of enumeration elements list.
CPOL : Clock Polarity
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
The inactive state value of SCK is low.
#1 : 1
The inactive state value of SCK is high.
End of enumeration elements list.
FMSZ : Frame Size
bits : 27 - 30 (4 bit)
access : read-write
DBR : Double Baud Rate
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
The baud rate is computed normally with a 50/50 duty cycle.
#1 : 1
The baud rate is doubled with the duty cycle depending on the Baud Rate Prescaler.
End of enumeration elements list.
Receive FIFO Registers
address_offset : 0x284 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXDATA : Receive Data
bits : 0 - 31 (32 bit)
access : read-only
Status Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POPNXTPTR : Pop Next Pointer
bits : 0 - 3 (4 bit)
access : read-only
RXCTR : RX FIFO Counter
bits : 4 - 7 (4 bit)
access : read-only
TXNXTPTR : Transmit Next Pointer
bits : 8 - 11 (4 bit)
access : read-only
TXCTR : TX FIFO Counter
bits : 12 - 15 (4 bit)
access : read-only
RFDF : Receive FIFO Drain Flag
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
RX FIFO is empty.
#1 : 1
RX FIFO is not empty.
End of enumeration elements list.
RFOF : Receive FIFO Overflow Flag
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
No Rx FIFO overflow.
#1 : 1
Rx FIFO overflow has occurred.
End of enumeration elements list.
TFFF : Transmit FIFO Fill Flag
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
TX FIFO is full.
#1 : 1
TX FIFO is not full.
End of enumeration elements list.
TFUF : Transmit FIFO Underflow Flag
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
No TX FIFO underflow.
#1 : 1
TX FIFO underflow has occurred.
End of enumeration elements list.
EOQF : End of Queue Flag
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
EOQ is not set in the executing command.
#1 : 1
EOQ is set in the executing SPI command.
End of enumeration elements list.
TXRXS : TX and RX Status
bits : 30 - 30 (1 bit)
access : read-only
Enumeration:
#0 : 0
Transmit and receive operations are disabled (The module is in Stopped state).
#1 : 1
Transmit and receive operations are enabled (The module is in Running state).
End of enumeration elements list.
TCF : Transfer Complete Flag
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transfer not complete.
#1 : 1
Transfer complete.
End of enumeration elements list.
DMA/Interrupt Request Select and Enable Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RFDF_DIRS : Receive FIFO Drain DMA or Interrupt Request Select
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt request.
#1 : 1
DMA request.
End of enumeration elements list.
RFDF_RE : Receive FIFO Drain Request Enable
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
RFDF interrupt or DMA requests are disabled.
#1 : 1
RFDF interrupt or DMA requests are enabled.
End of enumeration elements list.
RFOF_RE : Receive FIFO Overflow Request Enable
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
RFOF interrupt requests are disabled.
#1 : 1
RFOF interrupt requests are enabled.
End of enumeration elements list.
TFFF_DIRS : Transmit FIFO Fill DMA or Interrupt Request Select
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
TFFF flag generates interrupt requests.
#1 : 1
TFFF flag generates DMA requests.
End of enumeration elements list.
TFFF_RE : Transmit FIFO Fill Request Enable
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
TFFF interrupts or DMA requests are disabled.
#1 : 1
TFFF interrupts or DMA requests are enabled.
End of enumeration elements list.
TFUF_RE : Transmit FIFO Underflow Request Enable
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
TFUF interrupt requests are disabled.
#1 : 1
TFUF interrupt requests are enabled.
End of enumeration elements list.
EOQF_RE : Finished Request Enable
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
EOQF interrupt requests are disabled.
#1 : 1
EOQF interrupt requests are enabled.
End of enumeration elements list.
TCF_RE : Transmission Complete Request Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
TCF interrupt requests are disabled.
#1 : 1
TCF interrupt requests are enabled.
End of enumeration elements list.
PUSH TX FIFO Register In Master Mode
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : SPI1
reset_Mask : 0x0
TXDATA : Transmit Data
bits : 0 - 15 (16 bit)
access : read-write
PCS0 : Select which PCS signals are to be asserted for the transfer
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Negate the PCS[x] signal.
#1 : 1
Assert the PCS[x] signal.
End of enumeration elements list.
PCS1 : Select which PCS signals are to be asserted for the transfer
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Negate the PCS[x] signal.
#1 : 1
Assert the PCS[x] signal.
End of enumeration elements list.
PCS2 : Select which PCS signals are to be asserted for the transfer
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Negate the PCS[x] signal.
#1 : 1
Assert the PCS[x] signal.
End of enumeration elements list.
PCS3 : Select which PCS signals are to be asserted for the transfer
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Negate the PCS[x] signal.
#1 : 1
Assert the PCS[x] signal.
End of enumeration elements list.
PCS4 : Select which PCS signals are to be asserted for the transfer
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Negate the PCS[x] signal.
#1 : 1
Assert the PCS[x] signal.
End of enumeration elements list.
PCS5 : Select which PCS signals are to be asserted for the transfer
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Negate the PCS[x] signal.
#1 : 1
Assert the PCS[x] signal.
End of enumeration elements list.
CTCNT : Clear Transfer Counter
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not clear the TCR[TCNT] field.
#1 : 1
Clear the TCR[TCNT] field.
End of enumeration elements list.
EOQ : End Of Queue
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
The SPI data is not the last data to transfer.
#1 : 1
The SPI data is the last data to transfer.
End of enumeration elements list.
CTAS : Clock and Transfer Attributes Select
bits : 28 - 30 (3 bit)
access : read-write
Enumeration:
#000 : 000
CTAR0
#001 : 001
CTAR1
End of enumeration elements list.
CONT : Continuous Peripheral Chip Select Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Return PCSn signals to their inactive state between transfers.
#1 : 1
Keep PCSn signals asserted between transfers.
End of enumeration elements list.
PUSH TX FIFO Register In Slave Mode
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : SPI1
reset_Mask : 0x0
TXDATA : Transmit Data
bits : 0 - 15 (16 bit)
access : read-write
POP RX FIFO Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXDATA : Received Data
bits : 0 - 31 (32 bit)
access : read-only
Transmit FIFO Registers
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXDATA : Transmit Data
bits : 0 - 15 (16 bit)
access : read-only
TXCMD_TXDATA : Transmit Command or Transmit Data
bits : 16 - 31 (16 bit)
access : read-only
Transfer Count Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPI_TCNT : SPI Transfer Counter
bits : 16 - 31 (16 bit)
access : read-write
Transmit FIFO Registers
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXDATA : Transmit Data
bits : 0 - 15 (16 bit)
access : read-only
TXCMD_TXDATA : Transmit Command or Transmit Data
bits : 16 - 31 (16 bit)
access : read-only
Clock and Transfer Attributes Register (In Slave Mode)
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : SPI1
reset_Mask : 0x0
CPHA : Clock Phase
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Data is captured on the leading edge of SCK and changed on the following edge.
#1 : 1
Data is changed on the leading edge of SCK and captured on the following edge.
End of enumeration elements list.
CPOL : Clock Polarity
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
The inactive state value of SCK is low.
#1 : 1
The inactive state value of SCK is high.
End of enumeration elements list.
FMSZ : Frame Size
bits : 27 - 30 (4 bit)
access : read-write
Receive FIFO Registers
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXDATA : Receive Data
bits : 0 - 31 (32 bit)
access : read-only
Transmit FIFO Registers
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXDATA : Transmit Data
bits : 0 - 15 (16 bit)
access : read-only
TXCMD_TXDATA : Transmit Command or Transmit Data
bits : 16 - 31 (16 bit)
access : read-only
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