Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x108 byte (0x0)
mem_usage : registers
protection : not protected
SAI Transmit Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRDE : FIFO Request DMA Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disables the DMA request.
#1 : 1
Enables the DMA request.
End of enumeration elements list.
FWDE : FIFO Warning DMA Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disables the DMA request.
#1 : 1
Enables the DMA request.
End of enumeration elements list.
FRIE : FIFO Request Interrupt Enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disables the interrupt.
#1 : 1
Enables the interrupt.
End of enumeration elements list.
FWIE : FIFO Warning Interrupt Enable
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disables the interrupt.
#1 : 1
Enables the interrupt.
End of enumeration elements list.
FEIE : FIFO Error Interrupt Enable
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disables the interrupt.
#1 : 1
Enables the interrupt.
End of enumeration elements list.
SEIE : Sync Error Interrupt Enable
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disables interrupt.
#1 : 1
Enables interrupt.
End of enumeration elements list.
WSIE : Word Start Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disables interrupt.
#1 : 1
Enables interrupt.
End of enumeration elements list.
FRF : FIFO Request Flag
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
#0 : 0
Transmit FIFO watermark has not been reached.
#1 : 1
Transmit FIFO watermark has been reached.
End of enumeration elements list.
FWF : FIFO Warning Flag
bits : 17 - 17 (1 bit)
access : read-only
Enumeration:
#0 : 0
No enabled transmit FIFO is empty.
#1 : 1
Enabled transmit FIFO is empty.
End of enumeration elements list.
FEF : FIFO Error Flag
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transmit underrun not detected.
#1 : 1
Transmit underrun detected.
End of enumeration elements list.
SEF : Sync Error Flag
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Sync error not detected.
#1 : 1
Frame sync error detected.
End of enumeration elements list.
WSF : Word Start Flag
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Start of word not detected.
#1 : 1
Start of word detected.
End of enumeration elements list.
SR : Software Reset
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.
#1 : 1
Software reset.
End of enumeration elements list.
FR : FIFO Reset
bits : 25 - 25 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect.
#1 : 1
FIFO reset.
End of enumeration elements list.
BCE : Bit Clock Enable
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transmit bit clock is disabled.
#1 : 1
Transmit bit clock is enabled.
End of enumeration elements list.
DBGE : Debug Enable
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transmitter is disabled in Debug mode, after completing the current frame.
#1 : 1
Transmitter is enabled in Debug mode.
End of enumeration elements list.
STOPE : Stop Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transmitter disabled in Stop mode.
#1 : 1
Transmitter enabled in Stop mode.
End of enumeration elements list.
TE : Transmitter Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transmitter is disabled.
#1 : 1
Transmitter is enabled, or transmitter has been disabled and has not yet reached end of frame.
End of enumeration elements list.
SAI Transmit Configuration 4 Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FSD : Frame Sync Direction
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Frame sync is generated externally in Slave mode.
#1 : 1
Frame sync is generated internally in Master mode.
End of enumeration elements list.
FSP : Frame Sync Polarity
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Frame sync is active high.
#1 : 1
Frame sync is active low.
End of enumeration elements list.
ONDEM : On Demand Mode
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal frame sync is generated continuously.
#1 : 1
Internal frame sync is generated when the FIFO warning flag is clear.
End of enumeration elements list.
FSE : Frame Sync Early
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Frame sync asserts with the first bit of the frame.
#1 : 1
Frame sync asserts one bit before the first bit of the frame.
End of enumeration elements list.
MF : MSB First
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
LSB is transmitted first.
#1 : 1
MSB is transmitted first.
End of enumeration elements list.
SYWD : Sync Width
bits : 8 - 12 (5 bit)
access : read-write
FRSZ : Frame size
bits : 16 - 20 (5 bit)
access : read-write
FPACK : FIFO Packing Mode
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
FIFO packing is disabled
#10 : 10
8-bit FIFO packing is enabled
#11 : 11
16-bit FIFO packing is enabled
End of enumeration elements list.
FCOMB : FIFO Combine Mode
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
#00 : 00
FIFO combine mode disabled.
#01 : 01
FIFO combine mode enabled on FIFO reads (from transmit shift registers).
#10 : 10
FIFO combine mode enabled on FIFO writes (by software).
#11 : 11
FIFO combine mode enabled on FIFO reads (from transmit shift registers) and writes (by software).
End of enumeration elements list.
FCONT : FIFO Continue on Error
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared.
#1 : 1
On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared.
End of enumeration elements list.
SAI MCLK Control Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MICS : MCLK Input Clock Select
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
MCLK divider input clock 0 is selected.
#01 : 01
MCLK divider input clock 1 is selected.
#10 : 10
MCLK divider input clock 2 is selected.
#11 : 11
MCLK divider input clock 3 is selected.
End of enumeration elements list.
MOE : MCLK Output Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
MCLK signal pin is configured as an input that bypasses the MCLK divider.
#1 : 1
MCLK signal pin is configured as an output from the MCLK divider and the MCLK divider is enabled.
End of enumeration elements list.
DUF : Divider Update Flag
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
MCLK divider ratio is not being updated currently.
#1 : 1
MCLK divider ratio is updating on-the-fly. Further updates to the MCLK divider ratio are blocked while this flag remains set.
End of enumeration elements list.
SAI MCLK Divide Register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIVIDE : MCLK Divide
bits : 0 - 11 (12 bit)
access : read-write
FRACT : MCLK Fraction
bits : 12 - 19 (8 bit)
access : read-write
SAI Transmit Configuration 5 Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FBT : First Bit Shifted
bits : 8 - 12 (5 bit)
access : read-write
W0W : Word 0 Width
bits : 16 - 20 (5 bit)
access : read-write
WNW : Word N Width
bits : 24 - 28 (5 bit)
access : read-write
SAI Receive Data Register
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDR : Receive Data Register
bits : 0 - 31 (32 bit)
access : read-only
SAI Receive FIFO Register
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RFP : Read FIFO Pointer
bits : 0 - 3 (4 bit)
access : read-only
RCP : Receive Channel Pointer
bits : 15 - 15 (1 bit)
access : read-only
Enumeration:
#0 : 0
No effect.
#1 : 1
FIFO combine is enabled for FIFO reads and this FIFO will be read on the next FIFO read.
End of enumeration elements list.
WFP : Write FIFO Pointer
bits : 16 - 19 (4 bit)
access : read-only
SAI Receive Data Register
address_offset : 0x1E4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDR : Receive Data Register
bits : 0 - 31 (32 bit)
access : read-only
SAI Receive FIFO Register
address_offset : 0x244 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RFP : Read FIFO Pointer
bits : 0 - 3 (4 bit)
access : read-only
RCP : Receive Channel Pointer
bits : 15 - 15 (1 bit)
access : read-only
Enumeration:
#0 : 0
No effect.
#1 : 1
FIFO combine is enabled for FIFO reads and this FIFO will be read on the next FIFO read.
End of enumeration elements list.
WFP : Write FIFO Pointer
bits : 16 - 19 (4 bit)
access : read-only
SAI Transmit Configuration 1 Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TFW : Transmit FIFO Watermark
bits : 0 - 2 (3 bit)
access : read-write
SAI Transmit Data Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TDR : Transmit Data Register
bits : 0 - 31 (32 bit)
access : write-only
SAI Transmit Mask Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TWM0 : Transmit Word Mask
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Word N is enabled.
#1 : 1
Word N is masked. The transmit data pins are tri-stated when masked.
End of enumeration elements list.
TWM1 : Transmit Word Mask
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Word N is enabled.
#1 : 1
Word N is masked. The transmit data pins are tri-stated when masked.
End of enumeration elements list.
TWM2 : Transmit Word Mask
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Word N is enabled.
#1 : 1
Word N is masked. The transmit data pins are tri-stated when masked.
End of enumeration elements list.
TWM3 : Transmit Word Mask
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Word N is enabled.
#1 : 1
Word N is masked. The transmit data pins are tri-stated when masked.
End of enumeration elements list.
TWM4 : Transmit Word Mask
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Word N is enabled.
#1 : 1
Word N is masked. The transmit data pins are tri-stated when masked.
End of enumeration elements list.
TWM5 : Transmit Word Mask
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Word N is enabled.
#1 : 1
Word N is masked. The transmit data pins are tri-stated when masked.
End of enumeration elements list.
TWM6 : Transmit Word Mask
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Word N is enabled.
#1 : 1
Word N is masked. The transmit data pins are tri-stated when masked.
End of enumeration elements list.
TWM7 : Transmit Word Mask
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Word N is enabled.
#1 : 1
Word N is masked. The transmit data pins are tri-stated when masked.
End of enumeration elements list.
TWM8 : Transmit Word Mask
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Word N is enabled.
#1 : 1
Word N is masked. The transmit data pins are tri-stated when masked.
End of enumeration elements list.
TWM9 : Transmit Word Mask
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Word N is enabled.
#1 : 1
Word N is masked. The transmit data pins are tri-stated when masked.
End of enumeration elements list.
TWM10 : Transmit Word Mask
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Word N is enabled.
#1 : 1
Word N is masked. The transmit data pins are tri-stated when masked.
End of enumeration elements list.
TWM11 : Transmit Word Mask
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Word N is enabled.
#1 : 1
Word N is masked. The transmit data pins are tri-stated when masked.
End of enumeration elements list.
TWM12 : Transmit Word Mask
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Word N is enabled.
#1 : 1
Word N is masked. The transmit data pins are tri-stated when masked.
End of enumeration elements list.
TWM13 : Transmit Word Mask
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Word N is enabled.
#1 : 1
Word N is masked. The transmit data pins are tri-stated when masked.
End of enumeration elements list.
TWM14 : Transmit Word Mask
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Word N is enabled.
#1 : 1
Word N is masked. The transmit data pins are tri-stated when masked.
End of enumeration elements list.
TWM15 : Transmit Word Mask
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Word N is enabled.
#1 : 1
Word N is masked. The transmit data pins are tri-stated when masked.
End of enumeration elements list.
TWM16 : Transmit Word Mask
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Word N is enabled.
#1 : 1
Word N is masked. The transmit data pins are tri-stated when masked.
End of enumeration elements list.
TWM17 : Transmit Word Mask
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Word N is enabled.
#1 : 1
Word N is masked. The transmit data pins are tri-stated when masked.
End of enumeration elements list.
TWM18 : Transmit Word Mask
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Word N is enabled.
#1 : 1
Word N is masked. The transmit data pins are tri-stated when masked.
End of enumeration elements list.
TWM19 : Transmit Word Mask
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Word N is enabled.
#1 : 1
Word N is masked. The transmit data pins are tri-stated when masked.
End of enumeration elements list.
TWM20 : Transmit Word Mask
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Word N is enabled.
#1 : 1
Word N is masked. The transmit data pins are tri-stated when masked.
End of enumeration elements list.
TWM21 : Transmit Word Mask
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Word N is enabled.
#1 : 1
Word N is masked. The transmit data pins are tri-stated when masked.
End of enumeration elements list.
TWM22 : Transmit Word Mask
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Word N is enabled.
#1 : 1
Word N is masked. The transmit data pins are tri-stated when masked.
End of enumeration elements list.
TWM23 : Transmit Word Mask
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Word N is enabled.
#1 : 1
Word N is masked. The transmit data pins are tri-stated when masked.
End of enumeration elements list.
TWM24 : Transmit Word Mask
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Word N is enabled.
#1 : 1
Word N is masked. The transmit data pins are tri-stated when masked.
End of enumeration elements list.
TWM25 : Transmit Word Mask
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Word N is enabled.
#1 : 1
Word N is masked. The transmit data pins are tri-stated when masked.
End of enumeration elements list.
TWM26 : Transmit Word Mask
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Word N is enabled.
#1 : 1
Word N is masked. The transmit data pins are tri-stated when masked.
End of enumeration elements list.
TWM27 : Transmit Word Mask
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Word N is enabled.
#1 : 1
Word N is masked. The transmit data pins are tri-stated when masked.
End of enumeration elements list.
TWM28 : Transmit Word Mask
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Word N is enabled.
#1 : 1
Word N is masked. The transmit data pins are tri-stated when masked.
End of enumeration elements list.
TWM29 : Transmit Word Mask
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Word N is enabled.
#1 : 1
Word N is masked. The transmit data pins are tri-stated when masked.
End of enumeration elements list.
TWM30 : Transmit Word Mask
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Word N is enabled.
#1 : 1
Word N is masked. The transmit data pins are tri-stated when masked.
End of enumeration elements list.
TWM31 : Transmit Word Mask
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Word N is enabled.
#1 : 1
Word N is masked. The transmit data pins are tri-stated when masked.
End of enumeration elements list.
SAI Transmit Data Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TDR : Transmit Data Register
bits : 0 - 31 (32 bit)
access : write-only
SAI Transmit Configuration 2 Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV : Bit Clock Divide
bits : 0 - 7 (8 bit)
access : read-write
BCD : Bit Clock Direction
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bit clock is generated externally in Slave mode.
#1 : 1
Bit clock is generated internally in Master mode.
End of enumeration elements list.
BCP : Bit Clock Polarity
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge.
#1 : 1
Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge.
End of enumeration elements list.
MSEL : MCLK Select
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
#00 : 00
Bus Clock selected.
#01 : 01
Master Clock (MCLK) 1 option selected.
#10 : 10
Master Clock (MCLK) 2 option selected.
#11 : 11
Master Clock (MCLK) 3 option selected.
End of enumeration elements list.
BCI : Bit Clock Input
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.
#1 : 1
Internal logic is clocked as if bit clock was externally generated.
End of enumeration elements list.
BCS : Bit Clock Swap
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Use the normal bit clock source.
#1 : 1
Swap the bit clock source.
End of enumeration elements list.
SYNC0 : Synchronous Mode
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#00 : 00
Asynchronous mode.
#01 : 01
Synchronous with receiver.
End of enumeration elements list.
SYNC1 : Synchronous Mode
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#00 : 00
Asynchronous mode.
#01 : 01
Synchronous with receiver.
End of enumeration elements list.
SAI Transmit FIFO Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RFP : Read FIFO Pointer
bits : 0 - 3 (4 bit)
access : read-only
WFP : Write FIFO Pointer
bits : 16 - 19 (4 bit)
access : read-only
WCP : Write Channel Pointer
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
No effect.
#1 : 1
FIFO combine is enabled for FIFO writes and this FIFO will be written on the next FIFO write.
End of enumeration elements list.
SAI Receive Control Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRDE : FIFO Request DMA Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disables the DMA request.
#1 : 1
Enables the DMA request.
End of enumeration elements list.
FWDE : FIFO Warning DMA Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disables the DMA request.
#1 : 1
Enables the DMA request.
End of enumeration elements list.
FRIE : FIFO Request Interrupt Enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disables the interrupt.
#1 : 1
Enables the interrupt.
End of enumeration elements list.
FWIE : FIFO Warning Interrupt Enable
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disables the interrupt.
#1 : 1
Enables the interrupt.
End of enumeration elements list.
FEIE : FIFO Error Interrupt Enable
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disables the interrupt.
#1 : 1
Enables the interrupt.
End of enumeration elements list.
SEIE : Sync Error Interrupt Enable
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disables interrupt.
#1 : 1
Enables interrupt.
End of enumeration elements list.
WSIE : Word Start Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disables interrupt.
#1 : 1
Enables interrupt.
End of enumeration elements list.
FRF : FIFO Request Flag
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
#0 : 0
Receive FIFO watermark not reached.
#1 : 1
Receive FIFO watermark has been reached.
End of enumeration elements list.
FWF : FIFO Warning Flag
bits : 17 - 17 (1 bit)
access : read-only
Enumeration:
#0 : 0
No enabled receive FIFO is full.
#1 : 1
Enabled receive FIFO is full.
End of enumeration elements list.
FEF : FIFO Error Flag
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receive overflow not detected.
#1 : 1
Receive overflow detected.
End of enumeration elements list.
SEF : Sync Error Flag
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Sync error not detected.
#1 : 1
Frame sync error detected.
End of enumeration elements list.
WSF : Word Start Flag
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Start of word not detected.
#1 : 1
Start of word detected.
End of enumeration elements list.
SR : Software Reset
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.
#1 : 1
Software reset.
End of enumeration elements list.
FR : FIFO Reset
bits : 25 - 25 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect.
#1 : 1
FIFO reset.
End of enumeration elements list.
BCE : Bit Clock Enable
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receive bit clock is disabled.
#1 : 1
Receive bit clock is enabled.
End of enumeration elements list.
DBGE : Debug Enable
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receiver is disabled in Debug mode, after completing the current frame.
#1 : 1
Receiver is enabled in Debug mode.
End of enumeration elements list.
STOPE : Stop Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receiver disabled in Stop mode.
#1 : 1
Receiver enabled in Stop mode.
End of enumeration elements list.
RE : Receiver Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receiver is disabled.
#1 : 1
Receiver is enabled, or receiver has been disabled and has not yet reached end of frame.
End of enumeration elements list.
SAI Receive Configuration 1 Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RFW : Receive FIFO Watermark
bits : 0 - 2 (3 bit)
access : read-write
SAI Receive Configuration 2 Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV : Bit Clock Divide
bits : 0 - 7 (8 bit)
access : read-write
BCD : Bit Clock Direction
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bit clock is generated externally in Slave mode.
#1 : 1
Bit clock is generated internally in Master mode.
End of enumeration elements list.
BCP : Bit Clock Polarity
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bit Clock is active high with drive outputs on rising edge and sample inputs on falling edge.
#1 : 1
Bit Clock is active low with drive outputs on falling edge and sample inputs on rising edge.
End of enumeration elements list.
MSEL : MCLK Select
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
#00 : 00
Bus Clock selected.
#01 : 01
Master Clock (MCLK) 1 option selected.
#10 : 10
Master Clock (MCLK) 2 option selected.
#11 : 11
Master Clock (MCLK) 3 option selected.
End of enumeration elements list.
BCI : Bit Clock Input
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.
#1 : 1
Internal logic is clocked as if bit clock was externally generated.
End of enumeration elements list.
BCS : Bit Clock Swap
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Use the normal bit clock source.
#1 : 1
Swap the bit clock source.
End of enumeration elements list.
SYNC0 : Synchronous Mode
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#00 : 00
Asynchronous mode.
#01 : 01
Synchronous with transmitter.
End of enumeration elements list.
SYNC1 : Synchronous Mode
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#00 : 00
Asynchronous mode.
#01 : 01
Synchronous with transmitter.
End of enumeration elements list.
SAI Receive Configuration 3 Register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDFL : Word Flag Configuration
bits : 0 - 4 (5 bit)
access : read-write
RCE0 : Receive Channel Enable
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#00 : 0
Receive data channel N is disabled.
#01 : 1
Receive data channel N is enabled.
End of enumeration elements list.
RCE1 : Receive Channel Enable
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#00 : 0
Receive data channel N is disabled.
#01 : 1
Receive data channel N is enabled.
End of enumeration elements list.
CFR0 : Channel FIFO Reset
bits : 24 - 24 (1 bit)
access : write-only
Enumeration:
#00 : 0
No effect.
#01 : 1
Receive data channel N FIFO is reset.
End of enumeration elements list.
CFR1 : Channel FIFO Reset
bits : 25 - 25 (1 bit)
access : write-only
Enumeration:
#00 : 0
No effect.
#01 : 1
Receive data channel N FIFO is reset.
End of enumeration elements list.
SAI Receive Configuration 4 Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FSD : Frame Sync Direction
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Frame Sync is generated externally in Slave mode.
#1 : 1
Frame Sync is generated internally in Master mode.
End of enumeration elements list.
FSP : Frame Sync Polarity
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Frame sync is active high.
#1 : 1
Frame sync is active low.
End of enumeration elements list.
ONDEM : On Demand Mode
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal frame sync is generated continuously.
#1 : 1
Internal frame sync is generated when the FIFO warning flag is clear.
End of enumeration elements list.
FSE : Frame Sync Early
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Frame sync asserts with the first bit of the frame.
#1 : 1
Frame sync asserts one bit before the first bit of the frame.
End of enumeration elements list.
MF : MSB First
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
LSB is received first.
#1 : 1
MSB is received first.
End of enumeration elements list.
SYWD : Sync Width
bits : 8 - 12 (5 bit)
access : read-write
FRSZ : Frame Size
bits : 16 - 20 (5 bit)
access : read-write
FPACK : FIFO Packing Mode
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
FIFO packing is disabled
#10 : 10
8-bit FIFO packing is enabled
#11 : 11
16-bit FIFO packing is enabled
End of enumeration elements list.
FCOMB : FIFO Combine Mode
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
#00 : 00
FIFO combine mode disabled.
#01 : 01
FIFO combine mode enabled on FIFO writes (from receive shift registers).
#10 : 10
FIFO combine mode enabled on FIFO reads (by software).
#11 : 11
FIFO combine mode enabled on FIFO writes (from receive shift registers) and reads (by software).
End of enumeration elements list.
FCONT : FIFO Continue on Error
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared.
#1 : 1
On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared.
End of enumeration elements list.
SAI Receive Configuration 5 Register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FBT : First Bit Shifted
bits : 8 - 12 (5 bit)
access : read-write
W0W : Word 0 Width
bits : 16 - 20 (5 bit)
access : read-write
WNW : Word N Width
bits : 24 - 28 (5 bit)
access : read-write
SAI Transmit Configuration 3 Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDFL : Word Flag Configuration
bits : 0 - 4 (5 bit)
access : read-write
TCE0 : Transmit Channel Enable
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#00 : 0
Transmit data channel N is disabled.
#01 : 1
Transmit data channel N is enabled.
End of enumeration elements list.
TCE1 : Transmit Channel Enable
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#00 : 0
Transmit data channel N is disabled.
#01 : 1
Transmit data channel N is enabled.
End of enumeration elements list.
CFR0 : Channel FIFO Reset
bits : 24 - 24 (1 bit)
access : write-only
Enumeration:
#00 : 0
No effect.
#01 : 1
Transmit data channel N FIFO is reset.
End of enumeration elements list.
CFR1 : Channel FIFO Reset
bits : 25 - 25 (1 bit)
access : write-only
Enumeration:
#00 : 0
No effect.
#01 : 1
Transmit data channel N FIFO is reset.
End of enumeration elements list.
SAI Transmit FIFO Register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RFP : Read FIFO Pointer
bits : 0 - 3 (4 bit)
access : read-only
WFP : Write FIFO Pointer
bits : 16 - 19 (4 bit)
access : read-only
WCP : Write Channel Pointer
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
No effect.
#1 : 1
FIFO combine is enabled for FIFO writes and this FIFO will be written on the next FIFO write.
End of enumeration elements list.
SAI Receive Mask Register
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RWM0 : Receive Word Mask
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Word N is enabled.
#1 : 1
Word N is masked.
End of enumeration elements list.
RWM1 : Receive Word Mask
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Word N is enabled.
#1 : 1
Word N is masked.
End of enumeration elements list.
RWM2 : Receive Word Mask
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Word N is enabled.
#1 : 1
Word N is masked.
End of enumeration elements list.
RWM3 : Receive Word Mask
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Word N is enabled.
#1 : 1
Word N is masked.
End of enumeration elements list.
RWM4 : Receive Word Mask
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Word N is enabled.
#1 : 1
Word N is masked.
End of enumeration elements list.
RWM5 : Receive Word Mask
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Word N is enabled.
#1 : 1
Word N is masked.
End of enumeration elements list.
RWM6 : Receive Word Mask
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Word N is enabled.
#1 : 1
Word N is masked.
End of enumeration elements list.
RWM7 : Receive Word Mask
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Word N is enabled.
#1 : 1
Word N is masked.
End of enumeration elements list.
RWM8 : Receive Word Mask
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Word N is enabled.
#1 : 1
Word N is masked.
End of enumeration elements list.
RWM9 : Receive Word Mask
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Word N is enabled.
#1 : 1
Word N is masked.
End of enumeration elements list.
RWM10 : Receive Word Mask
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Word N is enabled.
#1 : 1
Word N is masked.
End of enumeration elements list.
RWM11 : Receive Word Mask
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Word N is enabled.
#1 : 1
Word N is masked.
End of enumeration elements list.
RWM12 : Receive Word Mask
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Word N is enabled.
#1 : 1
Word N is masked.
End of enumeration elements list.
RWM13 : Receive Word Mask
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Word N is enabled.
#1 : 1
Word N is masked.
End of enumeration elements list.
RWM14 : Receive Word Mask
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Word N is enabled.
#1 : 1
Word N is masked.
End of enumeration elements list.
RWM15 : Receive Word Mask
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Word N is enabled.
#1 : 1
Word N is masked.
End of enumeration elements list.
RWM16 : Receive Word Mask
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Word N is enabled.
#1 : 1
Word N is masked.
End of enumeration elements list.
RWM17 : Receive Word Mask
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Word N is enabled.
#1 : 1
Word N is masked.
End of enumeration elements list.
RWM18 : Receive Word Mask
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Word N is enabled.
#1 : 1
Word N is masked.
End of enumeration elements list.
RWM19 : Receive Word Mask
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Word N is enabled.
#1 : 1
Word N is masked.
End of enumeration elements list.
RWM20 : Receive Word Mask
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Word N is enabled.
#1 : 1
Word N is masked.
End of enumeration elements list.
RWM21 : Receive Word Mask
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Word N is enabled.
#1 : 1
Word N is masked.
End of enumeration elements list.
RWM22 : Receive Word Mask
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Word N is enabled.
#1 : 1
Word N is masked.
End of enumeration elements list.
RWM23 : Receive Word Mask
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Word N is enabled.
#1 : 1
Word N is masked.
End of enumeration elements list.
RWM24 : Receive Word Mask
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Word N is enabled.
#1 : 1
Word N is masked.
End of enumeration elements list.
RWM25 : Receive Word Mask
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Word N is enabled.
#1 : 1
Word N is masked.
End of enumeration elements list.
RWM26 : Receive Word Mask
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Word N is enabled.
#1 : 1
Word N is masked.
End of enumeration elements list.
RWM27 : Receive Word Mask
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Word N is enabled.
#1 : 1
Word N is masked.
End of enumeration elements list.
RWM28 : Receive Word Mask
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Word N is enabled.
#1 : 1
Word N is masked.
End of enumeration elements list.
RWM29 : Receive Word Mask
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Word N is enabled.
#1 : 1
Word N is masked.
End of enumeration elements list.
RWM30 : Receive Word Mask
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Word N is enabled.
#1 : 1
Word N is masked.
End of enumeration elements list.
RWM31 : Receive Word Mask
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Word N is enabled.
#1 : 1
Word N is masked.
End of enumeration elements list.
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