Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x8 Bytes (0x0)
size : 0x3C byte (0x0)
mem_usage : registers
protection : not protected
Interrupt Status Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WABORTS : WABORTS is an imprecise write fault from the TCM backdoor (AHBS, that is, AHB Slave Interface).
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
#0 : 0
A WABORTS assertion has not occurred
#1 : 1
A WABORTS assertion has occurred
End of enumeration elements list.
WABORTS_OVERRUN : WABORTS is an imprecise write fault from the TCM backdoor (AHBS, that is, AHB Slave Interface).
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
#0 : 0
One or less than one WABORTS assertion has occurred
#1 : 1
More than 1 WABORTS assertion has occurred before clearing ISCR[WABORTS]
End of enumeration elements list.
FIOC : FPU invalid operation interrupt status
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
#0 : 0
No interrupt
#1 : 1
Interrupt occurred
End of enumeration elements list.
FDZC : FPU divide-by-zero interrupt status
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
#0 : 0
No interrupt
#1 : 1
Interrupt occurred
End of enumeration elements list.
FOFC : FPU overflow interrupt status
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
#0 : 0
No interrupt
#1 : 1
Interrupt occurred
End of enumeration elements list.
FUFC : FPU underflow interrupt status
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
#0 : 0
No interrupt
#1 : 1
Interrupt occurred
End of enumeration elements list.
FIXC : FPU inexact interrupt status
bits : 12 - 12 (1 bit)
access : read-only
Enumeration:
#0 : 0
No interrupt
#1 : 1
Interrupt occurred
End of enumeration elements list.
FIDC : FPU input denormal interrupt status
bits : 15 - 15 (1 bit)
access : read-only
Enumeration:
#0 : 0
No interrupt
#1 : 1
Interrupt occurred
End of enumeration elements list.
FIOCE : FPU invalid operation interrupt enable
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable interrupt
#1 : 1
Enable interrupt
End of enumeration elements list.
FDZCE : FPU divide-by-zero interrupt enable
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable interrupt
#1 : 1
Enable interrupt
End of enumeration elements list.
FOFCE : FPU overflow interrupt enable
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable interrupt
#1 : 1
Enable interrupt
End of enumeration elements list.
FUFCE : FPU underflow interrupt enable
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable interrupt
#1 : 1
Enable interrupt
End of enumeration elements list.
FIXCE : FPU inexact interrupt enable
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable interrupt
#1 : 1
Enable interrupt
End of enumeration elements list.
FIDCE : FPU input denormal interrupt enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable interrupt
#1 : 1
Enable interrupt
End of enumeration elements list.
Fault address register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADDRESS : Fault address
bits : 0 - 31 (32 bit)
access : read-only
Fault attributes register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BEDA : Bus error access type
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
Instruction
#1 : 1
Data
End of enumeration elements list.
BEMD : Bus error privilege level
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
User mode
#1 : 1
Supervisor/privileged mode
End of enumeration elements list.
BESZ : Bus error size
bits : 4 - 5 (2 bit)
access : read-only
Enumeration:
#00 : 00
8-bit access
#01 : 01
16-bit access
#10 : 10
32-bit access
End of enumeration elements list.
BEWT : Bus error write
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
Read access
#1 : 1
Write access
End of enumeration elements list.
BEMN : Bus error master number
bits : 8 - 11 (4 bit)
access : read-only
BEOVR : Bus error overrun
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
No bus error overrun
#1 : 1
Bus error overrun occurred. The FADR and FDR registers and the other FATR bits are not updated to reflect this new bus error.
End of enumeration elements list.
Fault data register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : Fault data
bits : 0 - 31 (32 bit)
access : read-only
Process ID register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : M0_PID And M1_PID For MPU
bits : 0 - 7 (8 bit)
access : read-write
Compute Operation Control Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPOREQ : Compute Operation request
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Request is cleared.
#1 : 1
Request Compute Operation.
End of enumeration elements list.
CPOACK : Compute Operation acknowledge
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
Compute operation entry has not completed or compute operation exit has completed.
#1 : 1
Compute operation entry has completed or compute operation exit has not completed.
End of enumeration elements list.
CPOWOI : Compute Operation wakeup on interrupt
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.
#1 : 1
When set, the CPOREQ is cleared on any interrupt or exception vector fetch.
End of enumeration elements list.
Crossbar Switch (AXBS) Slave Configuration
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ASC : Each bit in the ASC field indicates whether there is a corresponding connection to the crossbar switch's slave input port.
bits : 0 - 7 (8 bit)
access : read-only
Enumeration:
#0 : 0
A bus slave connection to AXBS input port n is absent
#1 : 1
A bus slave connection to AXBS input port n is present
End of enumeration elements list.
Crossbar Switch (AXBS) Master Configuration
address_offset : 0xA Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
AMC : Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input port.
bits : 0 - 7 (8 bit)
access : read-only
Enumeration:
#0 : 0
A bus master connection to AXBS input port n is absent
#1 : 1
A bus master connection to AXBS input port n is present
End of enumeration elements list.
Control Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRAMUAP : SRAM_U arbitration priority
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
Round robin
#01 : 01
Special round robin (favors SRAM backoor accesses over the processor)
#10 : 10
Fixed priority. Processor has highest, backdoor has lowest
#11 : 11
Fixed priority. Backdoor has highest, processor has lowest
End of enumeration elements list.
SRAMUWP : SRAM_U write protect
bits : 26 - 26 (1 bit)
access : read-write
SRAMLAP : SRAM_L arbitration priority
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
#00 : 00
Round robin
#01 : 01
Special round robin (favors SRAM backoor accesses over the processor)
#10 : 10
Fixed priority. Processor has highest, backdoor has lowest
#11 : 11
Fixed priority. Backdoor has highest, processor has lowest
End of enumeration elements list.
SRAMLWP : SRAM_L Write Protect
bits : 30 - 30 (1 bit)
access : read-write
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.