Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x42 Bytes (0x0)
size : 0x16 byte (0x0)
mem_usage : registers
protection : not protected
Control Register
address_offset : 0x42 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RC : Refresh count
bits : 0 - 8 (9 bit)
access : read-write
RTIM : Refresh timing
bits : 9 - 10 (2 bit)
access : read-write
Enumeration:
#00 : 00
3 clocks
#01 : 01
6 clocks
#10 : 10
9 clocks
#11 : 11
9 clocks
End of enumeration elements list.
IS : Initiate self-refresh command.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Take no action or issue a selfx command to exit self refresh.
#1 : 1
SDRAM controller sends a self command to both SDRAM blocks to put them in low-power, self-refresh state where they remain until IS is cleared. When IS is cleared, the controller sends a selfx command for the SDRAMs to exit self-refresh. The refresh counter is suspended while the SDRAMs are in self-refresh; the SDRAM controls the refresh period.
End of enumeration elements list.
Address and Control Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IP : Initiate precharge all (pall) command.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Take no action.
#1 : 1
A pall command is sent to the associated SDRAM block. During initialization, this command is executed after all DRAM controller registers are programmed. After IP is set, the next write to an appropriate SDRAM address generates the pall command to the SDRAM block.
End of enumeration elements list.
PS : Port size.
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 00
32-bit port
#01 : 01
8-bit port
#10 : 10
16-bit port
#11 : 11
16-bit port
End of enumeration elements list.
IMRS : Initiate mode register set (mrs) command.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Take no action
#1 : 1
Initiate mrs command
End of enumeration elements list.
CBM : Command bit location
bits : 8 - 10 (3 bit)
access : read-write
CASL : CAS Latency
bits : 12 - 13 (2 bit)
access : read-write
RE : Refresh enable
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not refresh associated DRAM block
#1 : 1
Refresh associated DRAM block
End of enumeration elements list.
BA : Base address register.
bits : 18 - 31 (14 bit)
access : read-write
Control Mask
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
V : Valid.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not decode DRAM accesses.
#1 : 1
Registers controlling the DRAM block are initialized; DRAM accesses can be decoded
End of enumeration elements list.
WP : Write protect.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Allow write accesses
#1 : 1
Ignore write accesses. The DRAM controller ignores write accesses to the memory block and an address exception occurs. Write accesses to a write-protected DRAM region are compared in the chip select module for a hit. If no hit occurs, an external bus cycle is generated. If this external bus cycle is not acknowledged, an access exception occurs.
End of enumeration elements list.
BAM : Base address mask.
bits : 18 - 31 (14 bit)
access : read-write
Enumeration:
#0 : 0
The associated address bit is used in decoding the DRAM hit to a memory block
#1 : 1
The associated address bit is not used in the DRAM hit decode
End of enumeration elements list.
Address and Control Register
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IP : Initiate precharge all (pall) command.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Take no action.
#1 : 1
A pall command is sent to the associated SDRAM block. During initialization, this command is executed after all DRAM controller registers are programmed. After IP is set, the next write to an appropriate SDRAM address generates the pall command to the SDRAM block.
End of enumeration elements list.
PS : Port size.
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 00
32-bit port
#01 : 01
8-bit port
#10 : 10
16-bit port
#11 : 11
16-bit port
End of enumeration elements list.
IMRS : Initiate mode register set (mrs) command.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Take no action
#1 : 1
Initiate mrs command
End of enumeration elements list.
CBM : Command bit location
bits : 8 - 10 (3 bit)
access : read-write
CASL : CAS Latency
bits : 12 - 13 (2 bit)
access : read-write
RE : Refresh enable
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not refresh associated DRAM block
#1 : 1
Refresh associated DRAM block
End of enumeration elements list.
BA : Base address register.
bits : 18 - 31 (14 bit)
access : read-write
Control Mask
address_offset : 0xEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
V : Valid.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not decode DRAM accesses.
#1 : 1
Registers controlling the DRAM block are initialized; DRAM accesses can be decoded
End of enumeration elements list.
WP : Write protect.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Allow write accesses
#1 : 1
Ignore write accesses. The DRAM controller ignores write accesses to the memory block and an address exception occurs. Write accesses to a write-protected DRAM region are compared in the chip select module for a hit. If no hit occurs, an external bus cycle is generated. If this external bus cycle is not acknowledged, an access exception occurs.
End of enumeration elements list.
BAM : Base address mask.
bits : 18 - 31 (14 bit)
access : read-write
Enumeration:
#0 : 0
The associated address bit is used in decoding the DRAM hit to a memory block
#1 : 1
The associated address bit is not used in the DRAM hit decode
End of enumeration elements list.
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