Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x410 byte (0x0)
mem_usage : registers
protection : not protected
Module Configuration Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWRSTSD : Software reset for serial flash domain
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No action
#1 : 1
Serial Flash domain flops are reset. Does not reset configuration registers. It is advisable to reset both the serial flash domain and AHB domain at the same time. Resetting only one domain might lead to side effects. The software resets need the clock to be running to propagate to the design. The MCR[MDIS] should therefore be set to 0 when the software reset bits are asserted. Also, before they can be deasserted again (by setting MCR[SWRSTSD] to 0), it is recommended to set the MCR[MDIS] bit to 1. Once the software resets have been deasserted, the normal operation can be started by setting the MCR[MDIS] bit to 0.
End of enumeration elements list.
SWRSTHD : Software reset for AHB domain
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No action
#1 : 1
AHB domain flops are reset. Does not reset configuration registers. It is advisable to reset both the serial flash domain and AHB domain at the same time. Resetting only one domain might lead to side effects. The software resets need the clock to be running to propagate to the design. The MCR[MDIS] should therefore be set to 0 when the software reset bits are asserted. Also, before they can be deasserted again (by setting MCR[SWRSTHD] to 0), it is recommended to set the MCR[MDIS] bit to 1. Once the software resets have been deasserted, the normal operation can be started by setting the MCR[MDIS] bit to 0.
End of enumeration elements list.
END_CFG : Defines the endianness of the QuadSPI module. For more details refer to Byte Ordering Endianess
bits : 2 - 3 (2 bit)
access : read-write
DQS_LAT_EN : DQS Latency Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
DQS Latency disabled
#1 : 1
DQS feature with latency included enabled
End of enumeration elements list.
DQS_EN : DQS enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
DQS disabled.
#1 : 1
DQS enabled. When enabled, the incoming data is sampled on both the edges of DQS input when QSPI_MCR[DDR_EN] is set, else, on only one edge when QSPI_MCR[DDR_EN] is 0. The QSPI_SMPR[DDR_SMP] values are ignored.
End of enumeration elements list.
DDR_EN : DDR mode enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
2x and 4x clocks are disabled for SDR instructions only
#1 : 1
2x and 4x clocks are enabled supports both SDR and DDR instruction.
End of enumeration elements list.
CLR_RXF : Clear RX FIFO. Invalidates the RX Buffer. This is a self-clearing field.
bits : 10 - 10 (1 bit)
access : write-only
Enumeration:
#0 : 0
No action.
#1 : 1
Read and write pointers of the RX Buffer are reset to 0. QSPI_RBSR[RDBFL] is reset to 0.
End of enumeration elements list.
CLR_TXF : Clear TX FIFO/Buffer. Invalidates the TX Buffer content. This is a self-clearing field.
bits : 11 - 11 (1 bit)
access : write-only
Enumeration:
#0 : 0
No action.
#1 : 1
Read and write pointers of the TX Buffer are reset to 0. QSPI_TBSR[TRCTR] is reset to 0.
End of enumeration elements list.
MDIS : Module Disable
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enable QuadSPI clocks.
#1 : 1
Allow external logic to disable QuadSPI clocks.
End of enumeration elements list.
ISD2FA : Idle Signal Drive IOFA[2] Flash A
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
IOFA[2] is driven to logic L
#1 : 1
IOFA[2] is driven to logic H
End of enumeration elements list.
ISD3FA : Idle Signal Drive IOFA[3] Flash A
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
IOFA[3] is driven to logic L
#1 : 1
IOFA[3] is driven to logic H
End of enumeration elements list.
ISD2FB : Idle Signal Drive IOFB[2] Flash B
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
IOFB[2] is driven to logic L
#1 : 1
IOFB[2] is driven to logic H
End of enumeration elements list.
ISD3FB : Idle Signal Drive IOFB[3] Flash B
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
IOFB[3] is driven to logic L
#1 : 1
IOFB[3] is driven to logic H
End of enumeration elements list.
SCLKCFG : Serial Clock Configuration
bits : 24 - 31 (8 bit)
access : read-write
Buffer0 Configuration Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MSTRID : Master ID
bits : 0 - 3 (4 bit)
access : read-write
ADATSZ : AHB data transfer size
bits : 8 - 14 (7 bit)
access : read-write
HP_EN : High Priority Enable
bits : 31 - 31 (1 bit)
access : read-write
Serial Flash Address Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SFADR : Serial Flash Address. The register content is used as byte address for all following IP Commands.
bits : 0 - 31 (32 bit)
access : read-write
Serial Flash Address Configuration Register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAS : Column Address Space
bits : 0 - 3 (4 bit)
access : read-write
WA : Word Addressable
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Byte addressable serial flash mode.
#1 : 1
Word (2 byte) addressable serial flash mode.
End of enumeration elements list.
RX Buffer Data Register
address_offset : 0x1054 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXDATA : RX Data
bits : 0 - 31 (32 bit)
access : read-only
Sampling Register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HSENA : Half Speed serial flash clock Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable divide by 2 of serial flash clock for half speed commands
#1 : 1
Enable divide by 2 of serial flash clock for half speed commands
End of enumeration elements list.
HSPHS : Half Speed Phase selection for SDR instructions.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Select sampling at non-inverted clock
#1 : 1
Select sampling at inverted clock
End of enumeration elements list.
HSDLY : Half Speed Delay selection for SDR instructions.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
One clock cycle delay
#1 : 1
Two clock cycle delay
End of enumeration elements list.
FSPHS : Full Speed Phase selection for SDR instructions.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Select sampling at non-inverted clock
#1 : 1
Select sampling at inverted clock. Please refer to Supported read modes for its usage. FSPHS programming is only supported with internal non-DQS SDR sampling. It must be '0' in other sampling modes.
End of enumeration elements list.
FSDLY : Full Speed Delay selection for SDR instructions. Select the delay with respect to the reference edge for the sample point valid for full speed commands.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
One clock cycle delay
#1 : 1
Two clock cycles delay. Please refer to Supported read modes for its usage. It is ignored when using non-DQS DDR instructions.
End of enumeration elements list.
DDRSMP : DDR Sampling point
bits : 16 - 18 (3 bit)
access : read-write
RX Buffer Status Register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDBFL : RX Buffer Fill Level
bits : 8 - 12 (5 bit)
access : read-only
RDCTR : Read Counter
bits : 16 - 31 (16 bit)
access : read-only
RX Buffer Control Register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WMRK : RX Buffer Watermark
bits : 0 - 3 (4 bit)
access : read-write
RXBRD : RX Buffer Readout. This field specifies the access scheme for the RX Buffer readout.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
RX Buffer content is read using the AHB Bus registers QSPI_ARDB0 to QSPI_ARDB15 . For details, refer to Exclusive Access to Serial Flash for AHB Commands.
#1 : 1
RX Buffer content is read using the IP Bus registers QSPI_RBDR0 to QSPI_RBDR15 .
End of enumeration elements list.
RX Buffer Data Register
address_offset : 0x1270 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXDATA : RX Data
bits : 0 - 31 (32 bit)
access : read-only
Look-up Table register
address_offset : 0x1288 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Buffer1 Configuration Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MSTRID : Master ID
bits : 0 - 3 (4 bit)
access : read-write
ADATSZ : AHB data transfer size
bits : 8 - 14 (7 bit)
access : read-write
RX Buffer Data Register
address_offset : 0x1490 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXDATA : RX Data
bits : 0 - 31 (32 bit)
access : read-only
TX Buffer Status Register
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TRBFL : TX Buffer Fill Level
bits : 8 - 12 (5 bit)
access : read-only
TRCTR : Transmit Counter
bits : 16 - 31 (16 bit)
access : read-only
TX Buffer Data Register
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXDATA : TX Data On write access the data is written into the next available entry of the TX Buffer and the QPSI_TBSR[TRBFL] field is updated accordingly
bits : 0 - 31 (32 bit)
access : read-write
Tx Buffer Control Register
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WMRK : Determines the watermark for the TX Buffer
bits : 0 - 3 (4 bit)
access : read-write
Look-up Table register
address_offset : 0x15AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Status Register
address_offset : 0x15C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BUSY : Module Busy
bits : 0 - 0 (1 bit)
access : read-only
IP_ACC : IP Access. Asserted when transaction currently executed was initiated by IP bus.
bits : 1 - 1 (1 bit)
access : read-only
AHB_ACC : AHB Access. Asserted when the transaction currently executed was initiated by AHB bus.
bits : 2 - 2 (1 bit)
access : read-only
AHBGNT : AHB Command priority Granted: Asserted when another module has been granted priority of AHB Commands against IP Commands
bits : 5 - 5 (1 bit)
access : read-only
AHBTRN : AHB Access Transaction pending
bits : 6 - 6 (1 bit)
access : read-only
AHB0NE : AHB 0 Buffer Not Empty. Asserted when AHB 0 buffer contains data.
bits : 7 - 7 (1 bit)
access : read-only
AHB1NE : AHB 1 Buffer Not Empty. Asserted when AHB 1 buffer contains data.
bits : 8 - 8 (1 bit)
access : read-only
AHB2NE : AHB 2 Buffer Not Empty. Asserted when AHB 2 buffer contains data.
bits : 9 - 9 (1 bit)
access : read-only
AHB3NE : AHB 3 Buffer Not Empty. Asserted when AHB 3 buffer contains data.
bits : 10 - 10 (1 bit)
access : read-only
AHB0FUL : AHB 0 Buffer Full. Asserted when AHB 0 buffer is full.
bits : 11 - 11 (1 bit)
access : read-only
AHB1FUL : AHB 1 Buffer Full. Asserted when AHB 1 buffer is full.
bits : 12 - 12 (1 bit)
access : read-only
AHB2FUL : AHB 2 Buffer Full. Asserted when AHB 2 buffer is full.
bits : 13 - 13 (1 bit)
access : read-only
AHB3FUL : AHB 3 Buffer Full. Asserted when AHB 3 buffer is full.
bits : 14 - 14 (1 bit)
access : read-only
RXWE : RX Buffer Watermark Exceeded
bits : 16 - 16 (1 bit)
access : read-only
RXFULL : RX Buffer Full
bits : 19 - 19 (1 bit)
access : read-only
RXDMA : RX Buffer DMA. Asserted when RX Buffer read out via DMA is active i.e DMA is requested or running.
bits : 23 - 23 (1 bit)
access : read-only
TXEDA : Tx Buffer Enough Data Available
bits : 24 - 24 (1 bit)
access : read-only
TXWA : TX Buffer watermark Available
bits : 25 - 25 (1 bit)
access : read-only
TXDMA : TXDMA
bits : 26 - 26 (1 bit)
access : read-only
TXFULL : TX Buffer Full. Asserted when no more data can be stored.
bits : 27 - 27 (1 bit)
access : read-only
DLPSMP : Data learning pattern sampling point
bits : 29 - 31 (3 bit)
access : read-only
Flag Register
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TFF : IP Command Transaction Finished Flag
bits : 0 - 0 (1 bit)
access : read-write
IPGEF : IP Command Trigger during AHB Grant Error Flag
bits : 4 - 4 (1 bit)
access : read-write
IPIEF : IP Command Trigger could not be executed Error Flag
bits : 6 - 6 (1 bit)
access : read-write
IPAEF : IP Command Trigger during AHB Access Error Flag
bits : 7 - 7 (1 bit)
access : read-write
IUEF : IP Command Usage Error Flag
bits : 11 - 11 (1 bit)
access : read-write
ABOF : AHB Buffer Overflow Flag
bits : 12 - 12 (1 bit)
access : read-write
AIBSEF : AHB Illegal Burst Size Error Flag
bits : 13 - 13 (1 bit)
access : read-write
AITEF : AHB Illegal transaction error flag
bits : 14 - 14 (1 bit)
access : read-write
ABSEF : AHB Sequence Error Flag
bits : 15 - 15 (1 bit)
access : read-write
RBDF : RX Buffer Drain Flag
bits : 16 - 16 (1 bit)
access : read-write
RBOF : RX Buffer Overflow Flag
bits : 17 - 17 (1 bit)
access : read-write
ILLINE : Illegal Instruction Error Flag
bits : 23 - 23 (1 bit)
access : read-write
TBUF : TX Buffer Underrun Flag
bits : 26 - 26 (1 bit)
access : read-write
TBFF : TX Buffer Fill Flag
bits : 27 - 27 (1 bit)
access : read-write
DLPFF : Data Learning Pattern Failure Flag
bits : 31 - 31 (1 bit)
access : read-write
Interrupt and DMA Request Select and Enable Register
address_offset : 0x164 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TFIE : Transaction Finished Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No TFF interrupt will be generated
#1 : 1
TFF interrupt will be generated
End of enumeration elements list.
IPGEIE : IP Command Trigger during AHB Grant Error Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
No IPGEF interrupt will be generated
#1 : 1
IPGEF interrupt will be generated
End of enumeration elements list.
IPIEIE : IP Command Trigger during IP Access Error Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
No IPIEF interrupt will be generated
#1 : 1
IPIEF interrupt will be generated
End of enumeration elements list.
IPAEIE : IP Command Trigger during AHB Access Error Interrupt Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
No IPAEF interrupt will be generated
#1 : 1
IPAEF interrupt will be generated
End of enumeration elements list.
IUEIE : IP Command Usage Error Interrupt Enable
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
No IUEF interrupt will be generated
#1 : 1
IUEF interrupt will be generated
End of enumeration elements list.
ABOIE : AHB Buffer Overflow Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
No ABOF interrupt will be generated
#1 : 1
ABOF interrupt will be generated
End of enumeration elements list.
AIBSIE : AHB Illegal Burst Size Interrupt Enable
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
No AIBSEF interrupt will be generated
#1 : 1
AIBSEF interrupt will be generated
End of enumeration elements list.
AITIE : AHB Illegal transaction interrupt enable.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
No AITEF interrupt will be generated
#1 : 1
AITEF interrupt will be generated
End of enumeration elements list.
ABSEIE : AHB Sequence Error Interrupt Enable: Triggered by ABSEF flags of QSPI_FR
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
No ABSEF interrupt will be generated
#1 : 1
ABSEF interrupt will be generated
End of enumeration elements list.
RBDIE : RX Buffer Drain Interrupt Enable: Enables generation of IRQ requests for RX Buffer Drain
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
No RBDF interrupt will be generated
#1 : 1
RBDF Interrupt will be generated
End of enumeration elements list.
RBOIE : RX Buffer Overflow Interrupt Enable
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
No RBOF interrupt will be generated
#1 : 1
RBOF interrupt will be generated
End of enumeration elements list.
RBDDE : RX Buffer Drain DMA Enable: Enables generation of DMA requests for RX Buffer Drain
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
No DMA request will be generated
#1 : 1
DMA request will be generated
End of enumeration elements list.
ILLINIE : Illegal Instruction Error Interrupt Enable. Triggered by ILLINE flag in QSPI_FR
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
No ILLINE interrupt will be generated
#1 : 1
ILLINE interrupt will be generated
End of enumeration elements list.
TBFDE : TX Buffer Fill DMA Enable
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
No DMA request will be generated
#1 : 1
DMA request will be generated
End of enumeration elements list.
TBUIE : TX Buffer Underrun Interrupt Enable
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
No TBUF interrupt will be generated
#1 : 1
TBUF interrupt will be generated
End of enumeration elements list.
TBFIE : TX Buffer Fill Interrupt Enable
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
No TBFF interrupt will be generated
#1 : 1
TBFF interrupt will be generated
End of enumeration elements list.
DLPFIE : Data Learning Pattern Failure Interrupt enable . Triggered by DLPFF flag in QSPI_FR register
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
No DLPFF interrupt will be generated
#1 : 1
DLPFF interrupt will be generated
End of enumeration elements list.
Sequence Suspend Status Register
address_offset : 0x168 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SUSPND : When set, it signifies that a sequence is in suspended state
bits : 0 - 0 (1 bit)
access : read-only
SPDBUF : Suspended Buffer: Provides the suspended buffer number. Valid only when SUSPND is set to 1'b1
bits : 6 - 7 (2 bit)
access : read-only
DATLFT : Data left: Provides information about the amount of data left to be read in the suspended sequence
bits : 9 - 14 (6 bit)
access : read-only
RX Buffer Data Register
address_offset : 0x16B4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXDATA : RX Data
bits : 0 - 31 (32 bit)
access : read-only
Sequence Pointer Clear Register
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BFPTRC : Buffer Pointer Clear: 1: Clears the sequence pointer for AHB accesses as defined in QuadSPI_BFGENCR
bits : 0 - 0 (1 bit)
access : write-only
IPPTRC : IP Pointer Clear: 1: Clears the sequence pointer for IP accesses as defined in QuadSPI_IPCR This is a self-clearing field
bits : 8 - 8 (1 bit)
access : write-only
Buffer2 Configuration Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MSTRID : Master ID
bits : 0 - 3 (4 bit)
access : read-write
ADATSZ : AHB data transfer size
bits : 8 - 14 (7 bit)
access : read-write
Serial Flash A1 Top Address
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TPADA1 : Top address for Serial Flash A1. In effect, TPADxx is the first location of the next memory.
bits : 10 - 31 (22 bit)
access : read-write
Serial Flash A2 Top Address
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TPADA2 : Top address for Serial Flash A2. In effect, TPxxAD is the first location of the next memory.
bits : 10 - 31 (22 bit)
access : read-write
Serial Flash B1 Top Address
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TPADB1 : Top address for Serial Flash B1.In effect, TPxxAD is the first location of the next memory.
bits : 10 - 31 (22 bit)
access : read-write
Serial Flash B2 Top Address
address_offset : 0x18C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TPADB2 : Top address for Serial Flash B2. In effect, TPxxAD is the first location of the next memory.
bits : 10 - 31 (22 bit)
access : read-write
Look-up Table register
address_offset : 0x18D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
RX Buffer Data Register
address_offset : 0x18DC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXDATA : RX Data
bits : 0 - 31 (32 bit)
access : read-only
Data Learn Pattern Register
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLPV : Data Learning Pattern Value: This value is used for data learning in DDR and DQS mode
bits : 0 - 31 (32 bit)
access : read-write
RX Buffer Data Register
address_offset : 0x1B08 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXDATA : RX Data
bits : 0 - 31 (32 bit)
access : read-only
Buffer3 Configuration Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MSTRID : Master ID
bits : 0 - 3 (4 bit)
access : read-write
ADATSZ : AHB data transfer size
bits : 8 - 14 (7 bit)
access : read-write
ALLMST : All master enable
bits : 31 - 31 (1 bit)
access : read-write
Look-up Table register
address_offset : 0x1C00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
RX Buffer Data Register
address_offset : 0x1D38 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXDATA : RX Data
bits : 0 - 31 (32 bit)
access : read-only
Look-up Table register
address_offset : 0x1F30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
RX Buffer Data Register
address_offset : 0x1F6C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXDATA : RX Data
bits : 0 - 31 (32 bit)
access : read-only
Buffer Generic Configuration Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEQID : Points to a sequence in the Look-up-table
bits : 12 - 15 (4 bit)
access : read-write
PAR_EN : When set, a transaction to two serial flash devices is triggered in parallel mode
bits : 16 - 16 (1 bit)
access : read-write
RX Buffer Data Register
address_offset : 0x21A4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXDATA : RX Data
bits : 0 - 31 (32 bit)
access : read-only
Look-up Table register
address_offset : 0x2264 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
RX Buffer Data Register
address_offset : 0x23E0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXDATA : RX Data
bits : 0 - 31 (32 bit)
access : read-only
SOC Configuration Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
QSPISRC : QSPI clock source select
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#000 : 000
Core/system clock
#001 : 001
MCGFLL clock
#010 : 010
MCGPLL clock
#011 : 011
MCGPLL 2x clock (DDR mode specific)
#100 : 100
IRC48M clock
#101 : 101
OSCERCLK clock
#110 : 110
MCGIRCLK clock
End of enumeration elements list.
DQSLPEN : When this bit is set the internal generated DQS is selected and looped back to QuadSPI, without going to DQS pad. DQSPADLPEN should be cleared when this bit is set.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
DQS loop back is disabled
#1 : 1
DQS loop back is enabled
End of enumeration elements list.
DQSPADLPEN : When this bit is set the internal generated DQS will be sent to the DQS pad first and then looped back to QuadSPI. DQSLPEN should be cleared when this bit is set.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
DQS loop back from DQS pad is disabled
#1 : 1
DQS loop back from DQS pad is enabled
End of enumeration elements list.
DQSPHASEL : Select phase shift for internal DQS generation. These bits are always zero in SDR mode.
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
#00 : 00
No phase shift
#01 : 01
Select 45 degree phase shift
#10 : 10
Select 90 degree phase shift
#11 : 11
Select 135 degree phase shift
End of enumeration elements list.
DQSINVSEL : Select clock source for internal DQS generation
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Use 1x internal reference clock for the DQS generation
#1 : 1
Use inverse 1x internal reference clock for the DQS generation
End of enumeration elements list.
CK2EN : Flash CK2 clock pin enable
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
CK2 flash clock is disabled
#1 : 1
CK2 flash clock is enabled
End of enumeration elements list.
DIFFCKEN : Differential flash clock pins enable
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Differential flash clock is disabled
#1 : 1
Differential flash clock is enabled
End of enumeration elements list.
OCTEN : Octal data pins enable
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
QSPI0B_DATAx pins are assigned to QSPI Port B
#1 : 1
QSPI0B_DATAx pins are assigned to QSPI Port A
End of enumeration elements list.
DLYTAPSELA : Delay chain tap number selection for QSPI Port A DQS
bits : 16 - 21 (6 bit)
access : read-write
Enumeration:
#0 : 000000
Select 1 delay chain tap
#1 : 000001
Select 2 delay chain tap
#10 : 0000010
Select 3 delay chain tap
#11 : 0000011
Select 4 delay chain tap
#100 : 00000100
Select 5 delay chain tap
#101 : 00000101
Select 6 delay chain tap
#110 : 00000110
Select 7 delay chain tap
#111 : 00000111
Select 8 delay chain tap
#1000 : 000001000
Select 9 delay chain tap
#1001 : 000001001
Select 10 delay chain tap
#1010 : 000001010
Select 11 delay chain tap
#1011 : 000001011
Select 12 delay chain tap
#1100 : 000001100
Select 13 delay chain tap
#1101 : 000001101
Select 14 delay chain tap
#1110 : 000001110
Select 15 delay chain tap
#1111 : 000001111
Select 16 delay chain tap
#10000 : 0000010000
Select 17 delay chain tap
#10001 : 0000010001
Select 18 delay chain tap
#10010 : 0000010010
Select 19 delay chain tap
#10011 : 0000010011
Select 20 delay chain tap
#10100 : 0000010100
Select 21 delay chain tap
#10101 : 0000010101
Select 22 delay chain tap
#10110 : 0000010110
Select 23 delay chain tap
#10111 : 0000010111
Select 24 delay chain tap
#11000 : 0000011000
Select 25 delay chain tap
#11001 : 0000011001
Select 26 delay chain tap
#11010 : 0000011010
Select 27 delay chain tap
#11011 : 0000011011
Select 28 delay chain tap
#11100 : 0000011100
Select 29 delay chain tap
#11101 : 0000011101
Select 30 delay chain tap
#11110 : 0000011110
Select 31 delay chain tap
#11111 : 0000011111
Select 32 delay chain tap
#100000 : 00000100000
Select 33 delay chain tap
#100001 : 00000100001
Select 34 delay chain tap
#100010 : 00000100010
Select 35 delay chain tap
#100011 : 00000100011
Select 36 delay chain tap
#100100 : 00000100100
Select 37 delay chain tap
#100101 : 00000100101
Select 38 delay chain tap
#100110 : 00000100110
Select 39 delay chain tap
#100111 : 00000100111
Select 40 delay chain tap
#101000 : 00000101000
Select 41 delay chain tap
#101001 : 00000101001
Select 42 delay chain tap
#101010 : 00000101010
Select 43 delay chain tap
#101011 : 00000101011
Select 44 delay chain tap
#101100 : 00000101100
Select 45 delay chain tap
#101101 : 00000101101
Select 46 delay chain tap
#101110 : 00000101110
Select 47 delay chain tap
#101111 : 00000101111
Select 48 delay chain tap
#110000 : 00000110000
Select 49 delay chain tap
#110001 : 00000110001
Select 50 delay chain tap
#110010 : 00000110010
Select 51 delay chain tap
#110011 : 00000110011
Select 52 delay chain tap
#110100 : 00000110100
Select 53 delay chain tap
#110101 : 00000110101
Select 54 delay chain tap
#110110 : 00000110110
Select 55 delay chain tap
#110111 : 00000110111
Select 56 delay chain tap
#111000 : 00000111000
Select 57 delay chain tap
#111001 : 00000111001
Select 58 delay chain tap
#111010 : 00000111010
Select 59 delay chain tap
#111011 : 00000111011
Select 60 delay chain tap
#111100 : 00000111100
Select 61 delay chain tap
#111101 : 00000111101
Select 62 delay chain tap
#111110 : 00000111110
Select 63 delay chain tap
#111111 : 00000111111
Select 64 delay chain tap
End of enumeration elements list.
DLYTAPSELB : Delay chain tap number selection for QSPI Port B DQS
bits : 24 - 29 (6 bit)
access : read-write
Enumeration:
#0 : 000000
Select 1 delay chain tap
#1 : 000001
Select 2 delay chain tap
#10 : 0000010
Select 3 delay chain tap
#11 : 0000011
Select 4 delay chain tap
#100 : 00000100
Select 5 delay chain tap
#101 : 00000101
Select 6 delay chain tap
#110 : 00000110
Select 7 delay chain tap
#111 : 00000111
Select 8 delay chain tap
#1000 : 000001000
Select 9 delay chain tap
#1001 : 000001001
Select 10 delay chain tap
#1010 : 000001010
Select 11 delay chain tap
#1011 : 000001011
Select 12 delay chain tap
#1100 : 000001100
Select 13 delay chain tap
#1101 : 000001101
Select 14 delay chain tap
#1110 : 000001110
Select 15 delay chain tap
#1111 : 000001111
Select 16 delay chain tap
#10000 : 0000010000
Select 17 delay chain tap
#10001 : 0000010001
Select 18 delay chain tap
#10010 : 0000010010
Select 19 delay chain tap
#10011 : 0000010011
Select 20 delay chain tap
#10100 : 0000010100
Select 21 delay chain tap
#10101 : 0000010101
Select 22 delay chain tap
#10110 : 0000010110
Select 23 delay chain tap
#10111 : 0000010111
Select 24 delay chain tap
#11000 : 0000011000
Select 25 delay chain tap
#11001 : 0000011001
Select 26 delay chain tap
#11010 : 0000011010
Select 27 delay chain tap
#11011 : 0000011011
Select 28 delay chain tap
#11100 : 0000011100
Select 29 delay chain tap
#11101 : 0000011101
Select 30 delay chain tap
#11110 : 0000011110
Select 31 delay chain tap
#11111 : 0000011111
Select 32 delay chain tap
#100000 : 00000100000
Select 33 delay chain tap
#100001 : 00000100001
Select 34 delay chain tap
#100010 : 00000100010
Select 35 delay chain tap
#100011 : 00000100011
Select 36 delay chain tap
#100100 : 00000100100
Select 37 delay chain tap
#100101 : 00000100101
Select 38 delay chain tap
#100110 : 00000100110
Select 39 delay chain tap
#100111 : 00000100111
Select 40 delay chain tap
#101000 : 00000101000
Select 41 delay chain tap
#101001 : 00000101001
Select 42 delay chain tap
#101010 : 00000101010
Select 43 delay chain tap
#101011 : 00000101011
Select 44 delay chain tap
#101100 : 00000101100
Select 45 delay chain tap
#101101 : 00000101101
Select 46 delay chain tap
#101110 : 00000101110
Select 47 delay chain tap
#101111 : 00000101111
Select 48 delay chain tap
#110000 : 00000110000
Select 49 delay chain tap
#110001 : 00000110001
Select 50 delay chain tap
#110010 : 00000110010
Select 51 delay chain tap
#110011 : 00000110011
Select 52 delay chain tap
#110100 : 00000110100
Select 53 delay chain tap
#110101 : 00000110101
Select 54 delay chain tap
#110110 : 00000110110
Select 55 delay chain tap
#110111 : 00000110111
Select 56 delay chain tap
#111000 : 00000111000
Select 57 delay chain tap
#111001 : 00000111001
Select 58 delay chain tap
#111010 : 00000111010
Select 59 delay chain tap
#111011 : 00000111011
Select 60 delay chain tap
#111100 : 00000111100
Select 61 delay chain tap
#111101 : 00000111101
Select 62 delay chain tap
#111110 : 00000111110
Select 63 delay chain tap
#111111 : 00000111111
Select 64 delay chain tap
End of enumeration elements list.
Look-up Table register
address_offset : 0x259C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Look-up Table register
address_offset : 0x28D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Look-up Table register
address_offset : 0x2C18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Look-up Table register
address_offset : 0x2F5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Buffer0 Top Index Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TPINDX0 : Top index of buffer 0.
bits : 3 - 31 (29 bit)
access : read-write
LUT Key Register
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEY : The key to lock or unlock the LUT. The KEY is 0x5AF05AF0. The read value is always 0x5AF05AF0
bits : 0 - 31 (32 bit)
access : read-write
LUT Lock Configuration Register
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOCK : Locks the LUT when the following condition is met: This register is written just after the LUTKEYLUT Key Register The LUT key register was written with 0x5AF05AF0 key
bits : 0 - 0 (1 bit)
access : read-write
UNLOCK : Unlocks the LUT when the following two conditions are met: 1
bits : 1 - 1 (1 bit)
access : read-write
Look-up Table register
address_offset : 0x32A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Buffer1 Top Index Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TPINDX1 : Top index of buffer 1.
bits : 3 - 31 (29 bit)
access : read-write
Look-up Table register
address_offset : 0x35F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Buffer2 Top Index Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TPINDX2 : Top index of buffer 2.
bits : 3 - 31 (29 bit)
access : read-write
Look-up Table register
address_offset : 0x3940 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Look-up Table register
address_offset : 0x3C94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Look-up Table register
address_offset : 0x3FEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
RX Buffer Data Register
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXDATA : RX Data
bits : 0 - 31 (32 bit)
access : read-only
Look-up Table register
address_offset : 0x4348 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Look-up Table register
address_offset : 0x46A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Look-up Table register
address_offset : 0x4A0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Look-up Table register
address_offset : 0x4D74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Look-up Table register
address_offset : 0x50E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Look-up Table register
address_offset : 0x5450 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Look-up Table register
address_offset : 0x57C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Look-up Table register
address_offset : 0x5B3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Look-up Table register
address_offset : 0x5EB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
RX Buffer Data Register
address_offset : 0x604 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXDATA : RX Data
bits : 0 - 31 (32 bit)
access : read-only
Look-up Table register
address_offset : 0x620 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Look-up Table register
address_offset : 0x6238 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Look-up Table register
address_offset : 0x65BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Look-up Table register
address_offset : 0x6944 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Look-up Table register
address_offset : 0x6CD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Look-up Table register
address_offset : 0x7060 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Look-up Table register
address_offset : 0x73F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Look-up Table register
address_offset : 0x778C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Look-up Table register
address_offset : 0x7B28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Look-up Table register
address_offset : 0x7EC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
IP Configuration Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IDATSZ : IP data transfer size. Defines the data transfer size in bytes of the IP command.
bits : 0 - 15 (16 bit)
access : read-write
PAR_EN : When set, a transaction to two serial flash devices is triggered in parallel mode
bits : 16 - 16 (1 bit)
access : read-write
SEQID : Points to a sequence in the Look-up table
bits : 24 - 27 (4 bit)
access : read-write
RX Buffer Data Register
address_offset : 0x80C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXDATA : RX Data
bits : 0 - 31 (32 bit)
access : read-only
Look-up Table register
address_offset : 0x826C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Look-up Table register
address_offset : 0x8614 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Look-up Table register
address_offset : 0x89C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Look-up Table register
address_offset : 0x8D70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Look-up Table register
address_offset : 0x9124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Look-up Table register
address_offset : 0x934 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Look-up Table register
address_offset : 0x94DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Look-up Table register
address_offset : 0x9898 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Look-up Table register
address_offset : 0x9C58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Look-up Table register
address_offset : 0xA01C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
RX Buffer Data Register
address_offset : 0xA18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXDATA : RX Data
bits : 0 - 31 (32 bit)
access : read-only
Look-up Table register
address_offset : 0xA3E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Look-up Table register
address_offset : 0xA7B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Look-up Table register
address_offset : 0xAB80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Look-up Table register
address_offset : 0xAF54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Look-up Table register
address_offset : 0xB32C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Look-up Table register
address_offset : 0xB708 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Look-up Table register
address_offset : 0xBAE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Look-up Table register
address_offset : 0xBECC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Flash Configuration Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TCSS : Serial flash CS setup time in terms of serial flash clock cycles
bits : 0 - 3 (4 bit)
access : read-write
TCSH : Serial flash CS hold time in terms of serial flash clock cycles
bits : 8 - 11 (4 bit)
access : read-write
TDH : Serial flash data in hold time
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#00 : 00
Data aligned with the posedge of Internal reference clock of QuadSPI
#01 : 01
Data aligned with 2x serial flash half clock
#10 : 10
Data aligned with 4x serial flash half clock
End of enumeration elements list.
RX Buffer Data Register
address_offset : 0xC28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXDATA : RX Data
bits : 0 - 31 (32 bit)
access : read-only
Look-up Table register
address_offset : 0xC2B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Look-up Table register
address_offset : 0xC4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Look-up Table register
address_offset : 0xC6A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Look-up Table register
address_offset : 0xCA90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Look-up Table register
address_offset : 0xCE84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Look-up Table register
address_offset : 0xD27C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Look-up Table register
address_offset : 0xD678 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Look-up Table register
address_offset : 0xDA78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Look-up Table register
address_offset : 0xDE7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Look-up Table register
address_offset : 0xE284 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
RX Buffer Data Register
address_offset : 0xE3C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXDATA : RX Data
bits : 0 - 31 (32 bit)
access : read-only
Look-up Table register
address_offset : 0xE690 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
Look-up Table register
address_offset : 0xF68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPRND0 : Operand for INSTR0.
bits : 0 - 7 (8 bit)
access : read-write
PAD0 : Pad information for INSTR0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR0 : Instruction 0
bits : 10 - 15 (6 bit)
access : read-write
OPRND1 : Operand for INSTR1.
bits : 16 - 23 (8 bit)
access : read-write
PAD1 : Pad information for INSTR1.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 Pad
#01 : 01
2 Pads
#10 : 10
4 Pads
#11 : 11
8 Pads
End of enumeration elements list.
INSTR1 : Instruction 1
bits : 26 - 31 (6 bit)
access : read-write
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