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TRGMUX0

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x70 byte (0x0)
mem_usage : registers
protection : not protected

Registers

TRGMUX_CMP0

TRGMUX_FTM0

TRGMUX_FTM1

TRGMUX_PDB0

TRGMUX_EXTOUT0

TRGMUX_LPIT0

TRGMUX_LPUART0

TRGMUX_LPUART1

TRGMUX_LPI2C0

TRGMUX_LPSPI0

TRGMUX_LPTMR0

TRGMUX_TSI

TRGMUX_PWT

TRGMUX_ADC0


TRGMUX_CMP0

TRGMUX CMP0 Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRGMUX_CMP0 TRGMUX_CMP0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL0 LK

SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 4 (5 bit)
access : read-write

LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : UNLOCKED

Register can be written.

0x1 : LOCKED

Register cannot be written until the next system Reset.

End of enumeration elements list.


TRGMUX_FTM0

TRGMUX FTM0 Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRGMUX_FTM0 TRGMUX_FTM0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL0 SEL1 SEL2 SEL3 LK

SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 4 (5 bit)
access : read-write

SEL1 : Trigger MUX Input 1 Source Select
bits : 8 - 12 (5 bit)
access : read-write

SEL2 : Trigger MUX Input 2 Source Select
bits : 16 - 20 (5 bit)
access : read-write

SEL3 : Trigger MUX Input 3 Source Select
bits : 24 - 28 (5 bit)
access : read-write

LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : UNLOCKED

Register can be written.

0x1 : LOCKED

Register cannot be written until the next system Reset.

End of enumeration elements list.


TRGMUX_FTM1

TRGMUX FTM1 Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRGMUX_FTM1 TRGMUX_FTM1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL0 LK

SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 4 (5 bit)
access : read-write

LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : UNLOCKED

Register can be written.

0x1 : LOCKED

Register cannot be written until the next system Reset.

End of enumeration elements list.


TRGMUX_PDB0

TRGMUX PDB0 Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRGMUX_PDB0 TRGMUX_PDB0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL0 LK

SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 4 (5 bit)
access : read-write

LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : UNLOCKED

Register can be written.

0x1 : LOCKED

Register cannot be written until the next system Reset.

End of enumeration elements list.


TRGMUX_EXTOUT0

TRGMUX EXTOUT0 Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRGMUX_EXTOUT0 TRGMUX_EXTOUT0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL0 SEL1 SEL2 SEL3 LK

SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 4 (5 bit)
access : read-write

SEL1 : Trigger MUX Input 1 Source Select
bits : 8 - 12 (5 bit)
access : read-write

SEL2 : Trigger MUX Input 2 Source Select
bits : 16 - 20 (5 bit)
access : read-write

SEL3 : Trigger MUX Input 3 Source Select
bits : 24 - 28 (5 bit)
access : read-write

LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : UNLOCKED

Register can be written.

0x1 : LOCKED

Register cannot be written until the next system Reset.

End of enumeration elements list.


TRGMUX_LPIT0

TRGMUX LPIT0 Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRGMUX_LPIT0 TRGMUX_LPIT0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL0 SEL1 LK

SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 4 (5 bit)
access : read-write

SEL1 : Trigger MUX Input 1 Source Select
bits : 8 - 12 (5 bit)
access : read-write

LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : UNLOCKED

Register can be written.

0x1 : LOCKED

Register cannot be written until the next system Reset.

End of enumeration elements list.


TRGMUX_LPUART0

TRGMUX LPUART0 Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRGMUX_LPUART0 TRGMUX_LPUART0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL0 LK

SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 4 (5 bit)
access : read-write

LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : UNLOCKED

Register can be written.

0x1 : LOCKED

Register cannot be written until the next system Reset.

End of enumeration elements list.


TRGMUX_LPUART1

TRGMUX LPUART1 Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRGMUX_LPUART1 TRGMUX_LPUART1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL0 LK

SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 4 (5 bit)
access : read-write

LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : UNLOCKED

Register can be written.

0x1 : LOCKED

Register cannot be written until the next system Reset.

End of enumeration elements list.


TRGMUX_LPI2C0

TRGMUX LPI2C0 Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRGMUX_LPI2C0 TRGMUX_LPI2C0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL0 LK

SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 4 (5 bit)
access : read-write

LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : UNLOCKED

Register can be written.

0x1 : LOCKED

Register cannot be written until the next system Reset.

End of enumeration elements list.


TRGMUX_LPSPI0

TRGMUX LPSPI0 Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRGMUX_LPSPI0 TRGMUX_LPSPI0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL0 LK

SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 4 (5 bit)
access : read-write

LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : UNLOCKED

Register can be written.

0x1 : LOCKED

Register cannot be written until the next system Reset.

End of enumeration elements list.


TRGMUX_LPTMR0

TRGMUX LPTMR0 Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRGMUX_LPTMR0 TRGMUX_LPTMR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL0 LK

SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 4 (5 bit)
access : read-write

LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : UNLOCKED

Register can be written.

0x1 : LOCKED

Register cannot be written until the next system Reset.

End of enumeration elements list.


TRGMUX_TSI

TRGMUX TSI Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRGMUX_TSI TRGMUX_TSI read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL0 LK

SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 4 (5 bit)
access : read-write

LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : UNLOCKED

Register can be written.

0x1 : LOCKED

Register cannot be written until the next system Reset.

End of enumeration elements list.


TRGMUX_PWT

TRGMUX PWT Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRGMUX_PWT TRGMUX_PWT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL0 LK

SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 4 (5 bit)
access : read-write

LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : UNLOCKED

Register can be written.

0x1 : LOCKED

Register cannot be written until the next system Reset.

End of enumeration elements list.


TRGMUX_ADC0

TRGMUX ADC0 Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRGMUX_ADC0 TRGMUX_ADC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL0 SEL1 SEL2 SEL3 LK

SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 4 (5 bit)
access : read-write

SEL1 : Trigger MUX Input 1 Source Select
bits : 8 - 12 (5 bit)
access : read-write

SEL2 : Trigger MUX Input 2 Source Select
bits : 16 - 20 (5 bit)
access : read-write

SEL3 : Trigger MUX Input 3 Source Select
bits : 24 - 28 (5 bit)
access : read-write

LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : UNLOCKED

Register can be written.

0x1 : LOCKED

Register cannot be written until the next system Reset.

End of enumeration elements list.



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