Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : registers
protection : not protected
Version ID Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FEATURE : Feature Specification Number
bits : 0 - 15 (16 bit)
access : read-only
Enumeration:
0x3 : FEATURE_3
Standard feature set.
End of enumeration elements list.
MINOR : Minor Version Number
bits : 16 - 23 (8 bit)
access : read-only
MAJOR : Major Version Number
bits : 24 - 31 (8 bit)
access : read-only
Mode Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BOOTROM : Boot ROM Configuration
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : BOOTROM_0
Boot from Flash
0x1 : BOOTROM_1
Boot from ROM due to BOOTCFG0 pin assertion / Reserved if no Boot pin
0x2 : BOOTROM_2
Boot form ROM due to FOPT[7] configuration
0x3 : BOOTROM_3
Boot from ROM due to both BOOTCFG0 pin assertion and FOPT[7] configuration
End of enumeration elements list.
Force Mode Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FORCEROM : Force ROM Boot
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : FORCEROM_0
No effect
0x1 : FORCEROM_1
Force boot from ROM with RCM_MR[1] set.
0x2 : FORCEROM_2
Force boot from ROM with RCM_MR[2] set.
0x3 : FORCEROM_3
Force boot from ROM with RCM_MR[2:1] set.
End of enumeration elements list.
Sticky System Reset Status Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLVD : Sticky Low-Voltage Detect Reset
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : SLVD_0
Reset not caused by LVD trip or POR
0x1 : SLVD_1
Reset caused by LVD trip or POR
End of enumeration elements list.
SLOC : Sticky Loss-of-Clock Reset
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : SLOC_0
Reset not caused by a loss of external clock.
0x1 : SLOC_1
Reset caused by a loss of external clock.
End of enumeration elements list.
SLOL : Sticky Loss-of-Lock Reset
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : SLOL_0
Reset not caused by a loss of lock in the PLL/FLL
0x1 : SLOL_1
Reset caused by a loss of lock in the PLL/FLL
End of enumeration elements list.
SWDOG : Sticky Watchdog
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : SWDOG_0
Reset not caused by watchdog timeout
0x1 : SWDOG_1
Reset caused by watchdog timeout
End of enumeration elements list.
SPIN : Sticky External Reset Pin
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : SPIN_0
Reset not caused by external reset pin
0x1 : SPIN_1
Reset caused by external reset pin
End of enumeration elements list.
SPOR : Sticky Power-On Reset
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : SPOR_0
Reset not caused by POR
0x1 : SPOR_1
Reset caused by POR
End of enumeration elements list.
SLOCKUP : Sticky Core Lockup
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : SLOCKUP_0
Reset not caused by core LOCKUP event
0x1 : SLOCKUP_1
Reset caused by core LOCKUP event
End of enumeration elements list.
SSW : Sticky Software
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : SSW_0
Reset not caused by software setting of SYSRESETREQ bit
0x1 : SSW_1
Reset caused by software setting of SYSRESETREQ bit
End of enumeration elements list.
SMDM_AP : Sticky MDM-AP System Reset Request
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : SMDM_AP_0
Reset was not caused by host debugger system setting of the System Reset Request bit
0x1 : SMDM_AP_1
Reset was caused by host debugger system setting of the System Reset Request bit
End of enumeration elements list.
SSACKERR : Sticky Stop Acknowledge Error
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : SSACKERR_0
Reset not caused by peripheral failure to acknowledge attempt to enter stop mode
0x1 : SSACKERR_1
Reset caused by peripheral failure to acknowledge attempt to enter stop mode
End of enumeration elements list.
System Reset Interrupt Enable Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DELAY : Reset Delay Time
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : DELAY_0
10 LPO cycles
0x1 : DELAY_1
34 LPO cycles
0x2 : DELAY_2
130 LPO cycles
0x3 : DELAY_3
514 LPO cycles
End of enumeration elements list.
LOC : Loss-of-Clock Interrupt
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : LOC_0
Interrupt disabled.
0x1 : LOC_1
Interrupt enabled.
End of enumeration elements list.
LOL : Loss-of-Lock Interrupt
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : LOL_0
Interrupt disabled.
0x1 : LOL_1
Interrupt enabled.
End of enumeration elements list.
WDOG : Watchdog Interrupt
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : WDOG_0
Interrupt disabled.
0x1 : WDOG_1
Interrupt enabled.
End of enumeration elements list.
PIN : External Reset Pin Interrupt
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : PIN_0
Reset not caused by external reset pin
0x1 : PIN_1
Reset caused by external reset pin
End of enumeration elements list.
GIE : Global Interrupt Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : GIE_0
All interrupt sources disabled.
0x1 : GIE_1
All interrupt sources enabled. Note that the individual interrupt-enable bits still need to be set to generate interrupts.
End of enumeration elements list.
LOCKUP : Core Lockup Interrupt
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : LOCKUP_0
Interrupt disabled.
0x1 : LOCKUP_1
Interrupt enabled.
End of enumeration elements list.
SW : Software Interrupt
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : SW_0
Interrupt disabled.
0x1 : SW_1
Interrupt enabled.
End of enumeration elements list.
MDM_AP : MDM-AP System Reset Request
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : MDM_AP_0
Interrupt disabled.
0x1 : MDM_AP_1
Interrupt enabled.
End of enumeration elements list.
SACKERR : Stop Acknowledge Error Interrupt
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : SACKERR_0
Interrupt disabled.
0x1 : SACKERR_1
Interrupt enabled.
End of enumeration elements list.
System Reset Status Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LVD : Low-Voltage Detect Reset or High-Voltage Detect Reset
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0 : LVD_0
Reset not caused by LVD trip, HVD trip or POR
0x1 : LVD_1
Reset caused by LVD trip, HVD trip or POR
End of enumeration elements list.
LOC : Loss-of-Clock Reset
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0 : LOC_0
Reset not caused by a loss of external clock.
0x1 : LOC_1
Reset caused by a loss of external clock.
End of enumeration elements list.
LOL : Loss-of-Lock Reset
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0 : LOL_0
Reset not caused by a loss of lock in the PLL/FLL
0x1 : LOL_1
Reset caused by a loss of lock in the PLL/FLL
End of enumeration elements list.
WDOG : Watchdog
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
0 : WDOG_0
Reset not caused by watchdog timeout
0x1 : WDOG_1
Reset caused by watchdog timeout
End of enumeration elements list.
PIN : External Reset Pin
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
0 : PIN_0
Reset not caused by external reset pin
0x1 : PIN_1
Reset caused by external reset pin
End of enumeration elements list.
POR : Power-On Reset
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
0 : POR_0
Reset not caused by POR
0x1 : POR_1
Reset caused by POR
End of enumeration elements list.
LOCKUP : Core Lockup
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
0 : LOCKUP_0
Reset not caused by core LOCKUP event
0x1 : LOCKUP_1
Reset caused by core LOCKUP event
End of enumeration elements list.
SW : Software
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
0 : SW_0
Reset not caused by software setting of SYSRESETREQ bit
0x1 : SW_1
Reset caused by software setting of SYSRESETREQ bit
End of enumeration elements list.
MDM_AP : MDM-AP System Reset Request
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
0 : MDM_AP_0
Reset was not caused by host debugger system setting of the System Reset Request bit
0x1 : MDM_AP_1
Reset was caused by host debugger system setting of the System Reset Request bit
End of enumeration elements list.
SACKERR : Stop Acknowledge Error
bits : 13 - 13 (1 bit)
access : read-only
Enumeration:
0 : SACKERR_0
Reset not caused by peripheral failure to acknowledge attempt to enter stop mode
0x1 : SACKERR_1
Reset caused by peripheral failure to acknowledge attempt to enter stop mode
End of enumeration elements list.
Reset Pin Control register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RSTFLTSRW : Reset Pin Filter Select in Run and Wait Modes
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : RSTFLTSRW_0
All filtering disabled
0x1 : RSTFLTSRW_1
Bus clock filter enabled for normal operation
0x2 : RSTFLTSRW_2
LPO clock filter enabled for normal operation
End of enumeration elements list.
RSTFLTSS : Reset Pin Filter Select in Stop Mode
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : RSTFLTSS_0
All filtering disabled
0x1 : RSTFLTSS_1
LPO clock filter enabled
End of enumeration elements list.
RSTFLTSEL : Reset Pin Filter Bus Clock Select
bits : 8 - 12 (5 bit)
access : read-write
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