Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x28 byte (0x0)
mem_usage : registers
protection : not protected
TSI General Control and Status Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EOSDMEO : End-of-Scan DMA Transfer Request Enable Only
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : EOSDMEO_0
Do not enable the End-of-Scan DMA transfer request only. Depending on ESOR state, either Out-of-Range or End-of-Scan can trigger a DMA transfer request and interrupt.
0x1 : EOSDMEO_1
Only the End-of-Scan event can trigger a DMA transfer request. The Out-of-Range event only and always triggers an interrupt if TSIIE is set.
End of enumeration elements list.
EOSF : End of Scan Flag
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : EOSF_0
Scan not complete.
0x1 : EOSF_1
Scan complete.
End of enumeration elements list.
SCNIP : Scan In Progress Status
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0 : SCNIP_0
No scan in progress.
0x1 : SCNIP_1
Scan in progress.
End of enumeration elements list.
STM : Scan Trigger Mode
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : STM_0
Software trigger scan.
0x1 : STM_1
Hardware trigger scan.
End of enumeration elements list.
STPE : TSI STOP Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : STPE_0
TSI is disabled when MCU goes into low power mode.
0x1 : STPE_1
Allows TSI to continue running in all low power modes.
End of enumeration elements list.
TSIIEN : Touch Sensing Input Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : TSIIEN_0
TSI interrupt is disabled.
0x1 : TSIIEN_1
TSI interrupt is enabled.
End of enumeration elements list.
TSIEN : Touch Sensing Input Module Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : TSIEN_0
TSI module disabled.
0x1 : TSIEN_1
TSI module enabled.
End of enumeration elements list.
CLKSOC_SEL : CLKSOC_SEL
bits : 11 - 11 (1 bit)
access : read-write
RUN_CTRL : RUN_CTRL
bits : 12 - 12 (1 bit)
access : read-write
TSI_ANA_TEST : TSI_ANA_TEST
bits : 13 - 15 (3 bit)
access : read-write
DVOLT : DVOLT
bits : 19 - 20 (2 bit)
access : read-write
Enumeration:
0 : DVOLT_0
Vm=0.3V; Vp=1.3V; dvolt=1.0V.
0x1 : DVOLT_1
Vm=0.3V; Vp=1.6V; dvolt=1.3V.
0x2 : DVOLT_2
Vm=0.3V; Vp=1.9V; dvolt=1.6V.
0x3 : DVOLT_3
Vm=0.3V; Vp=2.3V; dvolt=2.0V.
End of enumeration elements list.
ESOR : End-of-scan or Out-of-Range Interrupt Selection
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : ESOR_0
Out-of-range interrupt is allowed.
0x1 : ESOR_1
End-of-scan interrupt is allowed.
End of enumeration elements list.
OUTRGF : Out of Range Flag.
bits : 31 - 31 (1 bit)
access : read-write
TSI MUTUAL-CAP Register 0
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M_SEL_RX : M_SEL_RX
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : M_SEL_RX_0
select channel 6 as rx6.
0x1 : M_SEL_RX_1
select channel 7 as rx7.
0x2 : M_SEL_RX_2
select channel 8 as rx8.
0x3 : M_SEL_RX_3
select channel 9 as rx9.
0x4 : M_SEL_RX_4
select channel 10 as rx10.
0x5 : M_SEL_RX_5
select channel 11 as rx11.
0x6 : M_SEL_RX_6
NA.
0x7 : M_SEL_RX_7
NA.
End of enumeration elements list.
M_SEL_TX : M_SEL_TX
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0 : M_SEL_TX_0
select channel 0 as tx0.
0x1 : M_SEL_TX_1
select channel 1 as tx1.
0x2 : M_SEL_TX_2
select channel 2 as tx2.
0x3 : M_SEL_TX_3
select channel 3 as tx3.
0x4 : M_SEL_TX_4
select channel 4 as tx4.
0x5 : M_SEL_TX_5
select channel 5 as tx5.
0x6 : M_SEL_TX_6
NA.
0x7 : M_SEL_TX_7
NA.
End of enumeration elements list.
M_SEN_RES : M_SEN_RES
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
0 : M_SEN_RES_0
2.5k.
0x1 : M_SEN_RES_1
5k.
0x2 : M_SEN_RES_2
7.5k.
0x3 : M_SEN_RES_3
10k.
0x4 : M_SEN_RES_4
12.5k.
0x5 : M_SEN_RES_5
15k.
0x6 : M_SEN_RES_6
17.5k.
0x7 : M_SEN_RES_7
20k.
0x8 : M_SEN_RES_8
22.5k.
0x9 : M_SEN_RES_9
25k.
0xA : M_SEN_RES_10
27.5k.
0xB : M_SEN_RES_11
30k.
0xC : M_SEN_RES_12
32.5k.
0xD : M_SEN_RES_13
35k.
0xE : M_SEN_RES_14
37.5k.
0xF : M_SEN_RES_15
40k.
End of enumeration elements list.
M_PRE_RES : M_PRE_RES
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : M_PRE_RES_0
1k.
0x1 : M_PRE_RES_1
2k.
0x2 : M_PRE_RES_2
3k.
0x3 : M_PRE_RES_3
4k.
0x4 : M_PRE_RES_4
5k.
0x5 : M_PRE_RES_5
6k.
0x6 : M_PRE_RES_6
7k.
0x7 : M_PRE_RES_7
8k.
End of enumeration elements list.
M_TX_USED : M_TX_USED
bits : 16 - 21 (6 bit)
access : read-write
M_PRE_CURRENT : M_PRE_CURRENT
bits : 29 - 31 (3 bit)
access : read-write
Enumeration:
0 : M_PRE_CURRENT_0
1uA.
0x1 : M_PRE_CURRENT_1
2uA.
0x2 : M_PRE_CURRENT_2
3uA.
0x3 : M_PRE_CURRENT_3
4uA.
0x4 : M_PRE_CURRENT_4
5uA.
0x5 : M_PRE_CURRENT_5
6uA.
0x6 : M_PRE_CURRENT_6
7uA.
0x7 : M_PRE_CURRENT_7
8uA.
End of enumeration elements list.
TSI MUTUAL-CAP Register 1
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M_NMIR_CTRL : M_NMIR_CTRL
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : M_NMIR_CTRL_0
Enable NMOS mirror.
0x1 : M_NMIR_CTRL_1
Disable NMOS mirror.
End of enumeration elements list.
M_NMIRROR : M_NMIRROR
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : M_NMIRROR_0
m=1.
0x1 : M_NMIRROR_1
m=2.
0x2 : M_NMIRROR_2
m=3.
0x3 : M_NMIRROR_3
m=4.
End of enumeration elements list.
M_PMIRRORR : M_PMIRRORR
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : M_PMIRRORR_0
m=1.
0x1 : M_PMIRRORR_1
m=2.
0x2 : M_PMIRRORR_2
m=3.
0x3 : M_PMIRRORR_3
m=4.
End of enumeration elements list.
M_PMIRRORL : M_PMIRRORL
bits : 5 - 7 (3 bit)
access : read-write
Enumeration:
0 : M_PMIRRORL_0
m=4.
0x1 : M_PMIRRORL_1
m=8.
0x2 : M_PMIRRORL_2
m=12.
0x3 : M_PMIRRORL_3
m=16.
0x4 : M_PMIRRORL_4
m=20.
0x5 : M_PMIRRORL_5
m=24.
0x6 : M_PMIRRORL_6
m=28.
0x7 : M_PMIRRORL_7
m=32.
End of enumeration elements list.
M_TRIM2 : M_TRIM2
bits : 8 - 15 (8 bit)
access : read-write
M_VPRE_CHOOSE : M_VPRE_CHOOSE
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : M_VPRE_CHOOSE_0
Internal 1.2V voltage.
0x1 : M_VPRE_CHOOSE_1
1.2V PMC output.
End of enumeration elements list.
M_MODE : M_MODE
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : M_MODE_0
-5V~+5V.
0x1 : M_MODE_1
0V~+5V.
End of enumeration elements list.
M_SEN_BOOST : M_SEN_BOOST
bits : 19 - 23 (5 bit)
access : read-write
Enumeration:
0 : M_SEN_BOOST_0
0u.
0x1 : M_SEN_BOOST_1
2u.
0x2 : M_SEN_BOOST_2
4u.
0x3 : M_SEN_BOOST_3
6u.
0x4 : M_SEN_BOOST_4
8u.
0x5 : M_SEN_BOOST_5
10u.
0x6 : M_SEN_BOOST_6
12u.
0x7 : M_SEN_BOOST_7
14u
0x8 : M_SEN_BOOST_8
16u.
0x9 : M_SEN_BOOST_9
18u.
0xA : M_SEN_BOOST_10
20u.
0xB : M_SEN_BOOST_11
22u.
0xC : M_SEN_BOOST_12
24u.
0xD : M_SEN_BOOST_13
26u.
0xE : M_SEN_BOOST_14
28u.
0xF : M_SEN_BOOST_15
30u.
0x10 : M_SEN_BOOST_16
32u.
0x11 : M_SEN_BOOST_17
34u.
0x12 : M_SEN_BOOST_18
36u.
0x13 : M_SEN_BOOST_19
38u.
0x14 : M_SEN_BOOST_20
40u.
0x15 : M_SEN_BOOST_21
42u.
0x16 : M_SEN_BOOST_22
44u.
0x17 : M_SEN_BOOST_23
46u.
0x18 : M_SEN_BOOST_24
48u.
0x19 : M_SEN_BOOST_25
50u.
0x1A : M_SEN_BOOST_26
52u.
0x1B : M_SEN_BOOST_27
54u.
0x1C : M_SEN_BOOST_28
56u.
0x1D : M_SEN_BOOST_29
58u.
0x1E : M_SEN_BOOST_30
60u.
0x1F : M_SEN_BOOST_31
62u.
End of enumeration elements list.
TSI SINC filter Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SSC_CONTROL_OUT : SSC_CONTROL_OUT
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : SSC_CONTROL_OUT_0
SSC output value is 0.
0x1 : SSC_CONTROL_OUT_1
SSC output value is 1.
End of enumeration elements list.
SINC_VALID : SINC_VALID
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0 : SINC_VALID_0
SINC filter is disabled.
0x1 : SINC_VALID_1
SINC filter is enabled.
End of enumeration elements list.
SINC_OVERFLOW_FLAG : SINC_OVERFLOW_FLAG
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0 : SINC_OVERFLOW_FLAG_0
The counter result has no overflow occurrence in the last scan process.
0x1 : SINC_OVERFLOW_FLAG_1
The counter result has an overflow occurrence in the last scan process.
End of enumeration elements list.
SWITCH_ENABLE : SWITCH_ENABLE
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0 : SWITCH_ENABLE_0
SSC function is disabled.
0x1 : SWITCH_ENABLE_1
SSC function is enabled.
End of enumeration elements list.
DECIMATION : DECIMATION
bits : 16 - 20 (5 bit)
access : read-write
Enumeration:
0 : DECIMATION_0
The TSI_DATA[TSICNT] bits is the counter value of 1 scan period.
0x1 : DECIMATION_1
The TSI_DATA[TSICNT] bits is the counter value of 2 scan periods.
0x2 : DECIMATION_2
The TSI_DATA[TSICNT] bits is the counter value of 3 scan periods.
0x3 : DECIMATION_3
The TSI_DATA[TSICNT] bits is the counter value of 4 scan periods.
0x4 : DECIMATION_4
The TSI_DATA[TSICNT] bits is the counter value of 5 scan periods.
0x5 : DECIMATION_5
The TSI_DATA[TSICNT] bits is the counter value of 6 scan periods.
0x6 : DECIMATION_6
The TSI_DATA[TSICNT] bits is the counter value of 7 scan periods.
0x7 : DECIMATION_7
The TSI_DATA[TSICNT] bits is the counter value of 8 scan periods.
0x8 : DECIMATION_8
The TSI_DATA[TSICNT] bits is the counter value of 9 scan periods.
0x9 : DECIMATION_9
The TSI_DATA[TSICNT] bits is the counter value of 10 scan periods.
0xA : DECIMATION_10
The TSI_DATA[TSICNT] bits is the counter value of 11 scan periods.
0xB : DECIMATION_11
The TSI_DATA[TSICNT] bits is the counter value of 12 scan periods.
0xC : DECIMATION_12
The TSI_DATA[TSICNT] bits is the counter value of 13 scan periods.
0xD : DECIMATION_13
The TSI_DATA[TSICNT] bits is the counter value of 14 scan periods.
0xE : DECIMATION_14
The TSI_DATA[TSICNT] bits is the counter value of 15 scan periods.
0xF : DECIMATION_15
The TSI_DATA[TSICNT] bits is the counter value of 16 scan periods.
0x10 : DECIMATION_16
The TSI_DATA[TSICNT] bits is the counter value of 17 scan periods.
0x11 : DECIMATION_17
The TSI_DATA[TSICNT] bits is the counter value of 18 scan periods.
0x12 : DECIMATION_18
The TSI_DATA[TSICNT] bits is the counter value of 19 scan periods.
0x13 : DECIMATION_19
The TSI_DATA[TSICNT] bits is the counter value of 20 scan periods.
0x14 : DECIMATION_20
The TSI_DATA[TSICNT] bits is the counter value of 21 scan periods.
0x15 : DECIMATION_21
The TSI_DATA[TSICNT] bits is the counter value of 22 scan periods.
0x16 : DECIMATION_22
The TSI_DATA[TSICNT] bits is the counter value of 23 scan periods.
0x17 : DECIMATION_23
The TSI_DATA[TSICNT] bits is the counter value of 24 scan periods.
0x18 : DECIMATION_24
The TSI_DATA[TSICNT] bits is the counter value of 25 scan periods.
0x19 : DECIMATION_25
The TSI_DATA[TSICNT] bits is the counter value of 26 scan periods.
0x1A : DECIMATION_26
The TSI_DATA[TSICNT] bits is the counter value of 27 scan periods.
0x1B : DECIMATION_27
The TSI_DATA[TSICNT] bits is the counter value of 28 scan periods.
0x1C : DECIMATION_28
The TSI_DATA[TSICNT] bits is the counter value of 29 scan periods.
0x1D : DECIMATION_29
The TSI_DATA[TSICNT] bits is the counter value of 30 scan periods.
0x1E : DECIMATION_30
The TSI_DATA[TSICNT] bits is the counter value of 31 scan periods.
0x1F : DECIMATION_31
The TSI_DATA[TSICNT] bits is the counter value of 32 scan periods.
End of enumeration elements list.
ORDER : ORDER
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : ORDER_0
Using 1 order SINC filter.
0x1 : ORDER_1
Using 2 order SINC filter.
End of enumeration elements list.
CUTOFF : CUTOFF
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
0 : CUTOFF_0
div=1.
0x1 : CUTOFF_1
div=2.
0x2 : CUTOFF_2
div=4.
0x3 : CUTOFF_3
div=8.
0x4 : CUTOFF_4
div=16.
0x5 : CUTOFF_5
div=32.
0x6 : CUTOFF_6
div=64.
0x7 : CUTOFF_7
div=128.
0x8 : CUTOFF_8
NC.
0x9 : CUTOFF_9
NC.
0xA : CUTOFF_10
NC.
0xB : CUTOFF_11
NC.
0xC : CUTOFF_12
NC.
0xD : CUTOFF_13
NC
0xE : CUTOFF_14
NC.
0xF : CUTOFF_15
NC.
End of enumeration elements list.
TSI SSC Register 0
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SSC_PRESCALE_NUM : SSC_PRESCALE_NUM
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0 : SSC_PRESCALE_NUM_0
div1
0x1 : SSC_PRESCALE_NUM_1
div2
0x3 : SSC_PRESCALE_NUM_3
div4
0x7 : SSC_PRESCALE_NUM_7
div8
0xF : SSC_PRESCALE_NUM_15
div16
0x1F : SSC_PRESCALE_NUM_31
div32
0x3F : SSC_PRESCALE_NUM_63
div64
0x7F : SSC_PRESCALE_NUM_127
div128
0xFF : SSC_PRESCALE_NUM_255
div256
End of enumeration elements list.
BASE_NOCHARGE_NUM : BASE_NOCHARGE_NUM
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0 : BASE_NOCHARGE_NUM_0
The SSC output bit 1's basic period will be 1 clock cycle of system clock.
0x1 : BASE_NOCHARGE_NUM_1
The SSC output bit 1's basic period will be 2 clock cycles of system clock.
0x2 : BASE_NOCHARGE_NUM_2
The SSC output bit 1's basic period will be 3 clock cycles of system clock.
0x3 : BASE_NOCHARGE_NUM_3
The SSC output bit 1's basic period will be 4 clock cycles of system clock.
0x4 : BASE_NOCHARGE_NUM_4
The SSC output bit 1's basic period will be 5 clock cycles of system clock.
0x5 : BASE_NOCHARGE_NUM_5
The SSC output bit 1's basic period will be 6 clock cycles of system clock.
0x6 : BASE_NOCHARGE_NUM_6
The SSC output bit 1's basic period will be 7 clock cycles of system clock.
0x7 : BASE_NOCHARGE_NUM_7
The SSC output bit 1's basic period will be 8 clock cycles of system clock.
0x8 : BASE_NOCHARGE_NUM_8
The SSC output bit 1's basic period will be 9 clock cycles of system clock.
0x9 : BASE_NOCHARGE_NUM_9
The SSC output bit 1's basic period will be 10 clock cycles of system clock.
0xA : BASE_NOCHARGE_NUM_10
The SSC output bit 1's basic period will be 11 clock cycles of system clock.
0xB : BASE_NOCHARGE_NUM_11
The SSC output bit 1's basic period will be 12 clock cycles of system clock.
0xC : BASE_NOCHARGE_NUM_12
The SSC output bit 1's basic period will be 13 clock cycles of system clock.
0xD : BASE_NOCHARGE_NUM_13
The SSC output bit 1's basic period will be 14 clock cycles of system clock.
0xE : BASE_NOCHARGE_NUM_14
The SSC output bit 1's basic period will be 15 clock cycles of system clock.
0xF : BASE_NOCHARGE_NUM_15
The SSC output bit 1's basic period will be 16 clock cycles of system clock.
End of enumeration elements list.
CHARGE_NUM : CHARGE_NUM
bits : 20 - 23 (4 bit)
access : read-write
Enumeration:
0 : CHARGE_NUM_0
The SSC output bit 0's period will be 1 clock cycle of system clock.
0x1 : CHARGE_NUM_1
The SSC output bit 0's period will be 2 clock cycles of system clock.
0x2 : CHARGE_NUM_2
The SSC output bit 0's period will be 3 clock cycles of system clock.
0x3 : CHARGE_NUM_3
The SSC output bit 0's period will be 4 clock cycles of system clock.
0x4 : CHARGE_NUM_4
The SSC output bit 0's period will be 5 clock cycles of system clock.
0x5 : CHARGE_NUM_5
The SSC output bit 0's period will be 6 clock cycles of system clock.
0x6 : CHARGE_NUM_6
The SSC output bit 0's period will be 7 clock cycles of system clock.
0x7 : CHARGE_NUM_7
The SSC output bit 0's period will be 8 clock cycles of system clock.
0x8 : CHARGE_NUM_8
The SSC output bit 0's period will be 9 clock cycles of system clock.
0x9 : CHARGE_NUM_9
The SSC output bit 0's period will be 10 clock cycles of system clock.
0xA : CHARGE_NUM_10
The SSC output bit 0's period will be 11 clock cycles of system clock.
0xB : CHARGE_NUM_11
The SSC output bit 0's period will be 12 clock cycles of system clock.
0xC : CHARGE_NUM_12
The SSC output bit 0's period will be 13 clock cycles of system clock.
0xD : CHARGE_NUM_13
The SSC output bit 0's period will be 14 clock cycles of system clock.
0xE : CHARGE_NUM_14
The SSC output bit 0's period will be 15 clock cycles of system clock.
0xF : CHARGE_NUM_15
The SSC output bit 0's period will be 16 clock cycles of system clock.
End of enumeration elements list.
SSC_CONTROL_REVERSE : SSC_CONTROL_REVERSE
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : SSC_CONTROL_REVERSE_0
Keep the polarity of the SSC output bit.
0x1 : SSC_CONTROL_REVERSE_1
Reverse the polarity of the SSC output bit.
End of enumeration elements list.
SSC_MODE : SSC_MODE
bits : 25 - 26 (2 bit)
access : read-write
Enumeration:
0 : SSC_MODE_0
Using PRBS method generating SSC output bit.
0x1 : SSC_MODE_1
Using up-down counter generating SSC output bit.
0x2 : SSC_MODE_2
SSC function is disabled.
0x3 : SSC_MODE_3
NC.
End of enumeration elements list.
PRBS_OUTSEL : PRBS_OUTSEL
bits : 28 - 31 (4 bit)
access : read-write
Enumeration:
0 : PRBS_OUTSEL_0
NC.
0x1 : PRBS_OUTSEL_1
NC.
0x2 : PRBS_OUTSEL_2
The length of the PRBS is 2.
0x3 : PRBS_OUTSEL_3
The length of the PRBS is 3.
0x4 : PRBS_OUTSEL_4
The length of the PRBS is 4.
0x5 : PRBS_OUTSEL_5
The length of the PRBS is 5.
0x6 : PRBS_OUTSEL_6
The length of the PRBS is 6.
0x7 : PRBS_OUTSEL_7
The length of the PRBS is 7.
0x8 : PRBS_OUTSEL_8
The length of the PRBS is 8.
0x9 : PRBS_OUTSEL_9
The length of the PRBS is 9.
0xA : PRBS_OUTSEL_10
The length of the PRBS is 10.
0xB : PRBS_OUTSEL_11
The length of the PRBS is 11.
0xC : PRBS_OUTSEL_12
The length of the PRBS is 12.
0xD : PRBS_OUTSEL_13
The length of the PRBS is 13.
0xE : PRBS_OUTSEL_14
The length of the PRBS is 14.
0xF : PRBS_OUTSEL_15
The length of the PRBS is 15.
End of enumeration elements list.
TSI SSC Register 1
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRBS_SEED_LO : PRBS_SEED_LO
bits : 0 - 7 (8 bit)
access : read-write
PRBS_SEED_HI : PRBS_SEED_HI
bits : 8 - 15 (8 bit)
access : read-write
PRBS_WEIGHT_LO : PRBS_WEIGHT_LO
bits : 16 - 23 (8 bit)
access : read-write
PRBS_WEIGHT_HI : PRBS_WEIGHT_HI
bits : 24 - 31 (8 bit)
access : read-write
TSI SSC Register 2
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MOVE_REPEAT_NUM : MOVE_REPEAT_NUM
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : MOVE_REPEAT_NUM_0
The up_down counter will be updated for every sample-charge cycle.
0x1 : MOVE_REPEAT_NUM_1
The up_down counter will be updated for every 2 sample-charge cycles.
0x2 : MOVE_REPEAT_NUM_2
The up_down counter will be updated for every 3 sample-charge cycles.
0x3 : MOVE_REPEAT_NUM_3
The up_down counter will be updated for every 4 sample-charge cycles.
0x4 : MOVE_REPEAT_NUM_4
The up_down counter will be updated for every 5 sample-charge cycles.
0x5 : MOVE_REPEAT_NUM_5
The up_down counter will be updated for every 6 sample-charge cycles.
0x6 : MOVE_REPEAT_NUM_6
The up_down counter will be updated for every 7 sample-charge cycles.
End of enumeration elements list.
MOVE_STEPS_NUM : MOVE_STEPS_NUM
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0 : MOVE_STEPS_NUM_0
The added value for up-down counter is 0.
0x1 : MOVE_STEPS_NUM_1
The added value for up-down counter is 1.
0x2 : MOVE_STEPS_NUM_2
The added value for up-down counter is 2.
0x3 : MOVE_STEPS_NUM_3
The added value for up-down counter is 3.
0x4 : MOVE_STEPS_NUM_4
The added value for up-down counter is 4.
0x5 : MOVE_STEPS_NUM_5
The added value for up-down counter is 5.
0x6 : MOVE_STEPS_NUM_6
The added value for up-down counter is 6.
0x7 : MOVE_STEPS_NUM_7
The added value for up-down counter is 7.
End of enumeration elements list.
MOVE_NOCHARGE_MAX : MOVE_NOCHARGE_MAX
bits : 16 - 21 (6 bit)
access : read-write
MOVE_NOCHARGE_MIN : MOVE_NOCHARGE_MIN
bits : 28 - 31 (4 bit)
access : read-write
Enumeration:
0 : MOVE_NOCHARGE_MIN_0
The SSC output bit 1's min period will be (1 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycle of divided system clock.
0x1 : MOVE_NOCHARGE_MIN_1
The SSC output bit 1's min period will be (2 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of divided system clock.
0x2 : MOVE_NOCHARGE_MIN_2
The SSC output bit 1's min period will be (3 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of divided system clock.
0x3 : MOVE_NOCHARGE_MIN_3
The SSC output bit 1's min period will be (4 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of divided system clock.
0x4 : MOVE_NOCHARGE_MIN_4
The SSC output bit 1's min period will be (5 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of divided system clock.
0x5 : MOVE_NOCHARGE_MIN_5
The SSC output bit 1's min period will be (6 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of divided system clock.
0x6 : MOVE_NOCHARGE_MIN_6
The SSC output bit 1's min period will be (7 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of divided system clock.
0x7 : MOVE_NOCHARGE_MIN_7
The SSC output bit 1's min period will be (8 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of divided system clock.
0x8 : MOVE_NOCHARGE_MIN_8
The SSC output bit 1's min period will be (9 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of divided system clock.
0x9 : MOVE_NOCHARGE_MIN_9
The SSC output bit 1's min period will be (10 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of divided system clock.
0xA : MOVE_NOCHARGE_MIN_10
The SSC output bit 1's min period will be (11 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of divided system clock.
0xB : MOVE_NOCHARGE_MIN_11
The SSC output bit 1's min period will be (12 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of divided system clock.
0xC : MOVE_NOCHARGE_MIN_12
The SSC output bit 1's min period will be (13 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of divided system clock.
0xD : MOVE_NOCHARGE_MIN_13
The SSC output bit 1's min period will be (14 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of divided system clock.
0xE : MOVE_NOCHARGE_MIN_14
The SSC output bit 1's min period will be (15 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of divided system clock.
0xF : MOVE_NOCHARGE_MIN_15
The SSC output bit 1's min period will be (16 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of divided system clock.
End of enumeration elements list.
TSI DATA Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSICNT : TSI Conversion Counter Value
bits : 0 - 15 (16 bit)
access : read-only
SWTS : Software Trigger Start
bits : 22 - 22 (1 bit)
access : write-only
Enumeration:
0 : SWTS_0
No effect.
0x1 : SWTS_1
Start a scan to determine which channel is specified by TSI_DATA[TSICH].
End of enumeration elements list.
DMAEN : DMA Transfer Enabled
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : DMAEN_0
Interrupt is selected when the interrupt enable bit is set and the corresponding TSI events assert.
0x1 : DMAEN_1
DMA transfer request is selected when the interrupt enable bit is set and the corresponding TSI events assert.
End of enumeration elements list.
TSICH : TSICH
bits : 27 - 31 (5 bit)
access : read-write
Enumeration:
0 : TSICH_0
For self-cap mode: Channel 0.
0x1 : TSICH_1
For self-cap mode: Channel 1.
0x2 : TSICH_2
For self-cap mode: Channel 2.
0x3 : TSICH_3
For self-cap mode: Channel 3.
0x4 : TSICH_4
For self-cap mode: Channel 4.
0x5 : TSICH_5
For self-cap mode: Channel 5.
0x6 : TSICH_6
For self-cap mode: Channel 6.
0x7 : TSICH_7
For self-cap mode: Channel 7.
0x8 : TSICH_8
For self-cap mode: Channel 8.
0x9 : TSICH_9
For self-cap mode: Channel 9.
0xA : TSICH_10
For self-cap mode: Channel 10.
0xB : TSICH_11
For self-cap mode: Channel 11.
0xC : TSICH_12
For self-cap mode: Channel 12.
0xD : TSICH_13
For self-cap mode: Channel 13.
0xE : TSICH_14
For self-cap mode: Channel 14.
0xF : TSICH_15
For self-cap mode: Channel 15.
0x10 : TSICH_16
For self-cap mode: Channel 16.
0x11 : TSICH_17
For self-cap mode: Channel 17.
0x12 : TSICH_18
For self-cap mode: Channel 18.
0x13 : TSICH_19
For self-cap mode: Channel 19.
0x14 : TSICH_20
For self-cap mode: Channel 20.
0x15 : TSICH_21
For self-cap mode: Channel 21.
0x16 : TSICH_22
For self-cap mode: Channel 22.
0x17 : TSICH_23
For self-cap mode: Channel 23.
0x18 : TSICH_24
For self-cap mode: Channel 24.
End of enumeration elements list.
TSI Threshold Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
THRESL : TSI Wakeup Channel Low-threshold
bits : 0 - 15 (16 bit)
access : read-write
THRESH : TSI Wakeup Channel High-threshold
bits : 16 - 31 (16 bit)
access : read-write
TSI MODE Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
S_NOISE : S_NOISE
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : S_NOISE_0
noise cancellation off.
0x1 : S_NOISE_1
noise cancellation on.
End of enumeration elements list.
MODE : MODE
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : MODE_0
self-cap mode.
0x1 : MODE_1
mutual-cap mode.
End of enumeration elements list.
SETCLK : SETCLK
bits : 5 - 6 (2 bit)
access : read-write
Enumeration:
0 : SETCLK_0
20.72MHz.
0x1 : SETCLK_1
16.65MHz.
0x2 : SETCLK_2
13.87MHz.
0x3 : SETCLK_3
11.91MHz.
End of enumeration elements list.
S_XCH : S_XCH
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0 : S_XCH_0
1/16.
0x1 : S_XCH_1
1/8.
0x2 : S_XCH_2
1/4.
0x3 : S_XCH_3
1/2.
0x4 : S_XCH_4
NA.
0x5 : S_XCH_5
NA.
0x6 : S_XCH_6
NA.
0x7 : S_XCH_7
NA.
End of enumeration elements list.
S_XIN : S_XIN
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : S_XIN_0
1/8.
0x1 : S_XIN_1
1/4.
End of enumeration elements list.
S_CTRIM : Capacitor trim setting
bits : 19 - 21 (3 bit)
access : read-write
Enumeration:
0 : S_CTRIM_0
Ctrim=2.5p.
0x1 : S_CTRIM_1
Ctrim=5.0p.
0x2 : S_CTRIM_2
Ctrim=7.5p.
0x3 : S_CTRIM_3
Ctrim=10p.
0x4 : S_CTRIM_4
Ctrim=12.5p.
0x5 : S_CTRIM_5
Ctrim=15p.
0x6 : S_CTRIM_6
Ctrim=17.5p.
0x7 : S_CTRIM_7
Ctrim=20p.
End of enumeration elements list.
S_SEN : S_SEN
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : S_SEN_0
Sensitivity boost off.
0x1 : S_SEN_1
Sensitivity boost on.
End of enumeration elements list.
S_W_SHIELD : S_W_SHIELD
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : S_W_SHIELD_0
shield switch off.
0x1 : S_W_SHIELD_1
shield switch on.
End of enumeration elements list.
S_XDN : S_XDN
bits : 28 - 30 (3 bit)
access : read-write
Enumeration:
0 : S_XDN_0
1/16.
0x1 : S_XDN_1
1/8.
0x2 : S_XDN_2
1/4.
0x3 : S_XDN_3
1/2.
0x4 : S_XDN_4
NA.
0x5 : S_XDN_5
NA.
0x6 : S_XDN_6
NA.
0x7 : S_XDN_7
NA.
End of enumeration elements list.
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