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TRGMUX1

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

Registers

TRGMUX_CTRL0


TRGMUX_CTRL0

TRGMUX CTRL0 Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRGMUX_CTRL0 TRGMUX_CTRL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL0 SEL1 SEL2 SEL3 LK

SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 4 (5 bit)
access : read-write

SEL1 : Trigger MUX Input 1 Source Select
bits : 8 - 12 (5 bit)
access : read-write

SEL2 : Trigger MUX Input 2 Source Select
bits : 16 - 20 (5 bit)
access : read-write

SEL3 : Trigger MUX Input 3 Source Select
bits : 24 - 28 (5 bit)
access : read-write

LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : UNLOCKED

Register can be written.

0x1 : LOCKED

Register cannot be written until the next system Reset.

End of enumeration elements list.



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