\n
address_offset : 0x0 Bytes (0x0)
size : 0x198 byte (0x0)
mem_usage : registers
protection : not protected
Status and Control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LDOK : Load OK
bits : 0 - 0 (1 bit)
access : read-write
CONT : Continuous Mode Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : CONT_0
PDB operation in One-Shot mode
0x1 : CONT_1
PDB operation in Continuous mode
End of enumeration elements list.
MULT : Multiplication Factor Select for Prescaler
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0 : MULT_0
Multiplication factor is 1.
0x1 : MULT_1
Multiplication factor is 10.
0x2 : MULT_2
Multiplication factor is 20.
0x3 : MULT_3
Multiplication factor is 40.
End of enumeration elements list.
PDBIE : PDB Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : PDBIE_0
PDB interrupt disabled.
0x1 : PDBIE_1
PDB interrupt enabled.
End of enumeration elements list.
PDBIF : PDB Interrupt Flag
bits : 6 - 6 (1 bit)
access : read-write
PDBEN : PDB Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : PDBEN_0
PDB disabled. Counter is off.
0x1 : PDBEN_1
PDB enabled.
End of enumeration elements list.
TRGSEL : Trigger Input Source Select
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
0 : TRGSEL_0
Trigger-In 0 is selected.
0x1 : TRGSEL_1
Trigger-In 1 is selected.
0x2 : TRGSEL_2
Trigger-In 2 is selected.
0x3 : TRGSEL_3
Trigger-In 3 is selected.
0x4 : TRGSEL_4
Trigger-In 4 is selected.
0x5 : TRGSEL_5
Trigger-In 5 is selected.
0x6 : TRGSEL_6
Trigger-In 6 is selected.
0x7 : TRGSEL_7
Trigger-In 7 is selected.
0x8 : TRGSEL_8
Trigger-In 8 is selected.
0x9 : TRGSEL_9
Trigger-In 9 is selected.
0xA : TRGSEL_10
Trigger-In 10 is selected.
0xB : TRGSEL_11
Trigger-In 11 is selected.
0xC : TRGSEL_12
Trigger-In 12 is selected.
0xD : TRGSEL_13
Trigger-In 13 is selected.
0xE : TRGSEL_14
Trigger-In 14 is selected.
0xF : TRGSEL_15
Software trigger is selected.
End of enumeration elements list.
PRESCALER : Prescaler Divider Select
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0 : PRESCALER_0
Counting uses the peripheral clock divided by MULT (the multiplication factor).
0x1 : PRESCALER_1
Counting uses the peripheral clock divided by 2 x MULT (the multiplication factor).
0x2 : PRESCALER_2
Counting uses the peripheral clock divided by 4 x MULT (the multiplication factor).
0x3 : PRESCALER_3
Counting uses the peripheral clock divided by 8 x MULT (the multiplication factor).
0x4 : PRESCALER_4
Counting uses the peripheral clock divided by 16 x MULT (the multiplication factor).
0x5 : PRESCALER_5
Counting uses the peripheral clock divided by 32 x MULT (the multiplication factor).
0x6 : PRESCALER_6
Counting uses the peripheral clock divided by 64 x MULT (the multiplication factor).
0x7 : PRESCALER_7
Counting uses the peripheral clock divided by 128 x MULT (the multiplication factor).
End of enumeration elements list.
DMAEN : DMA Enable
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : DMAEN_0
DMA disabled.
0x1 : DMAEN_1
DMA enabled.
End of enumeration elements list.
SWTRIG : Software Trigger
bits : 16 - 16 (1 bit)
access : write-only
PDBEIE : PDB Sequence Error Interrupt Enable
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : PDBEIE_0
PDB sequence error interrupt disabled.
0x1 : PDBEIE_1
PDB sequence error interrupt enabled.
End of enumeration elements list.
LDMOD : Load Mode Select
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
0 : LDMOD_0
The internal registers are loaded with the values from their buffers, immediately after 1 is written to LDOK.
0x1 : LDMOD_1
The internal registers are loaded with the values from their buffers when the PDB counter (CNT) = MOD + 1 CNT delay elapsed, after 1 is written to LDOK.
0x2 : LDMOD_2
The internal registers are loaded with the values from their buffers when a trigger input event is detected, after 1 is written to LDOK.
0x3 : LDMOD_3
The internal registers are loaded with the values from their buffers when either the PDB counter (CNT) = MOD + 1 CNT delay elapsed, or a trigger input event is detected, after 1 is written to LDOK.
End of enumeration elements list.
Channel n Control register 1
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN0 : PDB Channel Pre-Trigger Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : EN_0
PDB channel's corresponding pre-trigger disabled.
0x1 : EN_1
PDB channel's corresponding pre-trigger enabled.
End of enumeration elements list.
EN1 : PDB Channel Pre-Trigger Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : EN_0
PDB channel's corresponding pre-trigger disabled.
0x1 : EN_1
PDB channel's corresponding pre-trigger enabled.
End of enumeration elements list.
EN2 : PDB Channel Pre-Trigger Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : EN_0
PDB channel's corresponding pre-trigger disabled.
0x1 : EN_1
PDB channel's corresponding pre-trigger enabled.
End of enumeration elements list.
EN3 : PDB Channel Pre-Trigger Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : EN_0
PDB channel's corresponding pre-trigger disabled.
0x1 : EN_1
PDB channel's corresponding pre-trigger enabled.
End of enumeration elements list.
EN4 : PDB Channel Pre-Trigger Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : EN_0
PDB channel's corresponding pre-trigger disabled.
0x1 : EN_1
PDB channel's corresponding pre-trigger enabled.
End of enumeration elements list.
EN5 : PDB Channel Pre-Trigger Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : EN_0
PDB channel's corresponding pre-trigger disabled.
0x1 : EN_1
PDB channel's corresponding pre-trigger enabled.
End of enumeration elements list.
EN6 : PDB Channel Pre-Trigger Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : EN_0
PDB channel's corresponding pre-trigger disabled.
0x1 : EN_1
PDB channel's corresponding pre-trigger enabled.
End of enumeration elements list.
EN7 : PDB Channel Pre-Trigger Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : EN_0
PDB channel's corresponding pre-trigger disabled.
0x1 : EN_1
PDB channel's corresponding pre-trigger enabled.
End of enumeration elements list.
TOS0 : PDB Channel Pre-Trigger Output Select
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : TOS_0
PDB channel's corresponding pre-trigger is in bypassed mode. The pre-trigger asserts one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1.
0x1 : TOS_1
PDB channel's corresponding pre-trigger asserts when the counter reaches the channel delay register plus one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1.
End of enumeration elements list.
TOS1 : PDB Channel Pre-Trigger Output Select
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : TOS_0
PDB channel's corresponding pre-trigger is in bypassed mode. The pre-trigger asserts one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1.
0x1 : TOS_1
PDB channel's corresponding pre-trigger asserts when the counter reaches the channel delay register plus one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1.
End of enumeration elements list.
TOS2 : PDB Channel Pre-Trigger Output Select
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : TOS_0
PDB channel's corresponding pre-trigger is in bypassed mode. The pre-trigger asserts one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1.
0x1 : TOS_1
PDB channel's corresponding pre-trigger asserts when the counter reaches the channel delay register plus one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1.
End of enumeration elements list.
TOS3 : PDB Channel Pre-Trigger Output Select
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : TOS_0
PDB channel's corresponding pre-trigger is in bypassed mode. The pre-trigger asserts one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1.
0x1 : TOS_1
PDB channel's corresponding pre-trigger asserts when the counter reaches the channel delay register plus one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1.
End of enumeration elements list.
TOS4 : PDB Channel Pre-Trigger Output Select
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : TOS_0
PDB channel's corresponding pre-trigger is in bypassed mode. The pre-trigger asserts one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1.
0x1 : TOS_1
PDB channel's corresponding pre-trigger asserts when the counter reaches the channel delay register plus one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1.
End of enumeration elements list.
TOS5 : PDB Channel Pre-Trigger Output Select
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : TOS_0
PDB channel's corresponding pre-trigger is in bypassed mode. The pre-trigger asserts one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1.
0x1 : TOS_1
PDB channel's corresponding pre-trigger asserts when the counter reaches the channel delay register plus one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1.
End of enumeration elements list.
TOS6 : PDB Channel Pre-Trigger Output Select
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : TOS_0
PDB channel's corresponding pre-trigger is in bypassed mode. The pre-trigger asserts one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1.
0x1 : TOS_1
PDB channel's corresponding pre-trigger asserts when the counter reaches the channel delay register plus one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1.
End of enumeration elements list.
TOS7 : PDB Channel Pre-Trigger Output Select
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : TOS_0
PDB channel's corresponding pre-trigger is in bypassed mode. The pre-trigger asserts one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1.
0x1 : TOS_1
PDB channel's corresponding pre-trigger asserts when the counter reaches the channel delay register plus one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1.
End of enumeration elements list.
BB0 : PDB Channel Pre-Trigger Back-to-Back Operation Enable
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : BB_0
PDB channel's corresponding pre-trigger back-to-back operation disabled.
0x1 : BB_1
PDB channel's corresponding pre-trigger back-to-back operation enabled.
End of enumeration elements list.
BB1 : PDB Channel Pre-Trigger Back-to-Back Operation Enable
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : BB_0
PDB channel's corresponding pre-trigger back-to-back operation disabled.
0x1 : BB_1
PDB channel's corresponding pre-trigger back-to-back operation enabled.
End of enumeration elements list.
BB2 : PDB Channel Pre-Trigger Back-to-Back Operation Enable
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : BB_0
PDB channel's corresponding pre-trigger back-to-back operation disabled.
0x1 : BB_1
PDB channel's corresponding pre-trigger back-to-back operation enabled.
End of enumeration elements list.
BB3 : PDB Channel Pre-Trigger Back-to-Back Operation Enable
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : BB_0
PDB channel's corresponding pre-trigger back-to-back operation disabled.
0x1 : BB_1
PDB channel's corresponding pre-trigger back-to-back operation enabled.
End of enumeration elements list.
BB4 : PDB Channel Pre-Trigger Back-to-Back Operation Enable
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : BB_0
PDB channel's corresponding pre-trigger back-to-back operation disabled.
0x1 : BB_1
PDB channel's corresponding pre-trigger back-to-back operation enabled.
End of enumeration elements list.
BB5 : PDB Channel Pre-Trigger Back-to-Back Operation Enable
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : BB_0
PDB channel's corresponding pre-trigger back-to-back operation disabled.
0x1 : BB_1
PDB channel's corresponding pre-trigger back-to-back operation enabled.
End of enumeration elements list.
BB6 : PDB Channel Pre-Trigger Back-to-Back Operation Enable
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : BB_0
PDB channel's corresponding pre-trigger back-to-back operation disabled.
0x1 : BB_1
PDB channel's corresponding pre-trigger back-to-back operation enabled.
End of enumeration elements list.
BB7 : PDB Channel Pre-Trigger Back-to-Back Operation Enable
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : BB_0
PDB channel's corresponding pre-trigger back-to-back operation disabled.
0x1 : BB_1
PDB channel's corresponding pre-trigger back-to-back operation enabled.
End of enumeration elements list.
Channel n Status register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ERR0 : PDB Channel Sequence Error Flags
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : ERR_0
Sequence error not detected on PDB channel's corresponding pre-trigger.
0x1 : ERR_1
Sequence error detected on PDB channel's corresponding pre-trigger. ADCn block can be triggered for a conversion by one pre-trigger from PDB channel n. When one conversion, which is triggered by one of the pre-triggers from PDB channel n, is in progress, new trigger from PDB channel's corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is set. Writing 0's to clear the sequence error flags.
End of enumeration elements list.
ERR1 : PDB Channel Sequence Error Flags
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : ERR_0
Sequence error not detected on PDB channel's corresponding pre-trigger.
0x1 : ERR_1
Sequence error detected on PDB channel's corresponding pre-trigger. ADCn block can be triggered for a conversion by one pre-trigger from PDB channel n. When one conversion, which is triggered by one of the pre-triggers from PDB channel n, is in progress, new trigger from PDB channel's corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is set. Writing 0's to clear the sequence error flags.
End of enumeration elements list.
ERR2 : PDB Channel Sequence Error Flags
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : ERR_0
Sequence error not detected on PDB channel's corresponding pre-trigger.
0x1 : ERR_1
Sequence error detected on PDB channel's corresponding pre-trigger. ADCn block can be triggered for a conversion by one pre-trigger from PDB channel n. When one conversion, which is triggered by one of the pre-triggers from PDB channel n, is in progress, new trigger from PDB channel's corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is set. Writing 0's to clear the sequence error flags.
End of enumeration elements list.
ERR3 : PDB Channel Sequence Error Flags
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : ERR_0
Sequence error not detected on PDB channel's corresponding pre-trigger.
0x1 : ERR_1
Sequence error detected on PDB channel's corresponding pre-trigger. ADCn block can be triggered for a conversion by one pre-trigger from PDB channel n. When one conversion, which is triggered by one of the pre-triggers from PDB channel n, is in progress, new trigger from PDB channel's corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is set. Writing 0's to clear the sequence error flags.
End of enumeration elements list.
ERR4 : PDB Channel Sequence Error Flags
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : ERR_0
Sequence error not detected on PDB channel's corresponding pre-trigger.
0x1 : ERR_1
Sequence error detected on PDB channel's corresponding pre-trigger. ADCn block can be triggered for a conversion by one pre-trigger from PDB channel n. When one conversion, which is triggered by one of the pre-triggers from PDB channel n, is in progress, new trigger from PDB channel's corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is set. Writing 0's to clear the sequence error flags.
End of enumeration elements list.
ERR5 : PDB Channel Sequence Error Flags
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : ERR_0
Sequence error not detected on PDB channel's corresponding pre-trigger.
0x1 : ERR_1
Sequence error detected on PDB channel's corresponding pre-trigger. ADCn block can be triggered for a conversion by one pre-trigger from PDB channel n. When one conversion, which is triggered by one of the pre-triggers from PDB channel n, is in progress, new trigger from PDB channel's corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is set. Writing 0's to clear the sequence error flags.
End of enumeration elements list.
ERR6 : PDB Channel Sequence Error Flags
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : ERR_0
Sequence error not detected on PDB channel's corresponding pre-trigger.
0x1 : ERR_1
Sequence error detected on PDB channel's corresponding pre-trigger. ADCn block can be triggered for a conversion by one pre-trigger from PDB channel n. When one conversion, which is triggered by one of the pre-triggers from PDB channel n, is in progress, new trigger from PDB channel's corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is set. Writing 0's to clear the sequence error flags.
End of enumeration elements list.
ERR7 : PDB Channel Sequence Error Flags
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : ERR_0
Sequence error not detected on PDB channel's corresponding pre-trigger.
0x1 : ERR_1
Sequence error detected on PDB channel's corresponding pre-trigger. ADCn block can be triggered for a conversion by one pre-trigger from PDB channel n. When one conversion, which is triggered by one of the pre-triggers from PDB channel n, is in progress, new trigger from PDB channel's corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is set. Writing 0's to clear the sequence error flags.
End of enumeration elements list.
CF : PDB Channel Flags
bits : 16 - 23 (8 bit)
access : read-write
Channel n Delay 0 register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLY : PDB Channel Delay
bits : 0 - 15 (16 bit)
access : read-write
Pulse-Out n Enable register
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POEN0 : PDB Pulse-Out Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : POEN_0
PDB Pulse-Out disabled
0x1 : POEN_1
PDB Pulse-Out enabled
End of enumeration elements list.
POEN1 : PDB Pulse-Out Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : POEN_0
PDB Pulse-Out disabled
0x1 : POEN_1
PDB Pulse-Out enabled
End of enumeration elements list.
POEN2 : PDB Pulse-Out Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : POEN_0
PDB Pulse-Out disabled
0x1 : POEN_1
PDB Pulse-Out enabled
End of enumeration elements list.
POEN3 : PDB Pulse-Out Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : POEN_0
PDB Pulse-Out disabled
0x1 : POEN_1
PDB Pulse-Out enabled
End of enumeration elements list.
POEN4 : PDB Pulse-Out Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : POEN_0
PDB Pulse-Out disabled
0x1 : POEN_1
PDB Pulse-Out enabled
End of enumeration elements list.
POEN5 : PDB Pulse-Out Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : POEN_0
PDB Pulse-Out disabled
0x1 : POEN_1
PDB Pulse-Out enabled
End of enumeration elements list.
POEN6 : PDB Pulse-Out Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : POEN_0
PDB Pulse-Out disabled
0x1 : POEN_1
PDB Pulse-Out enabled
End of enumeration elements list.
POEN7 : PDB Pulse-Out Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : POEN_0
PDB Pulse-Out disabled
0x1 : POEN_1
PDB Pulse-Out enabled
End of enumeration elements list.
Pulse-Out n Delay register
address_offset : 0x194 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLY2 : PDB Pulse-Out Delay 2
bits : 0 - 15 (16 bit)
access : read-write
DLY1 : PDB Pulse-Out Delay 1
bits : 16 - 31 (16 bit)
access : read-write
Channel n Delay 1 register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLY : PDB Channel Delay
bits : 0 - 15 (16 bit)
access : read-write
Channel n Delay 2 register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLY : PDB Channel Delay
bits : 0 - 15 (16 bit)
access : read-write
Channel n Delay 3 register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLY : PDB Channel Delay
bits : 0 - 15 (16 bit)
access : read-write
Modulus register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MOD : PDB Modulus
bits : 0 - 15 (16 bit)
access : read-write
Counter register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CNT : PDB Counter
bits : 0 - 15 (16 bit)
access : read-only
Interrupt Delay register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IDLY : PDB Interrupt Delay
bits : 0 - 15 (16 bit)
access : read-write
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.