Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x70 byte (0x0)
mem_usage : registers
protection : not protected
ADC Options Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC0TRGSEL : ADC0 trigger source select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : PDB
PDB output
0x1 : TRGMUX
TRGMUX output
End of enumeration elements list.
ADC0SWPRETRG : ADC0 software pre-trigger sources
bits : 1 - 3 (3 bit)
access : read-write
Enumeration:
0 : DISABLED
software pre-trigger disabled
0x4 : PRETR0
software pre-trigger 0
0x5 : PRETR1
software pre-trigger 1
0x6 : PRETR2
software pre-trigger 2
0x7 : PRETR3
software pre-trigger 3
End of enumeration elements list.
ADC0PRETRGSEL : ADC0 pre-trigger source select
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : PDB
PDB output
0x1 : TRGMUX
TRGMUX output
0x2 : SOFTWR
ADC0 software pre-trigger
End of enumeration elements list.
FTM Option Register 1
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FTM0SYNCBIT : FTM0 Sync Bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : NONE
No effect.
0x1 : FTM0
Write 1 to assert the TRIG1 input to FTM0. Software must clear this bit to allow other trigger sources to assert.
End of enumeration elements list.
FTM1SYNCBIT : FTM1 Sync Bit
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : NONE
No effect.
0x1 : FTM1
Write 1 to assert the TRIG1 input to FTM1. Software must clear this bit to allow other trigger sources to assert.
End of enumeration elements list.
FTM1CH0SEL : FTM1 CH0 Select
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : FTM1CH0
FTM1_CH0 input
0x1 : CMP0
CMP0 output
End of enumeration elements list.
FTM0_OUTSEL : FTM0 channel modulation select with FTM1_CH1
bits : 16 - 21 (6 bit)
access : read-write
Enumeration:
0 : NONE
No modulation with FTM1_CH1
0x1 : FTM1CH1
Modulation with FTM1_CH1
End of enumeration elements list.
System Device Identification Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PINID : Pin identification
bits : 0 - 6 (7 bit)
access : read-only
Enumeration:
0x4 : PINID_4
32-pin
0x5 : PINID_5
44-pin
0x6 : PINID_6
48-pin
End of enumeration elements list.
PROJECTID : Project ID
bits : 7 - 11 (5 bit)
access : read-only
REVID : Device revision number
bits : 12 - 15 (4 bit)
access : read-only
RAMSIZE : RAM size
bits : 16 - 19 (4 bit)
access : read-only
Enumeration:
0x3 : RAMSIZE_3
4 KB
0x4 : RAMSIZE_4
8 KB
End of enumeration elements list.
SERIESID : Kinetis Series ID
bits : 20 - 23 (4 bit)
access : read-only
Enumeration:
0x2 : SERIESID_2
Kinetis E+ series
End of enumeration elements list.
SUBFAMID : Kinetis E-series Sub-Family ID
bits : 24 - 27 (4 bit)
access : read-only
FAMILYID : Kinetis E-series Family ID
bits : 28 - 31 (4 bit)
access : read-only
Enumeration:
0x1 : KE1x
KE1x Family (Enhanced features)
End of enumeration elements list.
Chip Control register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKOUTDIV : CLKOUT divider ratio
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : DIV1
Divided by 1
0x1 : DIV2
Divided by 2
0x2 : DIV4
Divided by 4
0x3 : DIV8
Divided by 8
End of enumeration elements list.
CLKOUTSEL : CLKOUT Select
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x1 : SCGCLKOUT
SCGCLKOUT(SIRC/FIRC/SOSC/LPFLL), see SCG_CLKOUTCNFG register.
0x3 : LPO
LPO clock (128 kHz)
End of enumeration elements list.
PWTCLKSEL : PWT clock source select
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : TCLK0
PWT alternative clock is from the TCLK0 pin.
0x1 : TCLK1
PWT alternative clock is from the TCLK1 pin.
0x2 : TCLK2
PWT alternative clock is from the TCLK2 pin.
End of enumeration elements list.
RTC32KCLKSEL : RTC 32K clock input select
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
0 : OSC32K
SOSC 32 kHZ high gain clock
0x1 : RTC_CLKIN
RTC_CLKIN
End of enumeration elements list.
Flash Configuration Register 1
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLASHDIS : Flash Disable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : FLASH_EN
Flash is enabled
0x1 : FLASH_DIS
Flash is disabled
End of enumeration elements list.
FLASHDOZE : Flash Doze
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : FLASH_EN
Flash remains enabled during Doze mode
0x1 : FLASH_DIS
Flash is disabled for the duration of Doze mode
End of enumeration elements list.
PFSIZE : Program flash size
bits : 24 - 27 (4 bit)
access : read-only
Enumeration:
0 : SIZE8K
8 KB of program flash memory, 1 KB protection region
0x1 : SIZE16K
16 KB of program flash memory, 1 KB protection region
0x3 : SIZE32K
32 KB of program flash memory, 1 KB protection region
0x5 : SIZE64K
64 KB of program flash memory, 2 KB protection region
End of enumeration elements list.
Flash Configuration Register 2
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MAXADDR0 : Max address block 0
bits : 24 - 30 (7 bit)
access : read-only
Unique Identification Register High
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
UID127_96 : Unique Identification
bits : 0 - 31 (32 bit)
access : read-only
Unique Identification Register Mid-High
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
UID95_64 : Unique Identification
bits : 0 - 31 (32 bit)
access : read-only
Unique Identification Register Mid Low
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
UID63_32 : Unique Identification
bits : 0 - 31 (32 bit)
access : read-only
Unique Identification Register Low
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
UID31_0 : Unique Identification
bits : 0 - 31 (32 bit)
access : read-only
Miscellaneous Control register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SW_TRG : Software Trigger bit to TRGMUX
bits : 0 - 0 (1 bit)
access : read-write
FTM Option Register 0
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FTM0FLTxSEL : FTM0 Fault x Select
bits : 0 - 2 (3 bit)
access : read-write
FTM0CLKSEL : FTM0 External Clock Pin Select
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : TCLK0
FTM0 external clock driven by TCLK0 pin.
0x1 : TCLK1
FTM0 external clock driven by TCLK1 pin.
0x2 : TCLK2
FTM0 external clock driven by TCLK2 pin.
0x3 : NONE
No clock input
End of enumeration elements list.
FTM1CLKSEL : FTM1 External Clock Pin Select
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
0 : TCLK0
FTM1 external clock driven by TCLK0 pin.
0x1 : TCLK1
FTM1 external clock driven by TCLK1 pin.
0x2 : TCLK2
FTM1 external clock driven by TCLK2 pin.
0x3 : NONE
No clock input
End of enumeration elements list.
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