Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected
Debug Halting Control and Status Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DHCSR_Read_DHCSR_Write
reset_Mask : 0x0
C_DEBUGEN : Halting debug enable bit. If a debugger writes to DHCSR to change the value of this bit from 0 to 1, it must also write 0 to the C_MASKINTS bit, otherwise behavior is UNPREDICTABLE.This bit can only be set to 1 from the DAP, it cannot be set to 1 under software control.This bit is 0 after a Power-on reset.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : C_DEBUGEN_0
Disabled
0x1 : C_DEBUGEN_1
Enabled
End of enumeration elements list.
C_HALT : Processor halt bit. This bit is UNKNOWN after a Power-on reset.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : C_HALT_0
No effect.
0x1 : C_HALT_1
Halt the processor.
End of enumeration elements list.
C_STEP : Processor step bit.This bit is UNKNOWN after a Power-on reset.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : C_STEP_0
No effect.
0x1 : C_STEP_1
Step the processor.
End of enumeration elements list.
C_MASKINTS : C_MASKINTS bit. When debug is enabled, the debugger can write to this bit to mask PendSV, SysTick and external configurable interrupts. The effect of any attempt to change the value of this bit is UNPREDICTABLE unless both:- before the write to DHCSR, the value of the C_HALT bit is 1.- the write to the DHCSR that changes the C_MASKINTS bit also writes 1 to the C_HALT bit.This means that a single write to DHCSR cannot set the C_HALT to 0 and change the value of the C_MASKINTS bit.The bit does not affect NMI. When DHCSR.C_DEBUGEN is set to 0, the value of this bit is UNKNOWN.This bit is UNKNOWN after a Power-on reset.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : C_MASKINTS_0
Do not mask.
0x1 : C_MASKINTS_1
Mask PenSV, SysTick and external configurable interrupts.
End of enumeration elements list.
S_REGRDY : S_REGRDY bit. A handshake flag for transfers through the DCRDR:- Writing to DCRSR clears the bit to 0.- Completion of the DCRDR transfer then sets the bit to 1.This bit is valid only when the processor is in Debug state, otherwise the bit is UNKNOWN.
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
0 : S_REGRDY_0
There has been a write to the DCRDR, but the transfer is not complete.
0x1 : S_REGRDY_1
The transfer to or from the DCRDR is complete.
End of enumeration elements list.
S_HALT : S_HALT bit. Indicates whether the processor is in Debug state.
bits : 17 - 17 (1 bit)
access : read-only
Enumeration:
0 : S_HALT_0
Not in Debug state.
0x1 : S_HALT_1
In Debug state.
End of enumeration elements list.
S_SLEEP : S_SLEEP bit. Indicates whether the processor is sleeping.The debugger must set the C_HALT bit to 1 to gain control, or wait for an interrupt or other wakeup event to wakeup the system.
bits : 18 - 18 (1 bit)
access : read-only
Enumeration:
0 : S_SLEEP_0
Not sleeping.
0x1 : S_SLEEP_1
Sleeping.
End of enumeration elements list.
S_LOCKUP : S_LOCKUP bit. Indicates whether the processor is locked up because of an unrecoverable exception.This bit can only be read as 1 by a remote debugger, using the DAP. The value of 1 indicates that the processor is running but locked up.The bit clears to 0 when the processor enters Debug state.
bits : 19 - 19 (1 bit)
access : read-only
Enumeration:
0 : S_LOCKUP_0
Not locked up
0x1 : S_LOCKUP_1
Locked up
End of enumeration elements list.
S_RETIRE_ST : S_RETIRE_ST bit. Indicates whether the processor has completed the execution of an instruction since the last read of DHCSR.This is a sticky bit, that clears to 0 on a read of DHCSR.A debugger can check this bit to determine if the processor is stalled on a load, store or fetch access.This bit is UNKNOWN after a Power-on or Local reset, but then is set to 1 as soon as the processor executes and retires an instruction.
bits : 24 - 24 (1 bit)
access : read-only
Enumeration:
0 : S_RETIRE_ST_0
No instruction retired since last DHCSR read.
0x1 : S_RETIRE_ST_1
At least one instruction retired since last DHCSR read.
End of enumeration elements list.
S_RESET_ST : S_RESET_ST bit. Indicates whether the processor has been reset since the last read of DHCSR.This is a sticky bit, that clears to 0 on a read of DHCSR.
bits : 25 - 25 (1 bit)
access : read-only
Enumeration:
0 : S_RESET_ST_0
No reset since last DHCSR read.
0x1 : S_RESET_ST_1
At least one reset since last DHCSR read.
End of enumeration elements list.
Debug Halting Control and Status Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DHCSR_Read_DHCSR_Write
reset_Mask : 0x0
C_DEBUGEN : Halting debug enable bit. If a debugger writes to DHCSR to change the value of this bit from 0 to 1, it must also write 0 to the C_MASKINTS bit, otherwise behavior is UNPREDICTABLE.This bit can only be set to 1 from the DAP, it cannot be set to 1 under software control.This bit is 0 after a Power-on reset.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : C_DEBUGEN_0
Disabled
0x1 : C_DEBUGEN_1
Enabled
End of enumeration elements list.
C_HALT : Processor halt bit. This bit is UNKNOWN after a Power-on reset.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : C_HALT_0
No effect.
0x1 : C_HALT_1
Halt the processor.
End of enumeration elements list.
C_STEP : Processor step bit.This bit is UNKNOWN after a Power-on reset.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : C_STEP_0
No effect.
0x1 : C_STEP_1
Step the processor.
End of enumeration elements list.
C_MASKINTS : C_MASKINTS bit. When debug is enabled, the debugger can write to this bit to mask PendSV, SysTick and external configurable interrupts. The effect of any attempt to change the value of this bit is UNPREDICTABLE unless both:- before the write to DHCSR, the value of the C_HALT bit is 1.- the write to the DHCSR that changes the C_MASKINTS bit also writes 1 to the C_HALT bit.This means that a single write to DHCSR cannot set the C_HALT to 0 and change the value of the C_MASKINTS bit.The bit does not affect NMI. When DHCSR.C_DEBUGEN is set to 0, the value of this bit is UNKNOWN.This bit is UNKNOWN after a Power-on reset.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : C_MASKINTS_0
Do not mask.
0x1 : C_MASKINTS_1
Mask PenSV, SysTick and external configurable interrupts.
End of enumeration elements list.
DBGKEY : Debug key:Software must write 0xA05F to this field to enable write accesses to bits [15:0], otherwise the processor ignores the write access.
bits : 16 - 31 (16 bit)
access : write-only
Debug Core Register Selector Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REGSEL : REGSEL bits. Specifies the ARM core register, special-purpose register, or Floating-point extension register, to transfer.
bits : 0 - 4 (5 bit)
access : write-only
REGWnR : REGWnR bit. Specifies the access type for the transfer.
bits : 16 - 16 (1 bit)
access : write-only
Enumeration:
0 : REGWnR_0
Read
0x1 : REGWnR_1
Write
End of enumeration elements list.
Debug Core Register Data Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBGTMP : DBGTMP bits. Data temporary cache, for reading and writing the ARM core registers, special-purpose registers, and Floating-point extension registers.The value of this register is UNKNOWN:- on reset- if the processor is in Debug state, the debugger has written to DCRSR since entering Debug state and DHCSR.S_REGRDY is set to 0.
bits : 0 - 31 (32 bit)
access : read-write
Debug Exception and Monitor Control Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VC_CORERESET : VC_CORERESET bit. Enable Reset Vector Catch. This causes a Local reset to halt a running system.If DHCSR.C_DEBUGEN is set to 0, the processor ignores the value of this bit.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : VC_CORERESET_0
Reset Vector Catch disabled.
0x1 : VC_CORERESET_1
Reset Vector Catch enabled.
End of enumeration elements list.
VC_HARDERR : VC_HARDERR bit. Enable halting debug trap on a HardFault exception.If DHCSR.C_DEBUGEN is set to 0, the processor ignores the value of this bit.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : VC_HARDERR_0
Halting debug trap disabled.
0x1 : VC_HARDERR_1
Halting debug trap enabled.
End of enumeration elements list.
DWTENA : DWTENA bit. Global enable for all features configured and controlled by the DWT unit.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : DWTENA_0
DWT disabled.
0x1 : DWTENA_1
DWT enabled.
End of enumeration elements list.
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