\n

FGPIOC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : registers
protection : not protected

Registers

PDOR

PDIR

PDDR

PSOR

PCOR

PTOR


PDOR

Port Data Output Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDOR PDOR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDO

PDO : Port Data Output
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

0 : PDO_0

Logic level 0 is driven on pin, provided pin is configured for general-purpose output.

0x1 : PDO_1

Logic level 1 is driven on pin, provided pin is configured for general-purpose output.

End of enumeration elements list.


PDIR

Port Data Input Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PDIR PDIR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDI

PDI : Port Data Input
bits : 0 - 31 (32 bit)
access : read-only

Enumeration:

0 : PDI_0

Pin logic level is logic 0, or is not configured for use by digital function.

0x1 : PDI_1

Pin logic level is logic 1.

End of enumeration elements list.


PDDR

Port Data Direction Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDDR PDDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDD

PDD : Port Data Direction
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

0 : PDD_0

Pin is configured as general-purpose input, for the GPIO function.

0x1 : PDD_1

Pin is configured as general-purpose output, for the GPIO function.

End of enumeration elements list.


PSOR

Port Set Output Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PSOR PSOR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PTSO

PTSO : Port Set Output
bits : 0 - 31 (32 bit)
access : write-only

Enumeration:

0 : PTSO_0

Corresponding bit in PDORn does not change.

0x1 : PTSO_1

Corresponding bit in PDORn is set to logic 1.

End of enumeration elements list.


PCOR

Port Clear Output Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PCOR PCOR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PTCO

PTCO : Port Clear Output
bits : 0 - 31 (32 bit)
access : write-only

Enumeration:

0 : PTCO_0

Corresponding bit in PDORn does not change.

0x1 : PTCO_1

Corresponding bit in PDORn is cleared to logic 0.

End of enumeration elements list.


PTOR

Port Toggle Output Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PTOR PTOR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PTTO

PTTO : Port Toggle Output
bits : 0 - 31 (32 bit)
access : write-only

Enumeration:

0 : PTTO_0

Corresponding bit in PDORn does not change.

0x1 : PTTO_1

Corresponding bit in PDORn is set to the inverse of its existing logic state.

End of enumeration elements list.



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