\n
address_offset : 0x8 Bytes (0x0)
size : 0xD2C byte (0x0)
mem_usage : registers
protection : not protected
Auxiliary Control Register,
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CPUID Base Register
address_offset : 0xD00 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
REVISION : Minor revision number m in the rnpm revision status
bits : 0 - 3 (4 bit)
access : read-only
PARTNO : Indicates part number
bits : 4 - 15 (12 bit)
access : read-only
ARCHITECTURE : Indicates the architecture
bits : 16 - 19 (4 bit)
access : read-only
VARIANT : Major revision number n in the npm revision status
bits : 20 - 23 (4 bit)
access : read-only
IMPLEMENTER : Implementer code
bits : 24 - 31 (8 bit)
access : read-only
Interrupt Control and State Register
address_offset : 0xD04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VECTPENDING : Exception number of the highest priority pending enabled exception
bits : 12 - 17 (6 bit)
access : read-only
PENDSTCLR : SysTick exception clear-pending bit
bits : 25 - 25 (1 bit)
access : write-only
Enumeration:
#0 : 0
no effect
#1 : 1
removes the pending state from the SysTick exception
End of enumeration elements list.
PENDSTSET : SysTick exception set-pending bit
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
write: no effect; read: SysTick exception is not pending
#1 : 1
write: changes SysTick exception state to pending; read: SysTick exception is pending
End of enumeration elements list.
PENDSVCLR : PendSV clear-pending bit
bits : 27 - 27 (1 bit)
access : write-only
Enumeration:
#0 : 0
no effect
#1 : 1
removes the pending state from the PendSV exception
End of enumeration elements list.
PENDSVSET : PendSV set-pending bit
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
write: no effect; read: PendSV exception is not pending
#1 : 1
write: changes PendSV exception state to pending; read: PendSV exception is pending
End of enumeration elements list.
NMIPENDSET : NMI set-pending bit
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
write: no effect; read: NMI exception is not pending
#1 : 1
write: changes NMI exception state to pending; read: NMI exception is pending
End of enumeration elements list.
Vector Table Offset Register
address_offset : 0xD08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TBLOFF : Vector table base offset
bits : 7 - 31 (25 bit)
access : read-write
Application Interrupt and Reset Control Register
address_offset : 0xD0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VECTCLRACTIVE : Reserved for Debug use
bits : 1 - 1 (1 bit)
access : write-only
SYSRESETREQ : System reset request
bits : 2 - 2 (1 bit)
access : write-only
Enumeration:
#0 : 0
no system reset request
#1 : 1
asserts a signal to the outer system that requests a reset
End of enumeration elements list.
ENDIANNESS : Data endianness bit
bits : 15 - 15 (1 bit)
access : read-only
Enumeration:
#0 : 0
Little-endian
#1 : 1
Big-endian
End of enumeration elements list.
VECTKEY : Register key
bits : 16 - 31 (16 bit)
access : read-write
System Control Register
address_offset : 0xD10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLEEPONEXIT : Indicates sleep-on-exit when returning from Handler mode to Thread mode
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
do not sleep when returning to Thread mode
#1 : 1
enter sleep, or deep sleep, on return from an ISR
End of enumeration elements list.
SLEEPDEEP : Controls whether the processor uses sleep or deep sleep as its low power mode
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
sleep
#1 : 1
deep sleep
End of enumeration elements list.
SEVONPEND : Send Event on Pending bit
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded
#1 : 1
enabled events and all interrupts, including disabled interrupts, can wakeup the processor
End of enumeration elements list.
Configuration and Control Register
address_offset : 0xD14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
UNALIGN_TRP : Always reads as one, indicates that all unaligned accesses generate a HardFault
bits : 3 - 3 (1 bit)
access : read-only
STKALIGN : Indicates stack alignment on exception entry
bits : 9 - 9 (1 bit)
access : read-only
System Handler Priority Register 2
address_offset : 0xD1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_11 : Priority of system handler 11, SVCall
bits : 30 - 31 (2 bit)
access : read-write
System Handler Priority Register 3
address_offset : 0xD20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_14 : Priority of system handler 14, PendSV
bits : 22 - 23 (2 bit)
access : read-write
PRI_15 : Priority of system handler 15, SysTick exception
bits : 30 - 31 (2 bit)
access : read-write
System Handler Control and State Register
address_offset : 0xD24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SVCALLPENDED : no description available
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
exception is not pending
#1 : 1
exception is pending
End of enumeration elements list.
Debug Fault Status Register
address_offset : 0xD30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HALTED : no description available
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No active halt request debug event
#1 : 1
Halt request debug event active
End of enumeration elements list.
BKPT : no description available
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No current breakpoint debug event
#1 : 1
At least one current breakpoint debug event
End of enumeration elements list.
DWTTRAP : no description available
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No current debug events generated by the DWT
#1 : 1
At least one current debug event generated by the DWT
End of enumeration elements list.
VCATCH : no description available
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
No Vector catch triggered
#1 : 1
Vector catch triggered
End of enumeration elements list.
EXTERNAL : no description available
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
No EDBGRQ debug event
#1 : 1
EDBGRQ debug event
End of enumeration elements list.
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