Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0xCC byte (0x0)
mem_usage : registers
protection : not protected
Pin Control Register n
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1 : 1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#1 : 1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Open drain output is disabled on the corresponding pin.
#1 : 1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin disabled (Alternative 0) (analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip-specific).
#011 : 011
Alternative 3 (chip-specific).
#100 : 100
Alternative 4 (chip-specific).
#101 : 101
Alternative 5 (chip-specific).
#110 : 110
Alternative 6 (chip-specific).
#111 : 111
Alternative 7 (chip-specific).
End of enumeration elements list.
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register fields [15:0] are not locked.
#1 : 1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt Status Flag (ISF) is disabled.
#0001 : 0001
ISF flag and DMA request on rising edge.
#0010 : 0010
ISF flag and DMA request on falling edge.
#0011 : 0011
ISF flag and DMA request on either edge.
#1000 : 1000
ISF flag and Interrupt when logic 0.
#1001 : 1001
ISF flag and Interrupt on rising-edge.
#1010 : 1010
ISF flag and Interrupt on falling-edge.
#1011 : 1011
ISF flag and Interrupt on either edge.
#1100 : 1100
ISF flag and Interrupt when logic 1.
End of enumeration elements list.
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt is not detected.
#1 : 1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1 : 1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#1 : 1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Open drain output is disabled on the corresponding pin.
#1 : 1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin disabled (Alternative 0) (analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip-specific).
#011 : 011
Alternative 3 (chip-specific).
#100 : 100
Alternative 4 (chip-specific).
#101 : 101
Alternative 5 (chip-specific).
#110 : 110
Alternative 6 (chip-specific).
#111 : 111
Alternative 7 (chip-specific).
End of enumeration elements list.
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register fields [15:0] are not locked.
#1 : 1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt Status Flag (ISF) is disabled.
#0001 : 0001
ISF flag and DMA request on rising edge.
#0010 : 0010
ISF flag and DMA request on falling edge.
#0011 : 0011
ISF flag and DMA request on either edge.
#1000 : 1000
ISF flag and Interrupt when logic 0.
#1001 : 1001
ISF flag and Interrupt on rising-edge.
#1010 : 1010
ISF flag and Interrupt on falling-edge.
#1011 : 1011
ISF flag and Interrupt on either edge.
#1100 : 1100
ISF flag and Interrupt when logic 1.
End of enumeration elements list.
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt is not detected.
#1 : 1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1 : 1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#1 : 1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Open drain output is disabled on the corresponding pin.
#1 : 1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin disabled (Alternative 0) (analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip-specific).
#011 : 011
Alternative 3 (chip-specific).
#100 : 100
Alternative 4 (chip-specific).
#101 : 101
Alternative 5 (chip-specific).
#110 : 110
Alternative 6 (chip-specific).
#111 : 111
Alternative 7 (chip-specific).
End of enumeration elements list.
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register fields [15:0] are not locked.
#1 : 1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt Status Flag (ISF) is disabled.
#0001 : 0001
ISF flag and DMA request on rising edge.
#0010 : 0010
ISF flag and DMA request on falling edge.
#0011 : 0011
ISF flag and DMA request on either edge.
#1000 : 1000
ISF flag and Interrupt when logic 0.
#1001 : 1001
ISF flag and Interrupt on rising-edge.
#1010 : 1010
ISF flag and Interrupt on falling-edge.
#1011 : 1011
ISF flag and Interrupt on either edge.
#1100 : 1100
ISF flag and Interrupt when logic 1.
End of enumeration elements list.
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt is not detected.
#1 : 1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1 : 1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#1 : 1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Open drain output is disabled on the corresponding pin.
#1 : 1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin disabled (Alternative 0) (analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip-specific).
#011 : 011
Alternative 3 (chip-specific).
#100 : 100
Alternative 4 (chip-specific).
#101 : 101
Alternative 5 (chip-specific).
#110 : 110
Alternative 6 (chip-specific).
#111 : 111
Alternative 7 (chip-specific).
End of enumeration elements list.
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register fields [15:0] are not locked.
#1 : 1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt Status Flag (ISF) is disabled.
#0001 : 0001
ISF flag and DMA request on rising edge.
#0010 : 0010
ISF flag and DMA request on falling edge.
#0011 : 0011
ISF flag and DMA request on either edge.
#1000 : 1000
ISF flag and Interrupt when logic 0.
#1001 : 1001
ISF flag and Interrupt on rising-edge.
#1010 : 1010
ISF flag and Interrupt on falling-edge.
#1011 : 1011
ISF flag and Interrupt on either edge.
#1100 : 1100
ISF flag and Interrupt when logic 1.
End of enumeration elements list.
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt is not detected.
#1 : 1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1 : 1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#1 : 1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Open drain output is disabled on the corresponding pin.
#1 : 1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin disabled (Alternative 0) (analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip-specific).
#011 : 011
Alternative 3 (chip-specific).
#100 : 100
Alternative 4 (chip-specific).
#101 : 101
Alternative 5 (chip-specific).
#110 : 110
Alternative 6 (chip-specific).
#111 : 111
Alternative 7 (chip-specific).
End of enumeration elements list.
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register fields [15:0] are not locked.
#1 : 1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt Status Flag (ISF) is disabled.
#0001 : 0001
ISF flag and DMA request on rising edge.
#0010 : 0010
ISF flag and DMA request on falling edge.
#0011 : 0011
ISF flag and DMA request on either edge.
#1000 : 1000
ISF flag and Interrupt when logic 0.
#1001 : 1001
ISF flag and Interrupt on rising-edge.
#1010 : 1010
ISF flag and Interrupt on falling-edge.
#1011 : 1011
ISF flag and Interrupt on either edge.
#1100 : 1100
ISF flag and Interrupt when logic 1.
End of enumeration elements list.
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt is not detected.
#1 : 1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1 : 1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#1 : 1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Open drain output is disabled on the corresponding pin.
#1 : 1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin disabled (Alternative 0) (analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip-specific).
#011 : 011
Alternative 3 (chip-specific).
#100 : 100
Alternative 4 (chip-specific).
#101 : 101
Alternative 5 (chip-specific).
#110 : 110
Alternative 6 (chip-specific).
#111 : 111
Alternative 7 (chip-specific).
End of enumeration elements list.
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register fields [15:0] are not locked.
#1 : 1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt Status Flag (ISF) is disabled.
#0001 : 0001
ISF flag and DMA request on rising edge.
#0010 : 0010
ISF flag and DMA request on falling edge.
#0011 : 0011
ISF flag and DMA request on either edge.
#1000 : 1000
ISF flag and Interrupt when logic 0.
#1001 : 1001
ISF flag and Interrupt on rising-edge.
#1010 : 1010
ISF flag and Interrupt on falling-edge.
#1011 : 1011
ISF flag and Interrupt on either edge.
#1100 : 1100
ISF flag and Interrupt when logic 1.
End of enumeration elements list.
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt is not detected.
#1 : 1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1 : 1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#1 : 1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Open drain output is disabled on the corresponding pin.
#1 : 1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin disabled (Alternative 0) (analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip-specific).
#011 : 011
Alternative 3 (chip-specific).
#100 : 100
Alternative 4 (chip-specific).
#101 : 101
Alternative 5 (chip-specific).
#110 : 110
Alternative 6 (chip-specific).
#111 : 111
Alternative 7 (chip-specific).
End of enumeration elements list.
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register fields [15:0] are not locked.
#1 : 1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt Status Flag (ISF) is disabled.
#0001 : 0001
ISF flag and DMA request on rising edge.
#0010 : 0010
ISF flag and DMA request on falling edge.
#0011 : 0011
ISF flag and DMA request on either edge.
#1000 : 1000
ISF flag and Interrupt when logic 0.
#1001 : 1001
ISF flag and Interrupt on rising-edge.
#1010 : 1010
ISF flag and Interrupt on falling-edge.
#1011 : 1011
ISF flag and Interrupt on either edge.
#1100 : 1100
ISF flag and Interrupt when logic 1.
End of enumeration elements list.
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt is not detected.
#1 : 1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
End of enumeration elements list.
Global Pin Control Low Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPWD : Global Pin Write Data
bits : 0 - 15 (16 bit)
access : read-write
GPWE0 : Global Pin Write Enable
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding Pin Control Register is not updated with the value in GPWD.
#1 : 1
Corresponding Pin Control Register is updated with the value in GPWD.
End of enumeration elements list.
GPWE1 : Global Pin Write Enable
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding Pin Control Register is not updated with the value in GPWD.
#1 : 1
Corresponding Pin Control Register is updated with the value in GPWD.
End of enumeration elements list.
GPWE2 : Global Pin Write Enable
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding Pin Control Register is not updated with the value in GPWD.
#1 : 1
Corresponding Pin Control Register is updated with the value in GPWD.
End of enumeration elements list.
GPWE3 : Global Pin Write Enable
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding Pin Control Register is not updated with the value in GPWD.
#1 : 1
Corresponding Pin Control Register is updated with the value in GPWD.
End of enumeration elements list.
GPWE4 : Global Pin Write Enable
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding Pin Control Register is not updated with the value in GPWD.
#1 : 1
Corresponding Pin Control Register is updated with the value in GPWD.
End of enumeration elements list.
GPWE5 : Global Pin Write Enable
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding Pin Control Register is not updated with the value in GPWD.
#1 : 1
Corresponding Pin Control Register is updated with the value in GPWD.
End of enumeration elements list.
GPWE6 : Global Pin Write Enable
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding Pin Control Register is not updated with the value in GPWD.
#1 : 1
Corresponding Pin Control Register is updated with the value in GPWD.
End of enumeration elements list.
GPWE7 : Global Pin Write Enable
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding Pin Control Register is not updated with the value in GPWD.
#1 : 1
Corresponding Pin Control Register is updated with the value in GPWD.
End of enumeration elements list.
GPWE8 : Global Pin Write Enable
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding Pin Control Register is not updated with the value in GPWD.
#1 : 1
Corresponding Pin Control Register is updated with the value in GPWD.
End of enumeration elements list.
GPWE9 : Global Pin Write Enable
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding Pin Control Register is not updated with the value in GPWD.
#1 : 1
Corresponding Pin Control Register is updated with the value in GPWD.
End of enumeration elements list.
GPWE10 : Global Pin Write Enable
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding Pin Control Register is not updated with the value in GPWD.
#1 : 1
Corresponding Pin Control Register is updated with the value in GPWD.
End of enumeration elements list.
GPWE11 : Global Pin Write Enable
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding Pin Control Register is not updated with the value in GPWD.
#1 : 1
Corresponding Pin Control Register is updated with the value in GPWD.
End of enumeration elements list.
GPWE12 : Global Pin Write Enable
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding Pin Control Register is not updated with the value in GPWD.
#1 : 1
Corresponding Pin Control Register is updated with the value in GPWD.
End of enumeration elements list.
GPWE13 : Global Pin Write Enable
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding Pin Control Register is not updated with the value in GPWD.
#1 : 1
Corresponding Pin Control Register is updated with the value in GPWD.
End of enumeration elements list.
GPWE14 : Global Pin Write Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding Pin Control Register is not updated with the value in GPWD.
#1 : 1
Corresponding Pin Control Register is updated with the value in GPWD.
End of enumeration elements list.
GPWE15 : Global Pin Write Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding Pin Control Register is not updated with the value in GPWD.
#1 : 1
Corresponding Pin Control Register is updated with the value in GPWD.
End of enumeration elements list.
Global Pin Control High Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPWD : Global Pin Write Data
bits : 0 - 15 (16 bit)
access : read-write
GPWE0 : Global Pin Write Enable
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding Pin Control Register is not updated with the value in GPWD.
#1 : 1
Corresponding Pin Control Register is updated with the value in GPWD.
End of enumeration elements list.
GPWE1 : Global Pin Write Enable
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding Pin Control Register is not updated with the value in GPWD.
#1 : 1
Corresponding Pin Control Register is updated with the value in GPWD.
End of enumeration elements list.
GPWE2 : Global Pin Write Enable
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding Pin Control Register is not updated with the value in GPWD.
#1 : 1
Corresponding Pin Control Register is updated with the value in GPWD.
End of enumeration elements list.
GPWE3 : Global Pin Write Enable
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding Pin Control Register is not updated with the value in GPWD.
#1 : 1
Corresponding Pin Control Register is updated with the value in GPWD.
End of enumeration elements list.
GPWE4 : Global Pin Write Enable
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding Pin Control Register is not updated with the value in GPWD.
#1 : 1
Corresponding Pin Control Register is updated with the value in GPWD.
End of enumeration elements list.
GPWE5 : Global Pin Write Enable
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding Pin Control Register is not updated with the value in GPWD.
#1 : 1
Corresponding Pin Control Register is updated with the value in GPWD.
End of enumeration elements list.
GPWE6 : Global Pin Write Enable
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding Pin Control Register is not updated with the value in GPWD.
#1 : 1
Corresponding Pin Control Register is updated with the value in GPWD.
End of enumeration elements list.
GPWE7 : Global Pin Write Enable
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding Pin Control Register is not updated with the value in GPWD.
#1 : 1
Corresponding Pin Control Register is updated with the value in GPWD.
End of enumeration elements list.
GPWE8 : Global Pin Write Enable
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding Pin Control Register is not updated with the value in GPWD.
#1 : 1
Corresponding Pin Control Register is updated with the value in GPWD.
End of enumeration elements list.
GPWE9 : Global Pin Write Enable
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding Pin Control Register is not updated with the value in GPWD.
#1 : 1
Corresponding Pin Control Register is updated with the value in GPWD.
End of enumeration elements list.
GPWE10 : Global Pin Write Enable
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding Pin Control Register is not updated with the value in GPWD.
#1 : 1
Corresponding Pin Control Register is updated with the value in GPWD.
End of enumeration elements list.
GPWE11 : Global Pin Write Enable
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding Pin Control Register is not updated with the value in GPWD.
#1 : 1
Corresponding Pin Control Register is updated with the value in GPWD.
End of enumeration elements list.
GPWE12 : Global Pin Write Enable
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding Pin Control Register is not updated with the value in GPWD.
#1 : 1
Corresponding Pin Control Register is updated with the value in GPWD.
End of enumeration elements list.
GPWE13 : Global Pin Write Enable
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding Pin Control Register is not updated with the value in GPWD.
#1 : 1
Corresponding Pin Control Register is updated with the value in GPWD.
End of enumeration elements list.
GPWE14 : Global Pin Write Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding Pin Control Register is not updated with the value in GPWD.
#1 : 1
Corresponding Pin Control Register is updated with the value in GPWD.
End of enumeration elements list.
GPWE15 : Global Pin Write Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding Pin Control Register is not updated with the value in GPWD.
#1 : 1
Corresponding Pin Control Register is updated with the value in GPWD.
End of enumeration elements list.
Interrupt Status Flag Register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISF0 : Interrupt Status Flag
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt is not detected.
#1 : 1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
End of enumeration elements list.
ISF1 : Interrupt Status Flag
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt is not detected.
#1 : 1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
End of enumeration elements list.
ISF2 : Interrupt Status Flag
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt is not detected.
#1 : 1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
End of enumeration elements list.
ISF3 : Interrupt Status Flag
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt is not detected.
#1 : 1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
End of enumeration elements list.
ISF4 : Interrupt Status Flag
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt is not detected.
#1 : 1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
End of enumeration elements list.
ISF5 : Interrupt Status Flag
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt is not detected.
#1 : 1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
End of enumeration elements list.
ISF6 : Interrupt Status Flag
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt is not detected.
#1 : 1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
End of enumeration elements list.
ISF7 : Interrupt Status Flag
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt is not detected.
#1 : 1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
End of enumeration elements list.
ISF8 : Interrupt Status Flag
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt is not detected.
#1 : 1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
End of enumeration elements list.
ISF9 : Interrupt Status Flag
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt is not detected.
#1 : 1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
End of enumeration elements list.
ISF10 : Interrupt Status Flag
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt is not detected.
#1 : 1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
End of enumeration elements list.
ISF11 : Interrupt Status Flag
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt is not detected.
#1 : 1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
End of enumeration elements list.
ISF12 : Interrupt Status Flag
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt is not detected.
#1 : 1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
End of enumeration elements list.
ISF13 : Interrupt Status Flag
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt is not detected.
#1 : 1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
End of enumeration elements list.
ISF14 : Interrupt Status Flag
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt is not detected.
#1 : 1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
End of enumeration elements list.
ISF15 : Interrupt Status Flag
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt is not detected.
#1 : 1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
End of enumeration elements list.
ISF16 : Interrupt Status Flag
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt is not detected.
#1 : 1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
End of enumeration elements list.
ISF17 : Interrupt Status Flag
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt is not detected.
#1 : 1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
End of enumeration elements list.
ISF18 : Interrupt Status Flag
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt is not detected.
#1 : 1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
End of enumeration elements list.
ISF19 : Interrupt Status Flag
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt is not detected.
#1 : 1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
End of enumeration elements list.
ISF20 : Interrupt Status Flag
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt is not detected.
#1 : 1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
End of enumeration elements list.
ISF21 : Interrupt Status Flag
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt is not detected.
#1 : 1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
End of enumeration elements list.
ISF22 : Interrupt Status Flag
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt is not detected.
#1 : 1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
End of enumeration elements list.
ISF23 : Interrupt Status Flag
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt is not detected.
#1 : 1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
End of enumeration elements list.
ISF24 : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt is not detected.
#1 : 1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
End of enumeration elements list.
ISF25 : Interrupt Status Flag
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt is not detected.
#1 : 1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
End of enumeration elements list.
ISF26 : Interrupt Status Flag
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt is not detected.
#1 : 1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
End of enumeration elements list.
ISF27 : Interrupt Status Flag
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt is not detected.
#1 : 1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
End of enumeration elements list.
ISF28 : Interrupt Status Flag
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt is not detected.
#1 : 1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
End of enumeration elements list.
ISF29 : Interrupt Status Flag
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt is not detected.
#1 : 1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
End of enumeration elements list.
ISF30 : Interrupt Status Flag
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt is not detected.
#1 : 1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
End of enumeration elements list.
ISF31 : Interrupt Status Flag
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt is not detected.
#1 : 1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
End of enumeration elements list.
Pin Control Register n
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1 : 1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#1 : 1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Open drain output is disabled on the corresponding pin.
#1 : 1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin disabled (Alternative 0) (analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip-specific).
#011 : 011
Alternative 3 (chip-specific).
#100 : 100
Alternative 4 (chip-specific).
#101 : 101
Alternative 5 (chip-specific).
#110 : 110
Alternative 6 (chip-specific).
#111 : 111
Alternative 7 (chip-specific).
End of enumeration elements list.
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register fields [15:0] are not locked.
#1 : 1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt Status Flag (ISF) is disabled.
#0001 : 0001
ISF flag and DMA request on rising edge.
#0010 : 0010
ISF flag and DMA request on falling edge.
#0011 : 0011
ISF flag and DMA request on either edge.
#1000 : 1000
ISF flag and Interrupt when logic 0.
#1001 : 1001
ISF flag and Interrupt on rising-edge.
#1010 : 1010
ISF flag and Interrupt on falling-edge.
#1011 : 1011
ISF flag and Interrupt on either edge.
#1100 : 1100
ISF flag and Interrupt when logic 1.
End of enumeration elements list.
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt is not detected.
#1 : 1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
End of enumeration elements list.
Digital Filter Enable Register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DFE0 : Digital Filter Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero.
#1 : 1
Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
DFE1 : Digital Filter Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero.
#1 : 1
Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
DFE2 : Digital Filter Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero.
#1 : 1
Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
DFE3 : Digital Filter Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero.
#1 : 1
Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
DFE4 : Digital Filter Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero.
#1 : 1
Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
DFE5 : Digital Filter Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero.
#1 : 1
Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
DFE6 : Digital Filter Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero.
#1 : 1
Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
DFE7 : Digital Filter Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero.
#1 : 1
Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
DFE8 : Digital Filter Enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero.
#1 : 1
Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
DFE9 : Digital Filter Enable
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero.
#1 : 1
Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
DFE10 : Digital Filter Enable
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero.
#1 : 1
Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
DFE11 : Digital Filter Enable
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero.
#1 : 1
Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
DFE12 : Digital Filter Enable
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero.
#1 : 1
Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
DFE13 : Digital Filter Enable
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero.
#1 : 1
Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
DFE14 : Digital Filter Enable
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero.
#1 : 1
Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
DFE15 : Digital Filter Enable
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero.
#1 : 1
Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
DFE16 : Digital Filter Enable
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero.
#1 : 1
Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
DFE17 : Digital Filter Enable
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero.
#1 : 1
Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
DFE18 : Digital Filter Enable
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero.
#1 : 1
Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
DFE19 : Digital Filter Enable
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero.
#1 : 1
Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
DFE20 : Digital Filter Enable
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero.
#1 : 1
Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
DFE21 : Digital Filter Enable
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero.
#1 : 1
Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
DFE22 : Digital Filter Enable
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero.
#1 : 1
Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
DFE23 : Digital Filter Enable
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero.
#1 : 1
Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
DFE24 : Digital Filter Enable
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero.
#1 : 1
Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
DFE25 : Digital Filter Enable
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero.
#1 : 1
Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
DFE26 : Digital Filter Enable
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero.
#1 : 1
Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
DFE27 : Digital Filter Enable
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero.
#1 : 1
Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
DFE28 : Digital Filter Enable
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero.
#1 : 1
Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
DFE29 : Digital Filter Enable
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero.
#1 : 1
Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
DFE30 : Digital Filter Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero.
#1 : 1
Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
DFE31 : Digital Filter Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero.
#1 : 1
Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
Digital Filter Clock Register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CS : Clock Source
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Digital filters are clocked by the bus clock.
#1 : 1
Digital filters are clocked by the LPO clock.
End of enumeration elements list.
Digital Filter Width Register
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FILT : Filter Length
bits : 0 - 4 (5 bit)
access : read-write
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