Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x10D0 byte (0x0)
mem_usage : registers
protection : not protected
System Options Register 1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRAMSIZE : Returns the size of the system RAM
bits : 12 - 15 (4 bit)
access : read-only
Enumeration:
#0110 : 110
32 KB System RAM
#0111 : 111
64 KB System RAM
End of enumeration elements list.
OSC32KSEL : 32K oscillator clock select
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
#00 : 00
OSC32KCLK (RTC Oscillator output)
#01 : 01
ERCLK32K
#10 : 10
MCGIRCLK
#11 : 11
LPO
End of enumeration elements list.
System Control Register
address_offset : 0x1004 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NMIDIS : NMI Disable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
NMI enabled
#1 : 1
NMI disabled
End of enumeration elements list.
PLLVLPEN : PLL VLP Enable
bits : 1 - 1 (1 bit)
access : read-write
ADCTRGSEL : SAR ADC Trigger Clock Select
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
#00 : 00
Bus ClockDuring Low Power Modes such as stop, the Bus clock is not available for conversion and should not be selected in case a conversion needs to be performed while in stop.
#01 : 01
ADC asynchronous Clock
#10 : 10
ERCLK32K
#11 : 11
OSCCLK
End of enumeration elements list.
CLKOUT : Clock out Select
bits : 5 - 7 (3 bit)
access : read-write
Enumeration:
#000 : 000
Disabled
#001 : 001
Gated Core Clk
#010 : 010
Bus Clk
#011 : 011
LPO clock from PMC
#100 : 100
IRC clock from MCG
#101 : 101
Muxed 32Khz source (please refer to SOPT1[19:18] for possible options)
#110 : 110
MHz Oscillator external reference clock
#111 : 111
PLL clock output from MCG
End of enumeration elements list.
SPI0_INV0 : This bit inverts the SPI0 signal output.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
not inverted
#1 : 1
inverts SS
End of enumeration elements list.
SPI0_INV1 : This bit inverts the SPI0 signal output.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
not inverted
#1 : 1
inverts SCK
End of enumeration elements list.
SPI0_INV2 : This bit inverts the SPI0 signal output.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
not inverted
#1 : 1
inverts MOSI
End of enumeration elements list.
SPI0_INV3 : This bit inverts the SPI0 signal output.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
not inverted
#1 : 1
inverts MISO
End of enumeration elements list.
SPI1_INV0 : This bit inverts the SPI1 signal output.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
not inverted
#1 : 1
inverts SS
End of enumeration elements list.
SPI1_INV1 : This bit inverts the SPI1 signal output.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
not inverted
#1 : 1
inverts SCK
End of enumeration elements list.
SPI1_INV2 : This bit inverts the SPI1 signal output.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
not inverted
#1 : 1
inverts MOSI
End of enumeration elements list.
SPI1_INV3 : This bit inverts the SPI1 signal output.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
not inverted
#1 : 1
inverts MISO
End of enumeration elements list.
PLLFLLSEL : PLL/FLL selection
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#00 : 00
MCGFLLCLK
#01 : 01
MCGPLLCLK
#10 : 10
BUSCLK
#11 : 11
OSC32KCLK (RTC Oscillator output)
End of enumeration elements list.
SPI2_INV0 : This bit inverts the SPI2 signal output.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
not inverted
#1 : 1
inverts SS
End of enumeration elements list.
SPI2_INV1 : This bit inverts the SPI2 signal output.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
not inverted
#1 : 1
inverts SCK
End of enumeration elements list.
SPI2_INV2 : This bit inverts the SPI2 signal output.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
not inverted
#1 : 1
inverts MOSI
End of enumeration elements list.
XBARCLKOUT : XBAR clock out selection
bits : 21 - 23 (3 bit)
access : read-write
Enumeration:
#000 : 000
Disabled
#001 : 001
Gated Core Clk
#010 : 010
Bus Clk
#011 : 011
LPO clock from PMC
#100 : 100
IRC clock from MCG
#101 : 101
MUXed 32 kHz source (please refer to SOPT1[19:18] for possible options)
#110 : 110
MHz Oscillator external reference clock
#111 : 111
PLL clock output from MCG
End of enumeration elements list.
AFEOUTCLKSEL : AFE clock output select
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
AFE output clock is divided by AFE clock prescaler.
#1 : 1
AFE output clock is NOT divided by AFE clock prescaler.
End of enumeration elements list.
SPI2_INV3 : This bit inverts the SPI2 signal output.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
not inverted
#1 : 1
inverts MISO
End of enumeration elements list.
LPUARTSRC : LPUART clock Source configuration
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
#00 : 00
Clock disabled
#01 : 01
MCGPLLCLK/MCGFLLCLK
#10 : 10
OSCERCLK
#11 : 11
MCGIRCLK
End of enumeration elements list.
RTC_OSC32K_COUNT4_INIT_CLR : RTC_OSC32K_COUNT4_INIT_CLR
bits : 28 - 28 (1 bit)
access : read-write
PDBCLKSRC : PDB Clock Source configuration
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
BUSCLK is used as PDB clock.
#1 : 1
MCGPLLCLK is used as PDB clock.
End of enumeration elements list.
TMRFREEZE : QTMR counters Freeze control
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
QTMR counters operate normally.
#1 : 1
QTMR counters and OFLAGs are reset. Clearing this bit will resume QTMR operation.
End of enumeration elements list.
System Device Identification Register
address_offset : 0x1024 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PINID : Pincount identification
bits : 0 - 3 (4 bit)
access : read-only
Enumeration:
#1000 : 1000
100-pin
#1010 : 1010
144-pin
End of enumeration elements list.
DIEID : Die ID
bits : 4 - 7 (4 bit)
access : read-only
Enumeration:
#0000 : 0
First cut
End of enumeration elements list.
REVID : Revision ID
bits : 8 - 11 (4 bit)
access : read-only
Enumeration:
#0000 : 0
First cut
End of enumeration elements list.
SRAMSIZE : SRAM Size
bits : 12 - 15 (4 bit)
access : read-only
Enumeration:
#0110 : 110
32 KB SRAM
#0111 : 111
64 KB SRAM
End of enumeration elements list.
ATTR : Attribute ID
bits : 16 - 19 (4 bit)
access : read-only
Enumeration:
#0000 : 0
M0+ core
End of enumeration elements list.
SERIESID : Series ID
bits : 20 - 23 (4 bit)
access : read-only
Enumeration:
#0011 : 11
Metering Series
End of enumeration elements list.
SUBFAMID : Sub-Family ID
bits : 24 - 27 (4 bit)
access : read-only
Enumeration:
#0000 : 000
Device derivatives with NO AFE enabled
#0001 : 001
Device derivatives with 1 AFE enabled
#0010 : 010
Device derivatives with 2 AFE enabled
#0011 : 011
Device derivatives with 3 AFE enabled
#0100 : 100
Device derivatives with 4 AFE enabled
End of enumeration elements list.
FAMID : Metering family ID
bits : 28 - 31 (4 bit)
access : read-only
Enumeration:
#0001 : 01
Device derivatives without LCD
#0011 : 11
Device derivatives with LCD
End of enumeration elements list.
System Clock Gating Control Register 4
address_offset : 0x1034 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EWM : External Watchdog Monitor Clock gate control
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
I2C0 : I2C0 Clock Gate Control
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
I2C1 : I2C1 Clock Gate Control
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
UART0 : UART0 Clock Gate Control
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
UART1 : UART1 Clock Gate Control
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
UART2 : UART2 Clock Gate Control
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
UART3 : UART3 Clock Gate Control
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
VREF : VREF Clock Gate Control
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
CMP : High Speed Comparator Clock Gate Control.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
SPI0 : SPI0 Clock Gate Control
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
SPI1 : SPI1 Clock Gate Control
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
SPI2 : SPI2 Clock Gate Control
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
System Clock Gating Control Register 5
address_offset : 0x1038 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLCD : Segmented LCD Clock Gate Control
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
PORTA : PCTLA Clock Gate Control
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
PORTB : PCTLB Clock Gate Control
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
PORTC : PCTLC Clock Gate Control
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
PORTD : PCTLD Clock Gate Control
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
PORTE : PCTLE Clock Gate Control
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
PORTF : PCTLF Clock Gate Control
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
PORTG : PCTLG Clock Gate Control
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
PORTH : PCTLH Clock Gate Control
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
PORTI : PCTLI Clock Gate Control
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
RTC : iRTC Clock Gate Control
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
RTCREG : iRTC_REG_FILE Clock Gate Control
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
XBAR : Peripheral Crossbar Clock Gate Control
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
TMR0 : QaudTimer channel 0 Clock Gate Control
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
TMR1 : QaudTimer channel 1 Clock Gate Control
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
TMR2 : QaudTimer channel 2 Clock Gate Control
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
TMR3 : QaudTimer channel 3 Clock Gate Control
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
System Clock Gating Control Register 6
address_offset : 0x103C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FTFA : FTFA Clock Gate Control
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
DMACHMUX : DMA Channel MUX Clock Gate Control
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
RNGA : RNGA Clock Gate Control
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
LPUART : LPUART Clock Gate Control
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
ADC : SAR ADC Clock Gate Control
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
PIT0 : PIT0 Clock Gate Control
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
PIT1 : PIT1 Clock Gate Control
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
AFE : AFE Clock Gate Control
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
CRC : Programmable CRC Clock Gate Control
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
PDB : PDB Clock Gate Control
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
PORTJ : PCTLJ Clock Gate Control
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
PORTK : PCTLK Clock Gate Control
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
PORTL : PCTLL Clock Gate Control
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
PORTM : PCTLM Clock Gate Control
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
LPTMR0 : LPTMR Clock Gate Control
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
LPTMR1 : LPTMR Clock Gate Control
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
System Clock Gating Control Register 7
address_offset : 0x1040 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPU : MPU Clock Gate control.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
DMA : DMA Clock Gate control.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
CAU : CAU Clock Gate control.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
System Clock Divider Register 1
address_offset : 0x1044 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLASHCLKMODE : Flash Clock Mode
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Flash Clock is the same as BUS clock.
#1 : 1
Flash Clock is a half of BUS clock.
End of enumeration elements list.
CLKDIVBUS : Bus Clock divider
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
SYSCLK:BUSCLK = 1:1
#01 : 01
SYSCLK:BUSCLK = 2:1
#10 : 10
SYSCLK:BUSCLK = 3:1
#11 : 11
SYSCLK:BUSCLK = 4:1
End of enumeration elements list.
CLKDIVSYS : System Clock divider
bits : 28 - 31 (4 bit)
access : read-write
Enumeration:
#0000 : 00
Divide by 1
#0001 : 01
Divide by 2
#0010 : 10
Divide by 3
#0011 : 11
Divide by 4 and so on... If FOPT[0] is 0, the divider is set to div-by-8 after system reset is deasserted (after completion of system initialization sequence).
End of enumeration elements list.
Flash Configuration Register 1
address_offset : 0x104C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLASHDIS : Flash Disable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Flash is enabled
#1 : 1
Flash is disabled
End of enumeration elements list.
FLASHDOZE : Flash Doze
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Flash remains enabled during Wait mode
#1 : 1
Flash is disabled for the duration of Wait mode
End of enumeration elements list.
PFSIZE : Program flash size
bits : 24 - 27 (4 bit)
access : read-only
Enumeration:
#1001 : 1001
256 KB of program flash memory
#1011 : 1011
512 KB of program flash memory
#1111 : 1111
(Default)
End of enumeration elements list.
Flash Configuration Register 2
address_offset : 0x1050 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MAXADDR1 : Max address
bits : 16 - 22 (7 bit)
access : read-only
PLASH : Program Flash only
bits : 23 - 23 (1 bit)
access : read-only
MAXADDR0 : Max address
bits : 24 - 30 (7 bit)
access : read-only
Unique Identification Register High
address_offset : 0x1054 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
UID127_96 : Unique Identification UID[127:96]
bits : 0 - 31 (32 bit)
access : read-only
Unique Identification Register Mid-High
address_offset : 0x1058 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
UID95_64 : Unique Identification UID[95:64]
bits : 0 - 31 (32 bit)
access : read-only
Unique Identification Register Mid-Low
address_offset : 0x105C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
UID63_32 : Unique Identification UID[63:32]
bits : 0 - 31 (32 bit)
access : read-only
Unique Identification Register Low
address_offset : 0x1060 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
UID31_0 : Unique Identification UID[31:0]
bits : 0 - 31 (32 bit)
access : read-only
Miscellaneous Control Register
address_offset : 0x106C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OSCON : RTC oscillator status
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
RTC oscillator is disabled.
#1 : 1
RTC oscillator is enabled.
End of enumeration elements list.
PDBADCTRG : PDB bypass XBAR as ADC trigger
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
XBAR to trigger ADC
#1 : 1
PDB output to trigger ADC
End of enumeration elements list.
DMADONESEL : DMA Done select
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 00
DMA0
#01 : 01
DMA1
#10 : 10
DMA2
#11 : 11
DMA3
End of enumeration elements list.
AFECLKSEL : AFE Clock Source Select (SIMAFECLK selection)
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 00
MCG PLL Clock selected
#01 : 01
MCG FLL Clock selected
#10 : 10
OSC Clock selected
#11 : 11
Disabled
End of enumeration elements list.
AFECLKPADDIR : AFE Clock Pad Direction
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
AFE CLK PAD is input
#1 : 1
AFE CLK PAD is output
End of enumeration elements list.
UARTMODTYPE : UART Modulation Type
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
TypeA (OR'ed) Modulation selected for IrDA
#1 : 1
TypeB (AND'ed) Modulation selected for IrDA
End of enumeration elements list.
UART0IRSEL : UART0 IrDA Select
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pad RX input (PTD[0], PTF[3] or PTK[3], as selected in Pinmux control) selected for RX input of UART0 and UART0 TX signal is not used for modulation
#1 : 1
UART0 selected for IrDA modulation. UART0 TX modulated by XBAR_OUT[14] and UART0 RX input connected to XBAR_OUT[13]. UARTxIRSEL cannot configure XBAR_OUT[14] and XBAR_OUT[13] automatically, and they need extra configuration in XBAR. User should configure XBAR[14:13] accordingly.
End of enumeration elements list.
UART1IRSEL : UART1 IrDA Select
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pad RX input (PTD[2], PTI[0] or PTK[5], as selected in Pinmux control) selected for RX input of UART1 and UART1 TX signal is not used for modulation
#1 : 1
UART1 selected for IrDA modulation. UART1 TX modulated by XBAR_OUT[14] and UART1 RX input connected to XBAR_OUT[13].UARTxIRSEL cannot configure XBAR_OUT[14] and XBAR_OUT[13] automatically, and they need extra configuration in XBAR. User should configure XBAR[14:13] accordingly.
End of enumeration elements list.
UART2IRSEL : UART2 IrDA Select
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pad RX input PTI[6] or PTE[6] selected for RX input of UART2 and UART2 TX signal is not used for modulation
#1 : 1
UART2 selected for IrDA modulation. UART2 TX modulated by XBAR_OUT[14] and UART2 RX input connected to XBAR_OUT[13].UARTxIRSEL cannot configure XBAR_OUT[14] and XBAR_OUT[13] automatically, and they need extra configuration in XBAR. User should configure XBAR[14:13] accordingly.
End of enumeration elements list.
UART3IRSEL : UART3 IrDA Select
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pad RX input (PTC[3] or PTD[7], as selected in Pinmux control) selected for RX input of UART3 and UART3 TX signal is not used for modulation
#1 : 1
UART3 selected for IrDA modulation. UART3 TX modulated by XBAR_OUT[14] and UART3 RX input connected to XBAR_OUT[13]. UARTxIRSEL cannot configure XBAR_OUT[14] and XBAR_OUT[13] automatically, and they need extra configuration in XBAR. User should configure XBAR[14:13] accordingly.
End of enumeration elements list.
RTC_OSC32K_INIT : RTC OSC32K clock count to 4096 done status
bits : 12 - 12 (1 bit)
access : read-only
RTC_OSC32K_COUNT4_INIT : RTC OSC32K clock count to 4 done status
bits : 13 - 13 (1 bit)
access : read-only
EWMINSEL : External Watchdog Monitor Input Select
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Input from PAD (PTL[3], PTE[2] or PTE[3] as selected from Pinmux control )
#1 : 1
Peripheral Crossbar (XBAR) Output[32]
End of enumeration elements list.
TMR0PLLSEL : Timer CH0 PLL clock Select
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Selects Bus Clock as source for the Timer CH0
#1 : 1
Selects the PLL_AFE clock as the source for Timer CH0. The PLL_AFE clock source is itself selected using the MISC_CTL[5:4]
End of enumeration elements list.
TMR0SCSEL : Quadtimer Channel0 Secondary Count source Select
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pad PTF1 or PTD5, depending upon PCTL configuration.
#1 : 1
Peripheral Crossbar (XBAR) Output[5]
End of enumeration elements list.
TMR1SCSEL : Quadtimer Channel1 Secondary Count source Select
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pad PTG0 or PTC6, depending upon PCTL configuration.
#1 : 1
Peripheral Crossbar (XBAR) Output[6]
End of enumeration elements list.
TMR2SCSEL : Quadtimer Channel2 Secondary Count source Select
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pad PTF7 or PTF0, depending upon PCTL configuration.
#1 : 1
Peripheral Crossbar (XBAR) Output[7]
End of enumeration elements list.
TMR3SCSEL : Quadtimer Channel3 Secondary Count source Select
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pad PTE5 or PTD1, depending upon PCTL configuration.
#1 : 1
Peripheral Crossbar (XBAR) Output[8]
End of enumeration elements list.
TMR0PCSSEL : Quadtimer Channel0 Primary Count Source Select
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
#00 : 00
Bus Clock
#01 : 01
Peripheral Crossbar Output [9]
#10 : 10
Peripheral Crossbar Output [10]
#11 : 11
Disabled
End of enumeration elements list.
TMR1PCSSEL : Quadtimer Channel1 Primary Count Source Select
bits : 22 - 23 (2 bit)
access : read-write
Enumeration:
#00 : 00
Bus Clock
#01 : 01
Peripheral Crossbar Output [9]
#10 : 10
Peripheral Crossbar Output [10]
#11 : 11
Disabled
End of enumeration elements list.
TMR2PCSSEL : Quadtimer Channel2 Primary Count Source Select
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
Bus Clock
#01 : 01
Peripheral Crossbar Output [9]
#10 : 10
Peripheral Crossbar Output [10]
#11 : 11
Disabled
End of enumeration elements list.
TMR3PCSSEL : Quadtimer Channel3 Primary Count Source Select
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
#00 : 00
Bus Clock
#01 : 01
Peripheral Crossbar Output [9]
#10 : 10
Peripheral Crossbar Output [10]
#11 : 11
Disabled
End of enumeration elements list.
RTCCLKSEL : RTC Clock select
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
RTC OSC_32K clock selected
#1 : 1
MCGIRCLK selected
End of enumeration elements list.
VREFBUFOUTEN : VrefBuffer Output Enable
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Buffer does not drive PAD
#1 : 1
Buffer drives selected voltage (selected by vref_buffer_sel) on pad
End of enumeration elements list.
VREFBUFINSEL : VrefBuffer Input Select
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal Reference selected as Buffer Input
#1 : 1
External Reference selected as Buffer Input
End of enumeration elements list.
VREFBUFPD : VrefBuffer Power Down
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Buffer Enabled
#1 : 1
Buffer Powered Down
End of enumeration elements list.
ADC Compensation Register 0
address_offset : 0x10C8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADCCOMPVAL0 : ADC Temperature Compensation Value 0
bits : 0 - 15 (16 bit)
access : read-only
ADCCOMPVAL1 : ADC Temperature Compensation Value 1
bits : 16 - 31 (16 bit)
access : read-only
ADC Compensation Register 1
address_offset : 0x10CC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADCCOMPVAL2 : ADC Temperature Compensation Value 2
bits : 0 - 15 (16 bit)
access : read-only
SOPT1 Configuration Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPTMRSEL0 : LP Timer Channel0 Select
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
CMP[0] output
#01 : 01
CMP[1] output
#10 : 10
CMP[2] output
End of enumeration elements list.
LPTMRSEL1 : LP Timer Channel1 Select
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 00
Pad PTE4
#01 : 01
Pad PTF4
#10 : 10
Pad PTG1
End of enumeration elements list.
LPTMRSEL2 : LP Timer Channel2 Select
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 00
Pad PTD6
#01 : 01
Pad PTF3
#10 : 10
Pad PTG5
End of enumeration elements list.
LPTMRSEL3 : LP Timer Channel Select3
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 00
Pad PTD5
#01 : 01
Pad PTG0
#10 : 10
Pad PTG6
End of enumeration elements list.
RAMSBDIS : Disable source bias of System SRAM arrays during VLPR and VLPW modes.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Source bias of System SRAM enabled during VLPR and VLPW modes.
#1 : 1
Source bias of System SRAM disabled during VLPR and VLPW modes.
End of enumeration elements list.
RAMBPEN : RAM Bitline Precharge Enable
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bitline precharge of system SRAM disabled during VLPR and VLPW modes.
#1 : 1
Bitline precharge of system SRAM enabled during VLPR and VLPW modes.
End of enumeration elements list.
LPTMR1SEL0 : LP Timer1 Channel0 Select
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#00 : 00
CMP[0] output
#01 : 01
CMP[1] output
#10 : 10
CMP[2] output
End of enumeration elements list.
LPTMR1SEL1 : LP Timer1 Channel1 Select1
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
#00 : 00
PAD PTC5
#01 : 01
PAD PTG7
#10 : 10
PAD PTJ4
End of enumeration elements list.
LPTMR1SEL2 : LP Timer1 Channel2 Select
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
#00 : 00
Pad PTD3
#01 : 01
Pad PTH4
#10 : 10
Pad PTJ7
End of enumeration elements list.
LPTMR1SEL3 : LP Timer1 Channel3 Select
bits : 22 - 23 (2 bit)
access : read-write
Enumeration:
#00 : 00
Pad PTD4
#01 : 01
Pad PTH5
#10 : 10
Pad PTK0
End of enumeration elements list.
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