Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : registers
protection : not protected
LPUART Baud Rate Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SBR : Baud Rate Modulo Divisor.
bits : 0 - 12 (13 bit)
access : read-write
SBNS : Stop Bit Number Select
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
One stop bit.
#1 : 1
Two stop bits.
End of enumeration elements list.
RXEDGIE : RX Input Active Edge Interrupt Enable
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Hardware interrupts from LPUART_STAT[RXEDGIF] disabled (use polling).
#1 : 1
Hardware interrupt requested when LPUART_STAT[RXEDGIF] flag is 1.
End of enumeration elements list.
LBKDIE : LIN Break Detect Interrupt Enable
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Hardware interrupts from LPUART_STAT[LBKDIF] disabled (use polling).
#1 : 1
Hardware interrupt requested when LPUART_STAT[LBKDIF] flag is 1.
End of enumeration elements list.
RESYNCDIS : Resynchronization Disable
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Resynchronization during received data word is supported
#1 : 1
Resynchronization during received data word is disabled
End of enumeration elements list.
BOTHEDGE : Both Edge Sampling
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receiver samples input data using the rising edge of the baud rate clock.
#1 : 1
Receiver samples input data using the rising and falling edge of the baud rate clock.
End of enumeration elements list.
MATCFG : Match Configuration
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
#00 : 00
Address Match Wakeup
#01 : 01
Idle Match Wakeup
#10 : 10
Match On and Match Off
#11 : 11
Enables RWU on Data Match and Match On/Off for transmitter CTS input
End of enumeration elements list.
RDMAE : Receiver Full DMA Enable
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA request disabled.
#1 : 1
DMA request enabled.
End of enumeration elements list.
TDMAE : Transmitter DMA Enable
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA request disabled.
#1 : 1
DMA request enabled.
End of enumeration elements list.
OSR : Oversampling Ratio
bits : 24 - 28 (5 bit)
access : read-write
M10 : 10-bit Mode select
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receiver and transmitter use 8-bit or 9-bit data characters.
#1 : 1
Receiver and transmitter use 10-bit data characters.
End of enumeration elements list.
MAEN2 : Match Address Mode Enable 2
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation.
#1 : 1
Enables automatic address matching or data matching mode for MATCH[MA2].
End of enumeration elements list.
MAEN1 : Match Address Mode Enable 1
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation.
#1 : 1
Enables automatic address matching or data matching mode for MATCH[MA1].
End of enumeration elements list.
LPUART Match Address Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MA1 : Match Address 1
bits : 0 - 9 (10 bit)
access : read-write
MA2 : Match Address 2
bits : 16 - 25 (10 bit)
access : read-write
LPUART Modem IrDA Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXCTSE : Transmitter clear-to-send enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
CTS has no effect on the transmitter.
#1 : 1
Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission.
End of enumeration elements list.
TXRTSE : Transmitter request-to-send enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The transmitter has no effect on RTS.
#1 : 1
When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit.
End of enumeration elements list.
TXRTSPOL : Transmitter request-to-send polarity
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transmitter RTS is active low.
#1 : 1
Transmitter RTS is active high.
End of enumeration elements list.
RXRTSE : Receiver request-to-send enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The receiver has no effect on RTS.
#1 : 1
RTS assertion is configured by the RTSWATER field
End of enumeration elements list.
TXCTSC : Transmit CTS Configuration
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
CTS input is sampled at the start of each character.
#1 : 1
CTS input is sampled when the transmitter is idle.
End of enumeration elements list.
TXCTSSRC : Transmit CTS Source
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
CTS input is the LPUART_CTS pin.
#1 : 1
CTS input is the inverted Receiver Match result.
End of enumeration elements list.
RTSWATER : Receive RTS Configuration
bits : 8 - 15 (8 bit)
access : read-write
Enumeration:
#0 : 0
RTS asserts when the receiver FIFO is full or receiving a character that causes the FIFO to become full.
#1 : 1
RTS asserts when the receive FIFO is less than or equal to the RXWATER configuration and negates when the receive FIFO is greater than the RXWATER configuration.
End of enumeration elements list.
TNP : Transmitter narrow pulse
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#00 : 00
1/OSR.
#01 : 01
2/OSR.
#10 : 10
3/OSR.
#11 : 11
4/OSR.
End of enumeration elements list.
IREN : Infrared enable
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
IR disabled.
#1 : 1
IR enabled.
End of enumeration elements list.
LPUART FIFO Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXFIFOSIZE : Receive FIFO. Buffer Depth
bits : 0 - 2 (3 bit)
access : read-only
Enumeration:
#010 : 010
Receive FIFO/Buffer depth = 4 datawords.
End of enumeration elements list.
RXFE : Receive FIFO Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receive FIFO is not enabled. Buffer is depth 1. (Legacy support)
#1 : 1
Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE.
End of enumeration elements list.
TXFIFOSIZE : Transmit FIFO. Buffer Depth
bits : 4 - 6 (3 bit)
access : read-only
Enumeration:
#010 : 010
Transmit FIFO/Buffer depth = 4 datawords.
End of enumeration elements list.
TXFE : Transmit FIFO Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support).
#1 : 1
Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE.
End of enumeration elements list.
RXUFE : Receive FIFO Underflow Interrupt Enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
RXUF flag does not generate an interrupt to the host.
#1 : 1
RXUF flag generates an interrupt to the host.
End of enumeration elements list.
TXOFE : Transmit FIFO Overflow Interrupt Enable
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
TXOF flag does not generate an interrupt to the host.
#1 : 1
TXOF flag generates an interrupt to the host.
End of enumeration elements list.
RXIDEN : Receiver Idle Empty Enable
bits : 10 - 12 (3 bit)
access : read-write
Enumeration:
#000 : 000
Disable RDRF assertion due to partially filled FIFO when receiver is idle.
#001 : 001
Enable RDRF assertion due to partially filled FIFO when receiver is idle for 1 character.
#010 : 010
Enable RDRF assertion due to partially filled FIFO when receiver is idle for 2 characters.
#011 : 011
Enable RDRF assertion due to partially filled FIFO when receiver is idle for 4 characters.
#100 : 100
Enable RDRF assertion due to partially filled FIFO when receiver is idle for 8 characters.
#101 : 101
Enable RDRF assertion due to partially filled FIFO when receiver is idle for 16 characters.
#110 : 110
Enable RDRF assertion due to partially filled FIFO when receiver is idle for 32 characters.
#111 : 111
Enable RDRF assertion due to partially filled FIFO when receiver is idle for 64 characters.
End of enumeration elements list.
RXFLUSH : Receive FIFO/Buffer Flush
bits : 14 - 14 (1 bit)
access : write-only
Enumeration:
#0 : 0
No flush operation occurs.
#1 : 1
All data in the receive FIFO/buffer is cleared out.
End of enumeration elements list.
TXFLUSH : Transmit FIFO/Buffer Flush
bits : 15 - 15 (1 bit)
access : write-only
Enumeration:
#0 : 0
No flush operation occurs.
#1 : 1
All data in the transmit FIFO/Buffer is cleared out.
End of enumeration elements list.
RXUF : Receiver Buffer Underflow Flag
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
No receive buffer underflow has occurred since the last time the flag was cleared.
#1 : 1
At least one receive buffer underflow has occurred since the last time the flag was cleared.
End of enumeration elements list.
TXOF : Transmitter Buffer Overflow Flag
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
No transmit buffer overflow has occurred since the last time the flag was cleared.
#1 : 1
At least one transmit buffer overflow has occurred since the last time the flag was cleared.
End of enumeration elements list.
RXEMPT : Receive Buffer/FIFO Empty
bits : 22 - 22 (1 bit)
access : read-only
Enumeration:
#0 : 0
Receive buffer is not empty.
#1 : 1
Receive buffer is empty.
End of enumeration elements list.
TXEMPT : Transmit Buffer/FIFO Empty
bits : 23 - 23 (1 bit)
access : read-only
Enumeration:
#0 : 0
Transmit buffer is not empty.
#1 : 1
Transmit buffer is empty.
End of enumeration elements list.
LPUART Watermark Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXWATER : Transmit Watermark
bits : 0 - 7 (8 bit)
access : read-write
TXCOUNT : Transmit Counter
bits : 8 - 15 (8 bit)
access : read-only
RXWATER : Receive Watermark
bits : 16 - 23 (8 bit)
access : read-write
RXCOUNT : Receive Counter
bits : 24 - 31 (8 bit)
access : read-only
LPUART Status Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MA2F : Match 2 Flag
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Received data is not equal to MA2
#1 : 1
Received data is equal to MA2
End of enumeration elements list.
MA1F : Match 1 Flag
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Received data is not equal to MA1
#1 : 1
Received data is equal to MA1
End of enumeration elements list.
PF : Parity Error Flag
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
No parity error.
#1 : 1
Parity error.
End of enumeration elements list.
FE : Framing Error Flag
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
No framing error detected. This does not guarantee the framing is correct.
#1 : 1
Framing error.
End of enumeration elements list.
NF : Noise Flag
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
No noise detected.
#1 : 1
Noise detected in the received character in LPUART_DATA.
End of enumeration elements list.
OR : Receiver Overrun Flag
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
No overrun.
#1 : 1
Receive overrun (new LPUART data lost).
End of enumeration elements list.
IDLE : Idle Line Flag
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
No idle line detected.
#1 : 1
Idle line was detected.
End of enumeration elements list.
RDRF : Receive Data Register Full Flag
bits : 21 - 21 (1 bit)
access : read-only
Enumeration:
#0 : 0
Receive data buffer empty.
#1 : 1
Receive data buffer full.
End of enumeration elements list.
TC : Transmission Complete Flag
bits : 22 - 22 (1 bit)
access : read-only
Enumeration:
#0 : 0
Transmitter active (sending data, a preamble, or a break).
#1 : 1
Transmitter idle (transmission activity complete).
End of enumeration elements list.
TDRE : Transmit Data Register Empty Flag
bits : 23 - 23 (1 bit)
access : read-only
Enumeration:
#0 : 0
Transmit data buffer full.
#1 : 1
Transmit data buffer empty.
End of enumeration elements list.
RAF : Receiver Active Flag
bits : 24 - 24 (1 bit)
access : read-only
Enumeration:
#0 : 0
LPUART receiver idle waiting for a start bit.
#1 : 1
LPUART receiver active (LPUART_RX input not idle).
End of enumeration elements list.
LBKDE : LIN Break Detection Enable
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Break character is detected at length 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1).
#1 : 1
Break character is detected at length of 11 bit times (if M = 0, SBNS = 0) or 12 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 14 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 15 (if M10 = 1, SNBS = 1).
End of enumeration elements list.
BRK13 : Break Character Generation Length
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Break character is transmitted with length of 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1).
#1 : 1
Break character is transmitted with length of 13 bit times (if M = 0, SBNS = 0) or 14 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 15 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 16 (if M10 = 1, SNBS = 1).
End of enumeration elements list.
RWUID : Receive Wake Up Idle Detect
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character. During address match wakeup, the IDLE bit does not get set when an address does not match.
#1 : 1
During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. During address match wakeup, the IDLE bit does get set when an address does not match.
End of enumeration elements list.
RXINV : Receive Data Inversion
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receive data not inverted.
#1 : 1
Receive data inverted.
End of enumeration elements list.
MSBF : MSB First
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0.
#1 : 1
MSB (bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on the setting of CTRL[M], CTRL[PE] and BAUD[M10]. Further, the first bit received after the start bit is identified as bit9, bit8, bit7 or bit6 depending on the setting of CTRL[M] and CTRL[PE].
End of enumeration elements list.
RXEDGIF : LPUART_RX Pin Active Edge Interrupt Flag
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
No active edge on the receive pin has occurred.
#1 : 1
An active edge on the receive pin has occurred.
End of enumeration elements list.
LBKDIF : LIN Break Detect Interrupt Flag
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
No LIN break character has been detected.
#1 : 1
LIN break character has been detected.
End of enumeration elements list.
LPUART Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PT : Parity Type
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Even parity.
#1 : 1
Odd parity.
End of enumeration elements list.
PE : Parity Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No hardware parity generation or checking.
#1 : 1
Parity enabled.
End of enumeration elements list.
ILT : Idle Line Type Select
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Idle character bit count starts after start bit.
#1 : 1
Idle character bit count starts after stop bit.
End of enumeration elements list.
WAKE : Receiver Wakeup Method Select
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configures RWU for idle-line wakeup.
#1 : 1
Configures RWU with address-mark wakeup.
End of enumeration elements list.
M : 9-Bit or 8-Bit Mode Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receiver and transmitter use 8-bit data characters.
#1 : 1
Receiver and transmitter use 9-bit data characters.
End of enumeration elements list.
RSRC : Receiver Source Select
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the LPUART does not use the LPUART_RX pin.
#1 : 1
Single-wire LPUART mode where the LPUART_TX pin is connected to the transmitter output and receiver input.
End of enumeration elements list.
DOZEEN : Doze Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
LPUART is enabled in Doze mode.
#1 : 1
LPUART is disabled in Doze mode.
End of enumeration elements list.
LOOPS : Loop Mode Select
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation - LPUART_RX and LPUART_TX use separate pins.
#1 : 1
Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input (see RSRC bit).
End of enumeration elements list.
IDLECFG : Idle Configuration
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
1 idle character
#001 : 001
2 idle characters
#010 : 010
4 idle characters
#011 : 011
8 idle characters
#100 : 100
16 idle characters
#101 : 101
32 idle characters
#110 : 110
64 idle characters
#111 : 111
128 idle characters
End of enumeration elements list.
MA2IE : Match 2 Interrupt Enable
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
MA2F interrupt disabled
#1 : 1
MA2F interrupt enabled
End of enumeration elements list.
MA1IE : Match 1 Interrupt Enable
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
MA1F interrupt disabled
#1 : 1
MA1F interrupt enabled
End of enumeration elements list.
SBK : Send Break
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal transmitter operation.
#1 : 1
Queue break character(s) to be sent.
End of enumeration elements list.
RWU : Receiver Wakeup Control
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal receiver operation.
#1 : 1
LPUART receiver in standby waiting for wakeup condition.
End of enumeration elements list.
RE : Receiver Enable
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receiver disabled.
#1 : 1
Receiver enabled.
End of enumeration elements list.
TE : Transmitter Enable
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transmitter disabled.
#1 : 1
Transmitter enabled.
End of enumeration elements list.
ILIE : Idle Line Interrupt Enable
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Hardware interrupts from IDLE disabled; use polling.
#1 : 1
Hardware interrupt requested when IDLE flag is 1.
End of enumeration elements list.
RIE : Receiver Interrupt Enable
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Hardware interrupts from RDRF disabled; use polling.
#1 : 1
Hardware interrupt requested when RDRF flag is 1.
End of enumeration elements list.
TCIE : Transmission Complete Interrupt Enable for
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Hardware interrupts from TC disabled; use polling.
#1 : 1
Hardware interrupt requested when TC flag is 1.
End of enumeration elements list.
TIE : Transmit Interrupt Enable
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Hardware interrupts from TDRE disabled; use polling.
#1 : 1
Hardware interrupt requested when TDRE flag is 1.
End of enumeration elements list.
PEIE : Parity Error Interrupt Enable
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
PF interrupts disabled; use polling).
#1 : 1
Hardware interrupt requested when PF is set.
End of enumeration elements list.
FEIE : Framing Error Interrupt Enable
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
FE interrupts disabled; use polling.
#1 : 1
Hardware interrupt requested when FE is set.
End of enumeration elements list.
NEIE : Noise Error Interrupt Enable
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
NF interrupts disabled; use polling.
#1 : 1
Hardware interrupt requested when NF is set.
End of enumeration elements list.
ORIE : Overrun Interrupt Enable
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
OR interrupts disabled; use polling.
#1 : 1
Hardware interrupt requested when OR is set.
End of enumeration elements list.
TXINV : Transmit Data Inversion
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transmit data not inverted.
#1 : 1
Transmit data inverted.
End of enumeration elements list.
TXDIR : LPUART_TX Pin Direction in Single-Wire Mode
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
LPUART_TX pin is an input in single-wire mode.
#1 : 1
LPUART_TX pin is an output in single-wire mode.
End of enumeration elements list.
R9T8 : Receive Bit 9 / Transmit Bit 8
bits : 30 - 30 (1 bit)
access : read-write
R8T9 : Receive Bit 8 / Transmit Bit 9
bits : 31 - 31 (1 bit)
access : read-write
LPUART Data Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
R0T0 : Read receive data buffer 0 or write transmit data buffer 0.
bits : 0 - 0 (1 bit)
access : read-write
R1T1 : Read receive data buffer 1 or write transmit data buffer 1.
bits : 1 - 1 (1 bit)
access : read-write
R2T2 : Read receive data buffer 2 or write transmit data buffer 2.
bits : 2 - 2 (1 bit)
access : read-write
R3T3 : Read receive data buffer 3 or write transmit data buffer 3.
bits : 3 - 3 (1 bit)
access : read-write
R4T4 : Read receive data buffer 4 or write transmit data buffer 4.
bits : 4 - 4 (1 bit)
access : read-write
R5T5 : Read receive data buffer 5 or write transmit data buffer 5.
bits : 5 - 5 (1 bit)
access : read-write
R6T6 : Read receive data buffer 6 or write transmit data buffer 6.
bits : 6 - 6 (1 bit)
access : read-write
R7T7 : Read receive data buffer 7 or write transmit data buffer 7.
bits : 7 - 7 (1 bit)
access : read-write
R8T8 : Read receive data buffer 8 or write transmit data buffer 8.
bits : 8 - 8 (1 bit)
access : read-write
R9T9 : Read receive data buffer 9 or write transmit data buffer 9.
bits : 9 - 9 (1 bit)
access : read-write
IDLINE : Idle Line
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
#0 : 0
Receiver was not idle before receiving this character.
#1 : 1
Receiver was idle before receiving this character.
End of enumeration elements list.
RXEMPT : Receive Buffer Empty
bits : 12 - 12 (1 bit)
access : read-only
Enumeration:
#0 : 0
Receive buffer contains valid data.
#1 : 1
Receive buffer is empty, data returned on read is not valid.
End of enumeration elements list.
FRETSC : Frame Error / Transmit Special Character
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
The dataword was received without a frame error on read, transmit a normal character on write.
#1 : 1
The dataword was received with a frame error, transmit an idle or break character on transmit.
End of enumeration elements list.
PARITYE : The current received dataword contained in DATA[R9:R0] was received with a parity error.
bits : 14 - 14 (1 bit)
access : read-only
Enumeration:
#0 : 0
The dataword was received without a parity error.
#1 : 1
The dataword was received with a parity error.
End of enumeration elements list.
NOISY : The current received dataword contained in DATA[R9:R0] was received with noise.
bits : 15 - 15 (1 bit)
access : read-only
Enumeration:
#0 : 0
The dataword was received without noise.
#1 : 1
The data was received with noise.
End of enumeration elements list.
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