\n
address_offset : 0x0 Bytes (0x0)
size : 0x130 byte (0x0)
mem_usage : registers
protection : not protected
Radio System Control
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BLE_RF_OSC_REQ_EN : BLE Ref Osc (Sysclk) Request Enable
bits : 0 - 0 (1 bit)
access : read-write
BLE_RF_OSC_REQ_STAT : BLE Ref Osc (Sysclk) Request Status
bits : 1 - 1 (1 bit)
access : read-only
BLE_RF_OSC_REQ_INT_EN : BLE Ref Osc (Sysclk) Request Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write
BLE_RF_OSC_REQ_INT : BLE Ref Osc (Sysclk) Request Interrupt Flag
bits : 5 - 5 (1 bit)
access : read-write
RF_OSC_EN : RF Ref Osc Enable Select
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
RF Ref Osc will be controlled by the SoC, external pin, or a link layer
#0001 : 0001
RF Ref Osc on in Run/Wait
#0011 : 0011
RF Ref Osc on in Stop
#0111 : 0111
RF Ref Osc on in VLPR/VLPW
#1111 : 1111
RF Ref Osc on in VLPS
End of enumeration elements list.
RADIO_GASKET_BYPASS_OVRD_EN : Radio Gasket Bypass Override Enable
bits : 12 - 12 (1 bit)
access : read-write
RADIO_GASKET_BYPASS_OVRD : Radio Gasket Bypass Override
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
XCVR and Link Layer Register Clock is the RF Ref Osc Clock
#1 : 1
XCVR and Link Layer Register Clock is the SoC IPG Clock
End of enumeration elements list.
RADIO_RAM_ACCESS_OVRD_EN : Radio RAM Access Override Enable
bits : 18 - 18 (1 bit)
access : read-write
RADIO_RAM_ACCESS_OVRD : Radio RAM Access Override
bits : 19 - 19 (1 bit)
access : read-write
RSIM_DSM_EXIT : BLE Force Deep Sleep Mode Exit
bits : 20 - 20 (1 bit)
access : read-write
RSIM_STOP_ACK_OVRD_EN : Stop Acknowledge Override Enable
bits : 22 - 22 (1 bit)
access : read-write
RSIM_STOP_ACK_OVRD : Stop Acknowledge Override
bits : 23 - 23 (1 bit)
access : read-write
RF_OSC_READY : RF Ref Osc Ready
bits : 24 - 24 (1 bit)
access : read-only
RF_OSC_READY_OVRD_EN : RF Ref Osc Ready Override Enable
bits : 25 - 25 (1 bit)
access : read-write
RF_OSC_READY_OVRD : RF Ref Osc Ready Override
bits : 26 - 26 (1 bit)
access : read-write
BLOCK_SOC_RESETS : Block SoC Resets of the Radio
bits : 28 - 28 (1 bit)
access : read-write
BLOCK_RADIO_OUTPUTS : Block Radio Outputs
bits : 29 - 29 (1 bit)
access : read-write
ALLOW_DFT_RESETS : Allow the DFT Reset Pin to Reset the Radio
bits : 30 - 30 (1 bit)
access : read-write
RADIO_RESET_BIT : Software Reset for the Radio
bits : 31 - 31 (1 bit)
access : read-write
Radio Miscellaneous
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RADIO_VERSION : Radio Version ID number
bits : 24 - 31 (8 bit)
access : read-write
Deep Sleep Timer
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DSM_TIMER : Deep Sleep Mode Timer
bits : 0 - 23 (24 bit)
access : read-only
Deep Sleep Timer Control
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSM_GEN_READY : Generic FSK Ready for Deep Sleep Mode
bits : 8 - 8 (1 bit)
access : read-only
GEN_DEEP_SLEEP_STATUS : Generic FSK Link Layer Deep Sleep Mode Status
bits : 9 - 9 (1 bit)
access : read-only
DSM_GEN_FINISHED : Generic FSK Deep Sleep Time Finished
bits : 10 - 10 (1 bit)
access : read-only
GEN_SYSCLK_REQUEST_EN : Enable Generic FSK Link Layer to Request RF OSC
bits : 11 - 11 (1 bit)
access : read-write
GEN_SLEEP_REQUEST : Generic FSK Link Layer Deep Sleep Requested
bits : 12 - 12 (1 bit)
access : read-only
GEN_SYSCLK_REQ : Generic FSK Link Layer RF OSC Request Status
bits : 13 - 13 (1 bit)
access : read-only
GEN_SYSCLK_INTERRUPT_EN : Generic FSK Link Layer RF OSC Request Interrupt Enable
bits : 14 - 14 (1 bit)
access : read-write
GEN_SYSCLK_REQ_INT : Interrupt Flag from an Generic FSK Link Layer RF OSC Request
bits : 15 - 15 (1 bit)
access : read-write
GEN_FSM_STATE : GEN Deep Sleep State Machine State
bits : 16 - 20 (5 bit)
access : read-only
DSM_TIMER_CLR : Deep Sleep Mode Timer Clear
bits : 27 - 27 (1 bit)
access : read-write
DSM_TIMER_EN : Deep Sleep Mode Timer Enable
bits : 31 - 31 (1 bit)
access : read-write
Deep Sleep Wakeup Time Offset
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSM_OSC_STABILIZE_TIME : Deep Sleep Wakeup RF OSC Stabilize Time
bits : 0 - 9 (10 bit)
access : read-write
Generic FSK Link Layer Sleep Time
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GEN_SLEEP_TIME : Generic FSK Link Layer Sleep Time
bits : 0 - 23 (24 bit)
access : read-write
Generic FSK Link Layer Wake Time
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GEN_WAKE_TIME : Generic FSK Link Layer Wake Time
bits : 0 - 23 (24 bit)
access : read-write
Radio Oscillator Control
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BB_XTAL_ALC_COUNT_SEL : rmap_bb_xtal_alc_count_sel_hv[1:0]
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
2048 (64 us @ 32 MHz)
#01 : 1
4096 (128 us @ 32 MHz)
#10 : 2
8192 (256 us @ 32 MHz)
#11 : 3
16384 (512 us @ 32 MHz)
End of enumeration elements list.
BB_XTAL_ALC_ON : rmap_bb_xtal_alc_on_hv
bits : 2 - 2 (1 bit)
access : read-write
RF_OSC_BYPASS_EN : RF Ref Osc Bypass Enable
bits : 3 - 3 (1 bit)
access : read-write
BB_XTAL_COMP_BIAS : rmap_bb_xtal_comp_bias_hv[4:0]
bits : 4 - 8 (5 bit)
access : read-write
BB_XTAL_DC_COUP_MODE_EN : rmap_bb_xtal_dc_coup_mode_en_hv
bits : 9 - 9 (1 bit)
access : read-write
BB_XTAL_DIAGSEL : rmap_bb_xtal_diagsel_hv
bits : 10 - 10 (1 bit)
access : read-write
BB_XTAL_DIG_CLK_ON : rmap_bb_xtal_dig_clk_on_hv
bits : 11 - 11 (1 bit)
access : read-write
BB_XTAL_GM : rmap_bb_xtal_gm_hv[4:0]
bits : 12 - 16 (5 bit)
access : read-write
BB_XTAL_ON_OVRD : rmap_bb_xtal_on_ovrd_hv
bits : 17 - 17 (1 bit)
access : read-write
BB_XTAL_ON_OVRD_ON : rmap_bb_xtal_on_ovrd_on_hv
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
rfctrl_bb_xtal_on_hv is asserted
#1 : 1
rfctrl_bb_xtal_on_ovrd_hv is asserted
End of enumeration elements list.
BB_XTAL_READY_COUNT_SEL : rmap_bb_xtal_ready_count_sel_hv[1:0]
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
#00 : 0
1024 counts (32 us @ 32 MHz)
#01 : 1
2048 (64 us @ 32 MHz)
#10 : 2
4096 (128 us @ 32 MHz)
#11 : 3
8192 (256 us @ 32 MHz)
End of enumeration elements list.
RADIO_EXT_OSC_RF_EN_SEL : Radio External Request for RF OSC Select
bits : 27 - 27 (1 bit)
access : read-write
RADIO_EXT_OSC_OVRD : Radio External Request for RF OSC Override
bits : 28 - 28 (1 bit)
access : read-write
RADIO_EXT_OSC_OVRD_EN : Radio External Request for RF OSC Override Enable
bits : 29 - 29 (1 bit)
access : read-write
RF_NOT_ALLOWED_OVRD : RF Not Allowed Override
bits : 30 - 30 (1 bit)
access : read-write
RF_NOT_ALLOWED_OVRD_EN : RF Not Allowed Override Enable
bits : 31 - 31 (1 bit)
access : read-write
Radio Analog Test Registers
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XTAL_OUT_BUF_EN : XTAL Output Buffer Enable
bits : 4 - 4 (1 bit)
access : read-write
Radio Analog Trim Registers
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BB_LDO_LS_SPARE : rmap_bb_ldo_ls_spare_hv[1:0]
bits : 0 - 1 (2 bit)
access : read-write
BB_LDO_LS_TRIM : rmap_bb_ldo_ls_trim_hv[2:0]
bits : 3 - 5 (3 bit)
access : read-write
Enumeration:
#000 : 0
1.20 V (Default)
#001 : 1
1.25 V
#010 : 2
1.28 V
#011 : 3
1.33 V
#100 : 4
1.40 V
#101 : 5
1.44 V
#110 : 6
1.50 V
#111 : 7
1.66 V
End of enumeration elements list.
BB_LDO_XO_SPARE : rmap_bb_ldo_xo_spare_hv[1:0]
bits : 6 - 7 (2 bit)
access : read-write
BB_LDO_XO_TRIM : rmap_bb_ldo_xo_trim_hv[2:0]
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 0
1.20 V (Default)
#001 : 1
1.25 V
#010 : 2
1.28 V
#011 : 3
1.33 V
#100 : 4
1.40 V
#101 : 5
1.44 V
#110 : 6
1.50 V
#111 : 7
1.66 V
End of enumeration elements list.
BB_XTAL_SPARE : rmap_bb_xtal_spare_hv[4:0]
bits : 11 - 15 (5 bit)
access : read-write
BB_XTAL_TRIM : rmap_bb_xtal_trim_hv[7:0]
bits : 16 - 23 (8 bit)
access : read-write
BG_1V_TRIM : rmap_bg_1v_trim_hv[3:0]
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
#0000 : 0
954.14 mV
#0001 : 1
959.26 mV
#0010 : 2
964.38 mV
#0011 : 3
969.5 mV
#0100 : 4
974.6 mV
#0101 : 5
979.7 mV
#0110 : 6
984.8 mV
#0111 : 7
989.9 mV
#1000 : 8
995 mV (Default)
#1001 : 9
1 V
#1010 : 10
1.005 V
#1011 : 11
1.01 V
#1100 : 12
1.015 V
#1101 : 13
1.02 V
#1110 : 14
1.025 V
#1111 : 15
1.031 V
End of enumeration elements list.
BG_IBIAS_5U_TRIM : rmap_bg_ibias_5u_trim_hv[3:0]
bits : 28 - 31 (4 bit)
access : read-write
Enumeration:
#0000 : 0
3.55 uA
#0001 : 1
3.73 uA
#0010 : 2
4.04 uA
#0011 : 3
4.22 uA
#0100 : 4
4.39 uA
#0101 : 5
4.57 uA
#0110 : 6
4.89 uA
#0111 : 7
5.06 (Default)
#1000 : 8
5.23 uA
#1001 : 9
5.41 uA
#1010 : 10
5.72 uA
#1011 : 11
5.9 uA
#1100 : 12
6.07 uA
#1101 : 13
6.25 uA
#1110 : 14
6.56 uA
#1111 : 15
6.74 uA
End of enumeration elements list.
Radio Software Configuration
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RADIO_CONFIGURED_POR_RESET : Radio Configuration Bit, cleared by Radio Power On Reset
bits : 0 - 0 (1 bit)
access : read-write
RADIO_CONFIGURED_SYS_RESET : Radio Configuration Bit, cleared by Radio System Reset
bits : 1 - 1 (1 bit)
access : read-write
RSIM_RF_ACTIVE_OVRD : RF Active Internal Override
bits : 4 - 4 (1 bit)
access : read-write
RSIM_RF_ACTIVE_OVRD_EN : RF Active Internal Override Enable
bits : 5 - 5 (1 bit)
access : read-write
RF_OSC_EN_OVRD : Radio Osc Enable Override
bits : 6 - 6 (1 bit)
access : read-write
RF_OSC_EN_OVRD_EN : Radio Osc Enable Override Enable
bits : 7 - 7 (1 bit)
access : read-write
IPP_IBE_RF_NOT_ALLOWED : IPP_IBE_RF_NOT_ALLOWED
bits : 8 - 8 (1 bit)
access : read-write
IPP_IBE_RF_EXT_OSC_EN : IPP_IBE_RF_EXT_OSC_EN
bits : 9 - 9 (1 bit)
access : read-write
IPP_IBE_DFT_RESET : IPP_IBE_DFT_RESET
bits : 10 - 10 (1 bit)
access : read-write
IPP_OBE_RF_OSC_EN : IPP_OBE_RF_OSC_EN
bits : 11 - 11 (1 bit)
access : read-write
RADIO_RF_NOT_ALLOWED_SEL : Radio RF_NOT_ALLOWED Select
bits : 12 - 12 (1 bit)
access : read-write
RADIO_DFT_RESET_SEL : Radio DFT_RESET Select
bits : 13 - 13 (1 bit)
access : read-write
RADIO_BLE_EARLY_WARNING_SEL : Radio BLE_EARLY_WARNING Select
bits : 14 - 14 (1 bit)
access : read-write
WIFI_COEXIST_1 : RF_ACTIVE Source
bits : 16 - 16 (1 bit)
access : read-only
WIFI_COEXIST_2 : RF_STATUS Source
bits : 17 - 17 (1 bit)
access : read-only
WIFI_COEXIST_3 : RF_EARLY_WARNING Source
bits : 18 - 18 (1 bit)
access : read-only
RF_ACTIVE_ENDS_WITH_TSM : RF_ACTIVE clearing mechanism
bits : 20 - 20 (1 bit)
access : read-only
SW_RF_ACTIVE_ENDS_WITH_TSM : Software RF_ACTIVE clearing mechanism
bits : 21 - 21 (1 bit)
access : read-only
SW_RF_ACTIVE_BIT : Software RF_ACTIVE Control Bit
bits : 22 - 22 (1 bit)
access : read-write
SW_RF_ACTIVE_EN : Software RF_ACTIVE Control Enable
bits : 23 - 23 (1 bit)
access : read-only
IPP_OBE_RF_PRIORITY : IPP_OBE_RF_PRIORITY
bits : 24 - 24 (1 bit)
access : read-write
IPP_OBE_RF_STATUS : IPP_OBE_RF_STATUS
bits : 25 - 25 (1 bit)
access : read-write
IPP_OBE_RF_ACTIVE : IPP_OBE_RF_ACTIVE
bits : 26 - 26 (1 bit)
access : read-write
IPP_OBE_BLE_EARLY_WARNING : IPP_OBE_BLE_EARLY_WARNING
bits : 27 - 27 (1 bit)
access : read-write
BLOCK_EXT_OSC_PWR_REQ : Block External Requests for RF OSC from starting a Radio Power Wakeup Sequence
bits : 31 - 31 (1 bit)
access : read-write
Deep Sleep Wakeup Sequence
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FINE_DELAY : Deep Sleep Wakeup Fine Delay Time
bits : 0 - 5 (6 bit)
access : read-write
COARSE_DELAY : Deep Sleep Wakeup Coarse Delay Time
bits : 16 - 19 (4 bit)
access : read-write
ACTIVE_WARNING : Deep Sleep Wakeup RF Active Warning Time
bits : 24 - 29 (6 bit)
access : read-write
Radio MAC Address
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MAC_ADDR_MSB : Radio MAC Address MSB
bits : 0 - 7 (8 bit)
access : read-only
Radio MAC Address
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MAC_ADDR_LSB : Radio MAC Address LSB
bits : 0 - 31 (32 bit)
access : read-only
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.