Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x40 byte (0x0)
mem_usage : registers
protection : not protected
TRANSCEIVER CONTROL
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PROTOCOL : Radio Protocol Selection
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
BLE
#0001 : 0001
BLE in MBAN
#0010 : 0010
BLE overlap MBAN
#0110 : 0110
Radio Channels 0-127 selectable, FSK
#0111 : 0111
Radio Channels 0-127 selectable, GFSK
#1000 : 1000
Generic GFSK, with Gaussian Filter
#1001 : 1001
Generic MSK, O-QPSK encoding
#1010 : 1010
Generic FSK, direct +/- Fdev FSK
End of enumeration elements list.
TGT_PWR_SRC : Target Power Source
bits : 4 - 6 (3 bit)
access : read-write
REF_CLK_FREQ : Radio Reference Clock Frequency
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
32 MHz
#01 : 01
26 MHz
End of enumeration elements list.
SOC_RF_OSC_CLK_GATE_EN : SOC_RF_OSC_CLK_GATE_EN
bits : 11 - 11 (1 bit)
access : read-write
DEMOD_SEL : Demodulator Selector
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
#00 : 00
No demodulator selected
#01 : 01
Use NXP Multi-standard PHY demodulator
End of enumeration elements list.
RADIO0_IRQ_SEL : RADIO0_IRQ_SEL
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
#000 : 000
Assign Radio #0 Interrupt to BLE
#001 : 001
Radio #0 Interrupt unassigned
#010 : 010
Radio #0 Interrupt unassigned
#011 : 011
Assign Radio #0 Interrupt to GENERIC_FSK
#100 : 100
Radio #0 Interrupt unassigned
#101 : 101
Radio #0 Interrupt unassigned
#110 : 110
Radio #0 Interrupt unassigned
#111 : 111
Radio #0 Interrupt unassigned
End of enumeration elements list.
RADIO1_IRQ_SEL : RADIO1_IRQ_SEL
bits : 20 - 22 (3 bit)
access : read-write
Enumeration:
#000 : 000
Assign Radio #1 Interrupt to BLE
#001 : 001
Radio #1 Interrupt unassigned
#010 : 010
Radio #1 Interrupt unassigned
#011 : 011
Assign Radio #1 Interrupt to GENERIC_FSK
#100 : 100
Radio #1 Interrupt unassigned
#101 : 101
Radio #1 Interrupt unassigned
#110 : 110
Radio #1 Interrupt unassigned
#111 : 111
Radio #1 Interrupt unassigned
End of enumeration elements list.
TSM_LL_INHIBIT : TSM Per-Link-Layer Inhibit
bits : 24 - 27 (4 bit)
access : read-write
TRANSCEIVER DMA CONTROL
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_PAGE : Transceiver DMA Page Selector
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
DMA Idle
#0001 : 0001
RX_DIG I and Q
#0010 : 0010
RX_DIG I Only
#0011 : 0011
RX_DIG Q Only
#0100 : 0100
RAW ADC I and Q
#0101 : 0101
RAW ADC I Only
#0110 : 0110
RAW ADC Q only
#0111 : 0111
DC Estimator I and Q
#1000 : 1000
DC Estimator I Only
#1001 : 1001
DC Estimator Q only
#1010 : 1010
RX_DIG Phase Output
#1100 : 1100
Demodulator Soft Decision
#1101 : 1101
Demodulator Data Output
#1110 : 1110
Demodulator CFO Phase Output
End of enumeration elements list.
DMA_EN : DMA Enable
bits : 4 - 4 (1 bit)
access : read-write
BYPASS_DMA_SYNC : Bypass External DMA Synchronization
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Don't Bypass External Synchronization. Use this setting if SINGLE_REQ_MODE=1.
#1 : 1
Bypass External Synchronization. This setting is mandatory if SINGLE_REQ_MODE=0.
End of enumeration elements list.
DMA_AA_TRIGGERED : DMA Access Address triggered
bits : 6 - 6 (1 bit)
access : read-only
DMA_TIMED_OUT : DMA Transfer Timed Out
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
A DMA timeout has not occurred
#1 : 1
A DMA timeout has occurred in Single Request Mode since the last time this bit was cleared
End of enumeration elements list.
DMA_TIMEOUT : DMA Timeout
bits : 8 - 11 (4 bit)
access : read-write
DMA_START_TRG : DMA Start Trigger Selector
bits : 12 - 14 (3 bit)
access : read-write
DMA_START_EDGE : DMA Start Trigger Edge Selector
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Trigger fires on a rising edge of the selected trigger source
#1 : 1
Trigger fires on a falling edge of the selected trigger source
End of enumeration elements list.
DMA_START_TRIGGERED : DMA Start Trigger Occurred
bits : 16 - 16 (1 bit)
access : read-only
SINGLE_REQ_MODE : DMA Single Request Mode
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable Single Request Mode. The transceiver will assert ipd_req_radio_rx whenever it has a new sample ready for transfer.
#1 : 1
Enable Single Request Mode. A single initial request by the transceiver will transfer the entire DMA block of data
End of enumeration elements list.
TRANSCEIVER DMA DATA
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DMA_DATA : DMA Data Register
bits : 0 - 31 (32 bit)
access : read-only
PACKET RAM CONTROL
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBG_PAGE : Packet RAM Debug Page Selector
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Packet RAM Debug Mode Idle
#0001 : 0001
RX_DIG I and Q
#0100 : 0100
RAW ADC I and Q
#0111 : 0111
DC Estimator I and Q
#1010 : 1010
RX_DIG Phase Output
#1100 : 1100
Demodulator Soft Decision
#1101 : 1101
Demodulator Data Output
#1110 : 1110
Demodulator CFO Phase Output
End of enumeration elements list.
DBG_EN : Packet RAM Debug Mode Enable
bits : 4 - 4 (1 bit)
access : read-write
XCVR_RAM_PAGE : RAM Page Selector for XCVR Access
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
RAM0 is mapped into XCVR address space, between XCVR_BASE + 0x700, and XCVR_BASE + 0xFFF
#1 : 1
RAM1 is mapped into XCVR address space, between XCVR_BASE + 0x700, and XCVR_BASE + 0xFFF
End of enumeration elements list.
XCVR_RAM_ALLOW : Allow Packet RAM Transceiver Access
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Protocol Engines, and associated IPS busses, have exclusive access to Packet RAM (mission mode)
#1 : 1
Transceiver-space access to Packet RAM, including Packet RAM debug mode, are allowed
End of enumeration elements list.
ALL_PROTOCOLS_ALLOW : Allow IPS bus access to Packet RAM for any protocol at any time.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
IPS bus access to Packet RAM is restricted to the protocol engine currently selected by XCVR_CTRL[PROTOCOL].
#1 : 1
All IPS bus access to Packet RAM permitted, regardless of XCVR_CTRL[PROTOCOL] setting
End of enumeration elements list.
DBG_RAM_FULL : DBG_RAM_FULL[1:0]
bits : 8 - 9 (2 bit)
access : read-only
Enumeration:
#00 : 00
Neither Packet RAM0 nor RAM1 is full
End of enumeration elements list.
DBG_AA_TRIGGERED : Packet Ram Debug Access Address triggered
bits : 10 - 10 (1 bit)
access : read-only
DBG_SOFT_INFO_SEL : Packet RAM Debug PHY Soft Info Output Selector
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
PHY input cg_vbr_en is used to capture soft decision data
#1 : 1
PHY output fsk_demod_bit_valid is used to capture soft decision data
End of enumeration elements list.
DBG_START_TRG : Packet RAM Debug Start Trigger Selector
bits : 12 - 14 (3 bit)
access : read-write
DBG_START_EDGE : Packet RAM Debug Start Trigger Edge Selector
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Trigger fires on a rising edge of the selected trigger source
#1 : 1
Trigger fires on a falling edge of the selected trigger source
End of enumeration elements list.
DBG_STOP_TRG : Packet RAM Debug Stop Trigger Selector
bits : 16 - 19 (4 bit)
access : read-write
DBG_STOP_EDGE : Packet RAM Debug Stop Trigger Edge Selector
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Trigger fires on a rising edge of the selected trigger source
#1 : 1
Trigger fires on a falling edge of the selected trigger source
End of enumeration elements list.
DBG_START_TRIGGERED : Packet RAM Debug Start Triggered
bits : 21 - 21 (1 bit)
access : read-only
DBG_STOP_TRIGGERED : Packet RAM Debug Stop Triggered
bits : 22 - 22 (1 bit)
access : read-only
PB_PROTECT : Packet Buffer Protect
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Incoming received packets overwrite Packet Buffer RX contents (default)
#1 : 1
Incoming received packets are blocked from overwriting Packet Buffer RX contents
End of enumeration elements list.
RAM0_CLK_ON_OVRD_EN : Override control for RAM0 Clock Gate Enable
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation.
#1 : 1
Use the state of RAM0_CLK_ON_OVRD to override the RAM0 Clock Gate Enable.
End of enumeration elements list.
RAM0_CLK_ON_OVRD : Override value for RAM0 Clock Gate Enable
bits : 25 - 25 (1 bit)
access : read-write
RAM1_CLK_ON_OVRD_EN : Override control for RAM1 Clock Gate Enable
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation.
#1 : 1
Use the state of RAM1_CLK_ON_OVRD to override the RAM1 Clock Gate Enable.
End of enumeration elements list.
RAM1_CLK_ON_OVRD : Override value for RAM1 Clock Gate Enable
bits : 27 - 27 (1 bit)
access : read-write
RAM0_CE_ON_OVRD_EN : Override control for RAM0 CE (Chip Enable)
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation.
#1 : 1
Use the state of RAM0_CE_ON_OVRD to override the RAM0 CE.
End of enumeration elements list.
RAM0_CE_ON_OVRD : Override value for RAM0 CE (Chip Enable)
bits : 29 - 29 (1 bit)
access : read-write
RAM1_CE_ON_OVRD_EN : Override control for RAM1 CE (Chip Enable)
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation.
#1 : 1
Use the state of RAM1_CE_ON_OVRD to override the RAM1 CE.
End of enumeration elements list.
RAM1_CE_ON_OVRD : Override value for RAM1 CE (Chip Enable)
bits : 31 - 31 (1 bit)
access : read-write
PACKET RAM DEBUG RAM STOP ADDRESS
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RAM0_STOP_ADDR : RAM0 Stop Address
bits : 0 - 10 (11 bit)
access : read-only
RAM1_STOP_ADDR : RAM1 Stop Address
bits : 16 - 26 (11 bit)
access : read-only
FAD CONTROL
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FAD_EN : This bit currently has no functionality
bits : 0 - 0 (1 bit)
access : read-write
ANTX : This bit currently has no functionality
bits : 1 - 1 (1 bit)
access : read-write
ANTX_EN : These bits currently have no functionality
bits : 4 - 5 (2 bit)
access : read-write
ANTX_HZ : This bit currently has no functionality
bits : 6 - 6 (1 bit)
access : read-write
ANTX_CTRLMODE : Antenna Diversity Control Mode
bits : 7 - 7 (1 bit)
access : read-write
ANTX_POL : FAD Antenna Controls Polarity
bits : 8 - 11 (4 bit)
access : read-write
FAD_NOT_GPIO : FAD versus GPIO Mode Selector
bits : 12 - 15 (4 bit)
access : read-write
COEXISTENCE CONTROL
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RF_NOT_ALLOWED_EN : RF_NOT_ALLOWED PER-LINK-LAYER ENABLE
bits : 0 - 3 (4 bit)
access : read-write
RF_NOT_ALLOWED_NO_TX : RF_NOT_ALLOWED_NO_TX
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Assertion on RF_NOT_ALLOWED has no effect on TX
#1 : 1
Assertion on RF_NOT_ALLOWED can abort TX
End of enumeration elements list.
RF_NOT_ALLOWED_NO_RX : RF_NOT_ALLOWED_NO_RX
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Assertion on RF_NOT_ALLOWED has no effect on RX
#1 : 1
Assertion on RF_NOT_ALLOWED can abort RX
End of enumeration elements list.
RF_NOT_ALLOWED_ASSERTED : RF_NOT_ALLOWED_ASSERTED
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Assertion on RF_NOT_ALLOWED has not occurred
#1 : 1
Assertion on RF_NOT_ALLOWED has occurred since the last time this bit was cleared
End of enumeration elements list.
RF_NOT_ALLOWED_TX_ABORT : RF_NOT_ALLOWED_TX_ABORT
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
A TX abort due to assertion on RF_NOT_ALLOWED has not occurred
#1 : 1
A TX abort due to assertion on RF_NOT_ALLOWED has occurred since the last time this bit was cleared
End of enumeration elements list.
RF_NOT_ALLOWED_RX_ABORT : RF_NOT_ALLOWED_RX_ABORT
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
A RX abort due to assertion on RF_NOT_ALLOWED has not occurred
#1 : 1
A RX abort due to assertion on RF_NOT_ALLOWED has occurred since the last time this bit was cleared
End of enumeration elements list.
RF_NOT_ALLOWED : RF_NOT_ALLOWED
bits : 9 - 9 (1 bit)
access : read-only
TSM_SPARE1_EXTEND : TSM_SPARE1_EX Extension Duration
bits : 16 - 23 (8 bit)
access : read-write
CRC/WHITENER CONFIG REGISTER
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CRCW_EN : CRC calculation enable
bits : 0 - 0 (1 bit)
access : read-write
CRCW_EC_EN : CRC Error Correction Enable
bits : 1 - 1 (1 bit)
access : read-write
CRC_ZERO : CRC zero
bits : 2 - 2 (1 bit)
access : read-only
CRC_EARLY_FAIL : CRC error correction fail
bits : 3 - 3 (1 bit)
access : read-only
CRC_RES_OUT_VLD : CRC result output valid
bits : 4 - 4 (1 bit)
access : read-only
CRC_EC_OFFSET : CRC error correction offset
bits : 16 - 26 (11 bit)
access : read-only
CRC_EC_DONE : CRC error correction done
bits : 28 - 28 (1 bit)
access : read-only
CRC_EC_FAIL : CRC error correction fail
bits : 29 - 29 (1 bit)
access : read-only
CRC ERROR CORRECTION MASK
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CRC_EC_MASK : CRC error correction mask
bits : 0 - 31 (32 bit)
access : read-only
CRC RESULT
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CRC_RES_OUT : CRC result output
bits : 0 - 31 (32 bit)
access : read-only
CRC/WHITENER CONFIG 2 REGISTER
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CRC_EC_SPKT_BYTES : Error Correction Short Packet Bytes
bits : 0 - 7 (8 bit)
access : read-write
CRC_EC_SPKT_WND : Error correction short packet burst error window
bits : 8 - 11 (4 bit)
access : read-write
CRC_EC_LPKT_WND : Error correction long packet burst error window
bits : 12 - 15 (4 bit)
access : read-write
TRANSCEIVER STATUS
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSM_COUNT : TSM_COUNT
bits : 0 - 7 (8 bit)
access : read-only
PLL_SEQ_STATE : PLL Sequence State
bits : 8 - 11 (4 bit)
access : read-only
Enumeration:
#0000 : 0
PLL OFF
#0010 : 2
CTUNE
#0011 : 3
CTUNE_SETTLE
#0110 : 6
HPMCAL1
#1000 : 8
HPMCAL1_SETTLE
#1010 : 10
HPMCAL2
#1100 : 12
HPMCAL2_SETTLE
#1111 : 15
PLLREADY
End of enumeration elements list.
RX_MODE : Receive Mode
bits : 12 - 12 (1 bit)
access : read-only
TX_MODE : Transmit Mode
bits : 13 - 13 (1 bit)
access : read-only
BTLE_SYSCLK_REQ : BTLE System Clock Request
bits : 16 - 16 (1 bit)
access : read-only
RIF_LL_ACTIVE : Link Layer Active Indication
bits : 17 - 17 (1 bit)
access : read-only
XTAL_READY : RF Osciallator Xtal Ready
bits : 18 - 18 (1 bit)
access : read-only
Enumeration:
#0 : 0
Indicates that the RF Oscillator is disabled or has not completed its warmup.
#1 : 1
Indicates that the RF Oscillator has completed its warmup count and is ready for use.
End of enumeration elements list.
SOC_USING_RF_OSC_CLK : SOC Using RF Clock Indication
bits : 19 - 19 (1 bit)
access : read-only
TSM_IRQ0 : TSM Interrupt #0
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
TSM Interrupt #0 is not asserted.
#1 : 1
TSM Interrupt #0 is asserted. Write '1' to this bit to clear it.
End of enumeration elements list.
TSM_IRQ1 : TSM Interrupt #1
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
TSM Interrupt #1 is not asserted.
#1 : 1
TSM Interrupt #1 is asserted. Write '1' to this bit to clear it.
End of enumeration elements list.
BLE ARBITRATION CONTROL
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BLE_RELINQUISH : BLE Relinquish Control
bits : 0 - 0 (1 bit)
access : read-write
XCVR_BUSY : Transceiver Busy Status Bit
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
RF Channel in available (TSM is idle)
#1 : 1
RF Channel in use (TSM is busy)
End of enumeration elements list.
OVERWRITE VERSION
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVERWRITE_VER : Overwrite Version Number.
bits : 0 - 7 (8 bit)
access : read-write
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.