\n
address_offset : 0x0 Bytes (0x0)
size : 0x7F4 byte (0x0)
mem_usage : registers
protection : not protected
Mode Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENC : Encrypt/Decrypt.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Decrypt.
#1 : 1
Encrypt.
End of enumeration elements list.
ICV_TEST : ICV Checking / Test AES fault detection.
bits : 1 - 1 (1 bit)
access : read-write
AS : Algorithm State
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 00
Update
#01 : 01
Initialize
#10 : 10
Finalize
#11 : 11
Initialize/Finalize
End of enumeration elements list.
AAI : Additional Algorithm information
bits : 4 - 12 (9 bit)
access : read-write
ALG : Algorithm
bits : 16 - 23 (8 bit)
access : read-write
Enumeration:
#10000 : 00010000
AES
End of enumeration elements list.
Data Size Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DS : Data Size
bits : 0 - 11 (12 bit)
access : read-write
Context Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTX : CTX
bits : 0 - 31 (32 bit)
access : read-write
Context Register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTX : CTX
bits : 0 - 31 (32 bit)
access : read-write
Context Register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTX : CTX
bits : 0 - 31 (32 bit)
access : read-write
Context Register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTX : CTX
bits : 0 - 31 (32 bit)
access : read-write
Context Register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTX : CTX
bits : 0 - 31 (32 bit)
access : read-write
Context Register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTX : CTX
bits : 0 - 31 (32 bit)
access : read-write
Context Register
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTX : CTX
bits : 0 - 31 (32 bit)
access : read-write
Context Register
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTX : CTX
bits : 0 - 31 (32 bit)
access : read-write
Context Register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTX : CTX
bits : 0 - 31 (32 bit)
access : read-write
Context Register
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTX : CTX
bits : 0 - 31 (32 bit)
access : read-write
Context Register
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTX : CTX
bits : 0 - 31 (32 bit)
access : read-write
Context Register
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTX : CTX
bits : 0 - 31 (32 bit)
access : read-write
Context Register
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTX : CTX
bits : 0 - 31 (32 bit)
access : read-write
Context Register
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTX : CTX
bits : 0 - 31 (32 bit)
access : read-write
ICV Size Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICVS : ICV Size, in Bytes
bits : 0 - 4 (5 bit)
access : read-write
Key Registers
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEY : KEY
bits : 0 - 31 (32 bit)
access : read-write
Key Registers
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEY : KEY
bits : 0 - 31 (32 bit)
access : read-write
Key Registers
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEY : KEY
bits : 0 - 31 (32 bit)
access : read-write
Key Registers
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEY : KEY
bits : 0 - 31 (32 bit)
access : read-write
Command Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ALL : Reset All Internal Logic
bits : 0 - 0 (1 bit)
access : write-only
Enumeration:
#0 : 0
Do Not Reset
#1 : 1
Reset all CHAs in use by this CCB.
End of enumeration elements list.
AES : Reset AESA
bits : 1 - 1 (1 bit)
access : write-only
Enumeration:
#0 : 0
Do Not Reset
#1 : 1
Reset AES Accelerator
End of enumeration elements list.
Control Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IM : Interrupt Mask
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt not masked.
#1 : 1
Interrupt masked
End of enumeration elements list.
IFE : Input FIFO DMA Enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA Request and Done signals disabled for the Input FIFO.
#1 : 1
DMA Request and Done signals enabled for the Input FIFO.
End of enumeration elements list.
IFR : Input FIFO DMA Request Size
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA request size is 1 entry.
#1 : 1
DMA request size is 4 entries.
End of enumeration elements list.
OFE : Output FIFO DMA Enable
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA Request and Done signals disabled for the Output FIFO.
#1 : 1
DMA Request and Done signals enabled for the Output FIFO.
End of enumeration elements list.
OFR : Output FIFO DMA Request Size
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA request size is 1 entry.
#1 : 1
DMA request size is 4 entries.
End of enumeration elements list.
IFS : Input FIFO Byte Swap
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do Not Byte Swap Data.
#1 : 1
Byte Swap Data.
End of enumeration elements list.
OFS : Output FIFO Byte Swap
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do Not Byte Swap Data.
#1 : 1
Byte Swap Data.
End of enumeration elements list.
KIS : Key Register Input Byte Swap
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do Not Byte Swap Data.
#1 : 1
Byte Swap Data.
End of enumeration elements list.
KOS : Key Register Output Byte Swap
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do Not Byte Swap Data.
#1 : 1
Byte Swap Data.
End of enumeration elements list.
CIS : Context Register Input Byte Swap
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do Not Byte Swap Data.
#1 : 1
Byte Swap Data.
End of enumeration elements list.
COS : Context Register Output Byte Swap
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do Not Byte Swap Data.
#1 : 1
Byte Swap Data.
End of enumeration elements list.
KAL : Key Register Access Lock
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Key Register is readable.
#1 : 1
Key Register is not readable.
End of enumeration elements list.
Clear Written Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CM : Clear the Mode Register
bits : 0 - 0 (1 bit)
access : write-only
CDS : Clear the Data Size Register
bits : 2 - 2 (1 bit)
access : write-only
CICV : Clear the ICV Size Register
bits : 3 - 3 (1 bit)
access : write-only
CCR : Clear the Context Register
bits : 5 - 5 (1 bit)
access : write-only
CKR : Clear the Key Register
bits : 6 - 6 (1 bit)
access : write-only
COF : Clear Output FIFO
bits : 30 - 30 (1 bit)
access : write-only
CIF : Clear Input FIFO
bits : 31 - 31 (1 bit)
access : write-only
Status Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AB : AESA Busy
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
AESA Idle
#1 : 1
AESA Busy.
End of enumeration elements list.
DI : Done Interrupt
bits : 16 - 16 (1 bit)
access : read-write
EI : Error Interrupt
bits : 20 - 20 (1 bit)
access : read-only
Enumeration:
#0 : 0
Not Error.
#1 : 1
Error Interrupt.
End of enumeration elements list.
Error Status Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ERRID1 : Error ID 1
bits : 0 - 3 (4 bit)
access : read-only
Enumeration:
#0001 : 0001
Mode Error
#0010 : 0010
Data Size Error
#0011 : 0011
Key Size Error
#0110 : 0110
Data Arrived out of Sequence Error
#1010 : 1010
ICV Check Failed
#1011 : 1011
Internal Hardware Failure
#1100 : 1100
CCM AAD Size Error (either 1. AAD flag in B0 =1 and no AAD type provided, 2. AAD flag in B0 = 0 and AAD povided, or 3. AAD flag in B0 =1 and not enough AAD provided - expecting more based on AAD size.)
#1111 : 1111
Invalid Crypto Engine Selected
End of enumeration elements list.
CL1 : algorithms
bits : 8 - 11 (4 bit)
access : read-only
Enumeration:
#0000 : 0000
General Error
#0001 : 0001
AES
End of enumeration elements list.
Version ID Register
address_offset : 0x4F0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MIN_REV : Minor revision number.
bits : 0 - 7 (8 bit)
access : read-only
MAJ_REV : Major revision number.
bits : 8 - 15 (8 bit)
access : read-only
IP_ID : ID(0x0034).
bits : 16 - 31 (16 bit)
access : read-only
Version ID 2 Register
address_offset : 0x4F4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ECO_REV : ECO revision number.
bits : 0 - 7 (8 bit)
access : read-only
ARCH_ERA : Architectural ERA.
bits : 8 - 15 (8 bit)
access : read-only
CHA Version ID Register
address_offset : 0x4F8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
AESREV : AES Revision Number
bits : 0 - 3 (4 bit)
access : read-only
AESVID : AES Version ID
bits : 4 - 7 (4 bit)
access : read-only
AAD Size Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AADSZ : AAD size in Bytes, mod 16
bits : 0 - 3 (4 bit)
access : read-write
AL : AAD Last
bits : 31 - 31 (1 bit)
access : read-write
FIFO Status Register
address_offset : 0x7C0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IFL : Input FIFO Level
bits : 0 - 6 (7 bit)
access : read-only
IFF : Input FIFO Full
bits : 15 - 15 (1 bit)
access : read-only
OFL : Output FIFO Level
bits : 16 - 22 (7 bit)
access : read-only
OFF : Output FIFO Full
bits : 31 - 31 (1 bit)
access : read-only
Input Data FIFO
address_offset : 0x7E0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
IFIFO : IFIFO
bits : 0 - 31 (32 bit)
access : write-only
Output Data FIFO
address_offset : 0x7F0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
OFIFO : Output FIFO
bits : 0 - 31 (32 bit)
access : read-only
Key Size Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KS : Key Size
bits : 0 - 4 (5 bit)
access : write-only
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