Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : registers
protection : not protected
DCDC REGISTER 0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCDC_DISABLE_AUTO_CLK_SWITCH : Disable automatic clock switch from internal oscillator to external clock.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Automatic clock switch feature is enabled
#1 : 1
Automatic clock switch feature is disabled
End of enumeration elements list.
DCDC_SEL_CLK : Select external clock for DCDC when DCDC_DISABLE_AUTO_CLK_SWITCH is set.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal oscillator is used as DCDC clock
#1 : 1
External oscillator is used as DCDC clock
End of enumeration elements list.
DCDC_PWD_OSC_INT : Power down internal oscillator. Only set this bit when 32M crystal oscillator is available.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal oscillator is powered up
#1 : 1
Internal oscillator is powered down
End of enumeration elements list.
DCDC_LP_DF_CMP_ENABLE : Enable low power differential comparators, to sense lower supply in pulsed mode
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#1 : 1
DCDC compare the lower supply(relative to target value) with DCDC_LP_STATE_HYS_L. When it is lower than DCDC_LP_STATE_HYS_L, re-charge output. This is the recommended configuration to guarantee optimal operation
#0 : 0
DCDC compare the common mode sense of supply(relative to target value) with DCDC_LP_STATE_HYS_L. When it is lower than DCDC_LP_STATE_HYS_L, re-charge output.
End of enumeration elements list.
DCDC_IN_DIV_CTRL : Controls DCDC_IN voltage divider
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
#00 : 00
OFF
#01 : 01
DCDC_IN
#10 : 10
DCDC_IN / 2
#11 : 11
DCDC_IN / 4
End of enumeration elements list.
DCDC_LP_STATE_HYS_L : Configure the hysteretic lower threshold value in low power mode
bits : 17 - 18 (2 bit)
access : read-write
Enumeration:
#00 : 00
Target voltage value - 0 mV
#01 : 01
Target voltage value - 25 mV
#10 : 10
Target voltage value - 50 mV
#11 : 11
Target voltage value - 75 mV
End of enumeration elements list.
DCDC_LP_STATE_HYS_H : Configure the hysteretic upper threshold value in low power mode
bits : 19 - 20 (2 bit)
access : read-write
Enumeration:
#00 : 00
Target voltage value + 0 mV
#01 : 01
Target voltage value + 25 mV
#10 : 10
Target voltage value + 50 mV
#11 : 11
Target voltage value + 75 mV
End of enumeration elements list.
HYST_LP_COMP_ADJ : Adjust hysteretic value in low power comparator
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Adjustment feature is disabled
#1 : 1
Adjustment feature is enabled
End of enumeration elements list.
HYST_LP_CMP_DISABLE : Disable hysteresis in low power comparator
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Hysteresis feature is enabled
#1 : 1
Hysteresis feature is disabled
End of enumeration elements list.
OFFSET_RSNS_LP_ADJ : Adjust hysteretic value in low power voltage sense
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Adjustment feature is disabled
#1 : 1
Adjustment feature is enabled
End of enumeration elements list.
OFFSET_RSNS_LP_DISABLE : Disable hysteresis in low power voltage sense
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Hysteresis feature is enabled
#1 : 1
Hysteresis feature is disabled
End of enumeration elements list.
DCDC_LESS_I : Reduces DCDC current by reducing the analog reference current inside the DCDC Converter
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Use normal current for analog references
#1 : 1
Use reduced current for analog references
End of enumeration elements list.
PWD_CMP_OFFSET : Output range comparator monitors the output voltage of DCDC
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Output range comparator powered up.
#1 : 1
Output range comparator powered down.
End of enumeration elements list.
DCDC_XTALOK_DISABLE : Disable xtalok detection circuit
bits : 27 - 27 (1 bit)
access : read-write
PSWITCH_STATUS : Status bit to indicate PSWITCH status
bits : 28 - 28 (1 bit)
access : read-only
Enumeration:
#0 : 0
PSWITCH is low
#1 : 1
PSWITCH is high
End of enumeration elements list.
VLPS_CONFIG_DCDC_HP : Selects behavior of DCDC in device VLPS low power mode
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
DCDC works in pulsed mode when SOC is in VLPS modes.
#1 : 1
DCDC works in continuous mode when SOC is in VLPS modes.
End of enumeration elements list.
VLPR_VLPW_CONFIG_DCDC_HP : Selects behavior of DCDC in device VLPR and VLPW low power modes
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
DCDC works in pulsed mode when SoC is in VLPR / VLPW modes.
#1 : 1
DCDC works in continuous mode when SoC is in VLPR / VLPW modes.
End of enumeration elements list.
DCDC_STS_DC_OK : Status bit to indicate that the DCDC output voltage is stable
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
Unstable DCDC output voltage
#1 : 1
Stable DCDC output voltage
End of enumeration elements list.
DCDC REGISTER 4
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCDC_SW_SHUTDOWN : Shut down DCDC in buck mode. DCDC can be turned on by pulling PSWITCH to high momentarily (DCDC Turn on time (TDCDC_ON; refer to the data sheet for specific time). This bit should not be used in buck mode when PSWITCH is tied to DCDC_IN.
bits : 0 - 0 (1 bit)
access : read-write
UNLOCK : 0x3E77 KEY-Key needed to unlock DCDC_REG4 register
bits : 16 - 31 (16 bit)
access : read-write
DCDC REGISTER 6
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSWITCH_INT_RISE_EN : Enable rising edge detect for interrupt.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
PSWITCH rising edge interrupt disabled
#1 : 1
PSWITCH rising edge interrupt enabled
End of enumeration elements list.
PSWITCH_INT_FALL_EN : Enable falling edge detect for interrupt.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
PSWITCH falling edge interrupt disabled
#1 : 1
PSWITCH falling edge interrupt enabled
End of enumeration elements list.
PSWITCH_INT_CLEAR : This bit clears the PSWITCH interrupt.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Clear PSWITCH interrupt
End of enumeration elements list.
PSWITCH_INT_MUTE : Mask interrupt to SoC, edge detection result can be read from PSIWTCH_INT_STS.
bits : 3 - 3 (1 bit)
access : read-write
PSWITCH_INT_STS : PSWITCH edge detection interrupt status
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
PSWITCH interrupt has not occurred
#1 : 1
PSWITCH interrupt has occurred
End of enumeration elements list.
DCDC REGISTER 7
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTEGRATOR_VALUE : Integrator value which can be loaded in pulsed mode
bits : 0 - 18 (19 bit)
access : read-write
INTEGRATOR_VALUE_SEL : Select the integrator value from above register or saved value in hardware.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Select the saved value in hardware.
#1 : 1
Select the integrator value in this register.
End of enumeration elements list.
PULSE_RUN_SPEEDUP : Enable pulse run speedup
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pulse run speedup feature disabled
#1 : 1
Pulse run speedup feature enabled
End of enumeration elements list.
DCDC REGISTER 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POSLIMIT_BUCK_IN : Upper limit duty cycle limit in DCDC converter
bits : 0 - 6 (7 bit)
access : read-write
DCDC_LOOPCTRL_CM_HST_THRESH : Enable hysteresis in switching converter common mode analog comparators
bits : 21 - 21 (1 bit)
access : read-write
DCDC_LOOPCTRL_DF_HST_THRESH : Enable hysteresis in switching converter differential mode analog comparators
bits : 22 - 22 (1 bit)
access : read-write
DCDC_LOOPCTRL_EN_CM_HYST : Enable hysteresis in switching converter common mode analog comparators
bits : 23 - 23 (1 bit)
access : read-write
DCDC_LOOPCTRL_EN_DF_HYST : Enable hysteresis in switching converter differential mode analog comparators
bits : 24 - 24 (1 bit)
access : read-write
DCDC REGISTER 2
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCDC_LOOPCTRL_EN_RCSCALE : The DCDC_LOOPCTRL_EN_RCSCALE reduces the response time of the DCDC to transient loads.
bits : 9 - 10 (2 bit)
access : read-write
Enumeration:
#00 : 00
Default response time
#01 : 01
2 times faster than default
#10 : 10
4 times faster than default
End of enumeration elements list.
DCDC_LOOPCTRL_HYST_SIGN : This bit ensures proper switching of DCDC in Pulsed mode and is set in Pulsed mode.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Hysteresis sign not inverted
#1 : 1
Hysteresis sign inverted (proper switching gauranteed)
End of enumeration elements list.
DCDC_BATTMONITOR_EN_BATADJ : This bit enables the DCDC to improve efficiency and minimize ripple using the information from the BATT_VAL field
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable the usage of the DCDC_BATTMONITOR_BATT_VAL value to calculate DCDC loop control
#1 : 1
Enable the usage of DCDC_BATTMONITOR_BATT_VAL value to calculate DCDC loop control
End of enumeration elements list.
DCDC_BATTMONITOR_BATT_VAL : Software should write the VDCDC_IN in this register measured with an 8 mV LSB resolution through the ADC
bits : 16 - 25 (10 bit)
access : read-write
DCDC REGISTER 3
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCDC_VDD1P8CTRL_TRG : Target value of VDD_1P8 : 25 mV each step in two ranges, from 0x00 to 0x11 and 0x20 to 0x3F and 50 mV each step in range from 0x12 to 0x1F
bits : 0 - 5 (6 bit)
access : read-write
DCDC_VDD1P5CTRL_TRG_BUCK : Target value of VDD_1P5 in buck mode, 25 mV each step from 0x00 to 0x0F Code VDD_1P8 Output Target (V) 0x00 1
bits : 6 - 10 (5 bit)
access : read-write
DCDC_VDD1P5CTRL_ADJTN : Adjust value of duty cycle when switching between VDD_1P5 and VDD_1P8
bits : 17 - 20 (4 bit)
access : read-write
DCDC_MINPWR_DC_HALFCLK_PULSED : Set DCDC clock to half frequency for the Pulsed mode.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pulsed mode uses normal operation for DCDC clock
#1 : 1
Pulsed mode uses half frequency DCDC clock operation
End of enumeration elements list.
DCDC_MINPWR_DOUBLE_FETS_PULSED : Use double switch FET for the Pulsed mode
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pulsed mode uses normal output configuration
#1 : 1
Pulsed mode uses double FET output configuration
End of enumeration elements list.
DCDC_MINPWR_HALF_FETS_PULSED : Use half switch FET for the Pulsed mode
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pulsed mode uses normal output configuration
#1 : 1
Pulsed mode uses half FET output configuration
End of enumeration elements list.
DCDC_MINPWR_DC_HALFCLK : Set DCDC clock to half frequency for the continuous mode.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation for DCDC clock
#1 : 1
DCDC clock operates at half frequency
End of enumeration elements list.
DCDC_MINPWR_DOUBLE_FETS : Use double switch FET for the continuous mode
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation
#1 : 1
Use Double FET
End of enumeration elements list.
DCDC_MINPWR_HALF_FETS : Use half switch FET for the continuous mode
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation
#1 : 1
Use Half FET
End of enumeration elements list.
DCDC_VDD1P5CTRL_DISABLE_STEP : Disable stepping for VDD_1P5. Must set this bit before enter low power modes.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
VDD_1P5 stepping enabled
#1 : 1
VDD_1P5 stepping disabled
End of enumeration elements list.
DCDC_VDD1P8CTRL_DISABLE_STEP : Disable stepping for VDD_1P8. Must set this bit before enter low power modes.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
VDD_1P8 stepping enabled
#1 : 1
VDD_1P8 stepping disabled
End of enumeration elements list.
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