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XCVR_PLL_DIG

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x58 byte (0x0)
mem_usage : registers
protection : not protected

Registers

HPM_BUMP

HPM_CTRL

HPM_SDM_RES

LPM_CTRL

LPM_SDM_CTRL1

LPM_SDM_CTRL2

LPM_SDM_CTRL3

LPM_SDM_RES1

LPM_SDM_RES2

DELAY_MATCH

MOD_CTRL

CTUNE_CTRL

CTUNE_RES

CHAN_MAP

LOCK_DETECT


HPM_BUMP

PLL HPM Analog Bump Control
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HPM_BUMP HPM_BUMP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HPM_VCM_TX HPM_VCM_CAL HPM_FDB_RES_TX HPM_FDB_RES_CAL

HPM_VCM_TX : rfctrl_tx_dac_bump_vcm[2:0] during Transmission
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#000 : 000

432 mV

#001 : 001

328 mV

#010 : 010

456 mV

#011 : 011

473 mV

#100 : 100

488 mV

#101 : 101

408 mV

#110 : 110

392 mV

#111 : 111

376 mV

End of enumeration elements list.

HPM_VCM_CAL : rfctrl_tx_dac_bump_vcm[2:0] during Calibration
bits : 4 - 6 (3 bit)
access : read-write

Enumeration:

#000 : 000

432 mV

#001 : 001

328 mV

#010 : 010

456 mV

#011 : 011

473 mV

#100 : 100

488 mV

#101 : 101

408 mV

#110 : 110

392 mV

#111 : 111

376 mV

End of enumeration elements list.

HPM_FDB_RES_TX : rfctrl_tx_dac_bump_fdb_res[1:0] during Transmission
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

#00 : 00

29 kohms

#01 : 01

58 kohms(gain of 2)

#10 : 10

13 kohms

#11 : 11

23.7 kohms

End of enumeration elements list.

HPM_FDB_RES_CAL : rfctrl_tx_dac_bump_fdb_res[1:0] during Calibration
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

#00 : 00

29 kohms

#01 : 01

58 kohms(gain of 2)

#10 : 10

13 kohms

#11 : 11

23.7 kohms

End of enumeration elements list.


HPM_CTRL

PLL High Port Modulator Control
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HPM_CTRL HPM_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HPM_SDM_IN_MANUAL HPFF HPM_SDM_OUT_INVERT HPM_SDM_IN_DISABLE HPM_LFSR_SIZE HPM_DTH_SCL HPM_DTH_EN HPM_INTEGER_SCALE HPM_INTEGER_INVERT HPM_CAL_INVERT HPM_MOD_IN_INVERT

HPM_SDM_IN_MANUAL : Manual High Port SDM Fractional value
bits : 0 - 9 (10 bit)
access : read-write

HPFF : HPM SDM Invalid Flag
bits : 13 - 13 (1 bit)
access : read-write

HPM_SDM_OUT_INVERT : Invert HPM SDM Output
bits : 14 - 14 (1 bit)
access : read-write

HPM_SDM_IN_DISABLE : Disable HPM SDM Input
bits : 15 - 15 (1 bit)
access : read-write

HPM_LFSR_SIZE : HPM LFSR Length
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

#000 : 000

LFSR 9, tap mask 100010000

#001 : 001

LFSR 10, tap mask 1001000000

#010 : 010

LFSR 11, tap mask 11101000000

#011 : 011

LFSR 13, tap mask 1101100000000

#100 : 100

LFSR 15, tap mask 111010000000000

#101 : 101

LFSR 17, tap mask 11110000000000000

End of enumeration elements list.

HPM_DTH_SCL : HPM Dither Scale
bits : 20 - 20 (1 bit)
access : read-write

HPM_DTH_EN : Dither Enable for HPM LFSR
bits : 23 - 23 (1 bit)
access : read-write

HPM_INTEGER_SCALE : High Port Modulation Integer Scale
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

#00 : 00

No Scaling

#01 : 01

Multiply by 2

#10 : 10

Divide by 2

End of enumeration elements list.

HPM_INTEGER_INVERT : Invert High Port Modulation Integer
bits : 27 - 27 (1 bit)
access : read-write

HPM_CAL_INVERT : Invert High Port Modulator Calibration
bits : 28 - 28 (1 bit)
access : read-write

HPM_MOD_IN_INVERT : Invert High Port Modulation
bits : 31 - 31 (1 bit)
access : read-write


HPM_SDM_RES

PLL High Port Sigma Delta Results
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HPM_SDM_RES HPM_SDM_RES read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HPM_NUM_SELECTED HPM_DENOM HPM_COUNT_ADJUST

HPM_NUM_SELECTED : High Port Modulator SDM Numerator
bits : 0 - 9 (10 bit)
access : read-only

HPM_DENOM : High Port Modulator SDM Denominator
bits : 16 - 25 (10 bit)
access : read-write

HPM_COUNT_ADJUST : HPM_COUNT_ADJUST
bits : 28 - 31 (4 bit)
access : read-write


LPM_CTRL

PLL Low Port Modulator Control
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LPM_CTRL LPM_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PLL_LD_MANUAL PLL_LD_DISABLE LPFF LPM_SDM_INV LPM_DISABLE LPM_DTH_SCL LPM_D_CTRL LPM_D_OVRD LPM_SCALE LPM_SDM_USE_NEG

PLL_LD_MANUAL : Manual PLL Loop Divider value
bits : 0 - 4 (5 bit)
access : read-write

PLL_LD_DISABLE : Disable PLL Loop Divider
bits : 11 - 11 (1 bit)
access : read-write

LPFF : LPM SDM Invalid Flag
bits : 13 - 13 (1 bit)
access : read-write

LPM_SDM_INV : Invert LPM SDM
bits : 14 - 14 (1 bit)
access : read-write

LPM_DISABLE : Disable LPM SDM
bits : 15 - 15 (1 bit)
access : read-write

LPM_DTH_SCL : LPM Dither Scale
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

#0101 : 0101

-128 to 96

#0110 : 0110

-256 to 192

#0111 : 0111

-512 to 384

#1000 : 1000

-1024 to 768, this is the intended setting for normal operation.

#1001 : 1001

-2048 to 1536

#1010 : 1010

-4096 to 3072

#1011 : 1011

-8192 to 6144

End of enumeration elements list.

LPM_D_CTRL : LPM Dither Control in Override Mode
bits : 22 - 22 (1 bit)
access : read-write

LPM_D_OVRD : LPM Dither Override Mode Select
bits : 23 - 23 (1 bit)
access : read-write

LPM_SCALE : LPM Scale Factor
bits : 24 - 27 (4 bit)
access : read-write

Enumeration:

#0000 : 0000

No Scaling

#0001 : 0001

Multiply by 2

#0010 : 0010

Multiply by 4

#0011 : 0011

Multiply by 8

#0100 : 0100

Multiply by 16

#0101 : 0101

Multiply by 32

#0110 : 0110

Multiply by 64

#0111 : 0111

Multiply by 128

#1000 : 1000

Multiply by 256, this is the intended setting for normal operation.

#1001 : 1001

Multiply by 512

#1010 : 1010

Multiply by 1024

#1011 : 1011

Multiply by 2048

End of enumeration elements list.

LPM_SDM_USE_NEG : Use the Negedge of the Sigma Delta clock
bits : 31 - 31 (1 bit)
access : read-write


LPM_SDM_CTRL1

PLL Low Port Sigma Delta Control 1
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LPM_SDM_CTRL1 LPM_SDM_CTRL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPM_INTG_SELECTED HPM_ARRAY_BIAS LPM_INTG SDM_MAP_DISABLE

LPM_INTG_SELECTED : Low Port Modulation Integer Value Selected
bits : 0 - 6 (7 bit)
access : read-only

HPM_ARRAY_BIAS : Bias value for High Port DAC Array Midpoint
bits : 8 - 14 (7 bit)
access : read-write

LPM_INTG : Manual Low Port Modulation Integer Value
bits : 16 - 22 (7 bit)
access : read-write

SDM_MAP_DISABLE : Disable SDM Mapping
bits : 31 - 31 (1 bit)
access : read-write


LPM_SDM_CTRL2

PLL Low Port Sigma Delta Control 2
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LPM_SDM_CTRL2 LPM_SDM_CTRL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPM_NUM

LPM_NUM : Low Port Modulation Numerator
bits : 0 - 27 (28 bit)
access : read-write


LPM_SDM_CTRL3

PLL Low Port Sigma Delta Control 3
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LPM_SDM_CTRL3 LPM_SDM_CTRL3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPM_DENOM

LPM_DENOM : Low Port Modulation Denominator
bits : 0 - 27 (28 bit)
access : read-write


LPM_SDM_RES1

PLL Low Port Sigma Delta Result 1
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

LPM_SDM_RES1 LPM_SDM_RES1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPM_NUM_SELECTED

LPM_NUM_SELECTED : Low Port Modulation Numerator Applied
bits : 0 - 27 (28 bit)
access : read-only


LPM_SDM_RES2

PLL Low Port Sigma Delta Result 2
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

LPM_SDM_RES2 LPM_SDM_RES2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPM_DENOM_SELECTED

LPM_DENOM_SELECTED : Low Port Modulation Denominator Selected
bits : 0 - 27 (28 bit)
access : read-only


DELAY_MATCH

PLL Delay Matching
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DELAY_MATCH DELAY_MATCH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPM_SDM_DELAY HPM_SDM_DELAY HPM_INTEGER_DELAY

LPM_SDM_DELAY : Low Port SDM Delay Matching
bits : 0 - 3 (4 bit)
access : read-write

HPM_SDM_DELAY : High Port SDM Delay Matching
bits : 8 - 11 (4 bit)
access : read-write

HPM_INTEGER_DELAY : High Port Integer Delay Matching
bits : 16 - 19 (4 bit)
access : read-write


MOD_CTRL

PLL Modulation Control
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MOD_CTRL MOD_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODULATION_WORD_MANUAL MOD_DISABLE HPM_MOD_MANUAL HPM_MOD_DISABLE HPM_SDM_OUT_MANUAL HPM_SDM_OUT_DISABLE

MODULATION_WORD_MANUAL : Manual Modulation Word
bits : 0 - 12 (13 bit)
access : read-write

MOD_DISABLE : Disable Modulation Word
bits : 15 - 15 (1 bit)
access : read-write

HPM_MOD_MANUAL : Manual HPM Modulation
bits : 16 - 23 (8 bit)
access : read-write

HPM_MOD_DISABLE : Disable HPM Modulation
bits : 27 - 27 (1 bit)
access : read-write

HPM_SDM_OUT_MANUAL : Manual HPM SDM out
bits : 28 - 29 (2 bit)
access : read-write

HPM_SDM_OUT_DISABLE : Disable HPM SDM out
bits : 31 - 31 (1 bit)
access : read-write


CTUNE_CTRL

PLL Coarse Tune Control
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTUNE_CTRL CTUNE_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTUNE_TARGET_MANUAL CTUNE_TARGET_DISABLE CTUNE_ADJUST CTUNE_MANUAL CTUNE_DISABLE

CTUNE_TARGET_MANUAL : Manual Coarse Tune Target
bits : 0 - 11 (12 bit)
access : read-write

CTUNE_TARGET_DISABLE : Disable Coarse Tune Target
bits : 15 - 15 (1 bit)
access : read-write

CTUNE_ADJUST : Coarse Tune Count Adjustment
bits : 16 - 19 (4 bit)
access : read-write

CTUNE_MANUAL : Manual Coarse Tune Setting
bits : 24 - 30 (7 bit)
access : read-write

CTUNE_DISABLE : Coarse Tune Disable
bits : 31 - 31 (1 bit)
access : read-write


CTUNE_RES

PLL Coarse Tune Results
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CTUNE_RES CTUNE_RES read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTUNE_SELECTED CTUNE_BEST_DIFF CTUNE_FREQ_SELECTED

CTUNE_SELECTED : Coarse Tune Setting to VCO
bits : 0 - 6 (7 bit)
access : read-only

CTUNE_BEST_DIFF : Coarse Tune Absolute Best Difference
bits : 8 - 15 (8 bit)
access : read-only

CTUNE_FREQ_SELECTED : Coarse Tune Frequency Selected
bits : 16 - 27 (12 bit)
access : read-only


CHAN_MAP

PLL Channel Mapping
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHAN_MAP CHAN_MAP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL_NUM BOC BMR HOP_TBL_CFG_OVRD HOP_TBL_CFG_OVRD_EN

CHANNEL_NUM : Protocol specific Channel Number for PLL Frequency Mapping
bits : 0 - 6 (7 bit)
access : read-write

BOC : BLE Channel Number Override
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

BLE channel number comes from the BLE Link Layer

#1 : 1

BLE channel number comes from the CHANNEL_NUM register (BLE protocols 0 and 2)

End of enumeration elements list.

BMR : BLE MBAN Channel Remap
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

BLE channel 39 is mapped to BLE channel 39, 2.480 GHz

#1 : 1

BLE channel 39 is mapped to MBAN channel 39, 2.399 GHz

End of enumeration elements list.

HOP_TBL_CFG_OVRD : Hop Table Configuration Override
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

#010 : 010

DFT_PATTERN[15:7] is signed offset to DFT_PATTERN[6:0] mapped channel number

#011 : 011

DFT_PATTERN[15:1] is signed Numerator, DFT_PATTERN[0] is integer selection

End of enumeration elements list.

HOP_TBL_CFG_OVRD_EN : Hop Table Configuration Override Enable
bits : 19 - 19 (1 bit)
access : read-write


LOCK_DETECT

PLL Lock Detect Control
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LOCK_DETECT LOCK_DETECT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CT_FAIL CTFF CS_FAIL CSFF FT_FAIL FTFF TAFF CTUNE_LDF_LEV FTF_RX_THRSH FTW_RX FTF_TX_THRSH FTW_TX FREQ_COUNT_GO FREQ_COUNT_FINISHED FREQ_COUNT_TIME

CT_FAIL : Real time status of Coarse Tune Fail signal
bits : 0 - 0 (1 bit)
access : read-only

CTFF : CTUNE Failure Flag, held until cleared
bits : 1 - 1 (1 bit)
access : read-write

CS_FAIL : Real time status of Cycle Slip circuit
bits : 2 - 2 (1 bit)
access : read-only

CSFF : Cycle Slip Failure Flag, held until cleared
bits : 3 - 3 (1 bit)
access : read-write

FT_FAIL : Real time status of Frequency Target Failure
bits : 4 - 4 (1 bit)
access : read-only

FTFF : Frequency Target Failure Flag
bits : 5 - 5 (1 bit)
access : read-write

TAFF : TSM Abort Failure Flag
bits : 7 - 7 (1 bit)
access : read-write

CTUNE_LDF_LEV : CTUNE Lock Detect Fail Level
bits : 8 - 11 (4 bit)
access : read-write

FTF_RX_THRSH : RX Frequency Target Fail Threshold
bits : 12 - 17 (6 bit)
access : read-write

FTW_RX : RX Frequency Target Window time select
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

#0 : 0

4 us

#1 : 1

8 us

End of enumeration elements list.

FTF_TX_THRSH : TX Frequency Target Fail Threshold
bits : 20 - 25 (6 bit)
access : read-write

FTW_TX : TX Frequency Target Window time select
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

#0 : 0

4 us

#1 : 1

8 us

End of enumeration elements list.

FREQ_COUNT_GO : Start the Frequency Meter
bits : 28 - 28 (1 bit)
access : read-write

FREQ_COUNT_FINISHED : Frequency Meter has finished the Count Time
bits : 29 - 29 (1 bit)
access : read-only

FREQ_COUNT_TIME : Frequency Meter Count Time
bits : 30 - 31 (2 bit)
access : read-write

Enumeration:

#00 : 00

800 us

#01 : 01

25 us

#10 : 10

50 us

#11 : 11

100 us

End of enumeration elements list.



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