DP_TOP_SYSTEM_CTRL

ANT_PDU_DATA1

ANT_PDU_DATA2

ANT_PDU_DATA3

ANT_PDU_DATA4

ANT_PDU_DATA5

ANT_PDU_DATA6

ANT_PDU_DATA7

CRCSEED

DP_FUNCTION_CTRL

DP_TEST_CTRL

BLE_DP_STATUS1

BLE_DP_STATUS2

PROP_MODE_CTRL

BLE_DP_STATUS3

BLE_DP_STATUS4

RX_FRONT_END_CTRL1

RX_FRONT_END_CTRL2

FREQ_DOMAIN_CTRL1

FREQ_DOMAIN_CTRL2

FREQ_DOMAIN_CTRL3

FREQ_DOMAIN_CTRL4

FREQ_DOMAIN_CTRL5

FREQ_DOMAIN_CTRL6

HP_MODE_CTRL1

HP_MODE_CTRL2

FREQ_DOMAIN_STATUS1

FREQ_DOMAIN_STATUS2

ACCESS_ADDRESS

DP_AA_ERROR_CTRL

DP_INT

DP_AA_ERROR_TH

DF_ANTENNA_CTRL

ANTENNA_MAP01

ANTENNA_MAP23

ANTENNA_MAP45

ANTENNA_MAP67

ANT_PDU_DATA0

RX_PDU_LEN_IN : pdu length user programmed header+payload unit is bit.
bits : 0 - 13 (14 bit)
access : read-write

AA_SEL : access address selection
bits : 14 - 14 (1 bit)
access : read-write

PDU_LEN_SEL : pdu length selection
bits : 15 - 15 (1 bit)
access : read-write

H_IDX : h index from 0.25 to 0.75 default is 0.5.
bits : 16 - 23 (8 bit)
access : read-write

RX_EN_SEL : rx enable select signal
bits : 24 - 24 (1 bit)
access : read-write

TX_EN_SEL : tx enable select signal
bits : 25 - 25 (1 bit)
access : read-write

RX_REQ : rx request.
bits : 26 - 26 (1 bit)
access : read-write

TX_REQ : tx request.
bits : 27 - 27 (1 bit)
access : read-write

RX_MODE : rx mode
bits : 28 - 29 (2 bit)
access : read-write

ANT_DATA_START : ant mode data start signal need write 0 first then to 1.
bits : 30 - 30 (1 bit)
access : read-write

DET_MODE : detection mode 0low ppwer mode 1high performance mode.
bits : 31 - 31 (1 bit)
access : read-write

PDU_DATA1 : pdu data 2 to 5 byte
bits : 0 - 31 (32 bit)
access : read-write

PDU_DATA2 : pdu data 6 to 9 byte
bits : 0 - 31 (32 bit)
access : read-write

PDU_DATA3 : pdu data 10 to 13 byte
bits : 0 - 31 (32 bit)
access : read-write

PDU_DATA4 : pdu data 14 to 17 byte
bits : 0 - 31 (32 bit)
access : read-write

PDU_DATA5 : pdu data 18 to 21 byte
bits : 0 - 31 (32 bit)
access : read-write

PDU_DATA6 : pdu data 22 to 25 byte
bits : 0 - 31 (32 bit)
access : read-write

PDU_DATA7 : pdu data 26 to 29 byte
bits : 0 - 31 (32 bit)
access : read-write

CRC_SEED_IN : user programmed crc seed.
bits : 0 - 23 (24 bit)
access : read-write

CRC_SEED_WEN : when high enable manual program crc seed.
bits : 24 - 24 (1 bit)
access : read-write

DP_STATISTICS_SEL : datapath statistics selection.
bits : 0 - 2 (3 bit)
access : read-write

CHF_COEF_WEN : manual select channel filter coefficent.
bits : 3 - 3 (1 bit)
access : read-write

CHF_COEF_IDX : no description available
bits : 4 - 5 (2 bit)
access : read-write

LP_SNR_LEN_AUTO : when enable auto adjust lp mode snr acc length otherwise the legnth fixed.
bits : 6 - 6 (1 bit)
access : read-write

DOUT_ADJ_DIS : data delay adjust disable.
bits : 7 - 7 (1 bit)
access : read-write

LP_ADJ_MODE : lp mode delay adjust mode
bits : 8 - 8 (1 bit)
access : read-write

FR_OFFSET_EN : pdu frequency offset track enable.
bits : 9 - 9 (1 bit)
access : read-write

DC_AVE_EN : when high enable cfo estimation average.
bits : 10 - 10 (1 bit)
access : read-write

FIX_DELAY_EN : no description available
bits : 11 - 11 (1 bit)
access : read-write

TRACK_LEN : track length
bits : 12 - 13 (2 bit)
access : read-write

TRACK_LEN_WEN : when high manual track length.
bits : 14 - 14 (1 bit)
access : read-write

XCORR_FILT_EN : when high enable xcorr filter.
bits : 16 - 16 (1 bit)
access : read-write

XCORR_FULLWIN_EN : when xcorr_win_auto_en low full sync enable.
bits : 17 - 17 (1 bit)
access : read-write

XCORR_AA_LEN : select access address bit number
bits : 18 - 18 (1 bit)
access : read-write

XCORR_AA_LEN_WEN : enable manual correlation aa length.
bits : 19 - 19 (1 bit)
access : read-write

XCORR_WIN_AUTO_EN : correlation window size auto selection enable.
bits : 20 - 20 (1 bit)
access : read-write

RESAMPLER_TAP : resampler tap number
bits : 21 - 21 (1 bit)
access : read-write

RESAMPLER_TAP_WEN : when high enable manual resampler tap number otherwise auto selection.
bits : 22 - 22 (1 bit)
access : read-write

RESAMPLER_BP : resampler enable or bypass
bits : 23 - 23 (1 bit)
access : read-write

FAGC_WIN_LEN : select estimation length
bits : 24 - 24 (1 bit)
access : read-write

FAGC_WEN : when high enable manual fine agc gain.
bits : 25 - 25 (1 bit)
access : read-write

HP_CFO_EN : when hp mode cfo estimation enable
bits : 26 - 26 (1 bit)
access : read-write

CFO_TRACK_EN : tracking cfo enable.
bits : 27 - 27 (1 bit)
access : read-write

CFO_INI_EN : initial cfo enable.
bits : 28 - 28 (1 bit)
access : read-write

ADC_IN_FLIP : when 1 exchange i and q signals.
bits : 29 - 29 (1 bit)
access : read-write

TX_EN_MODE : transmit mode
bits : 30 - 30 (1 bit)
access : read-write

RX_EN_MODE : receiver mode
bits : 31 - 31 (1 bit)
access : read-write

TIF_SEL : test interface selection.
bits : 0 - 7 (8 bit)
access : read-write

TIF_CLK_SEL : test interface clock selection
bits : 8 - 9 (2 bit)
access : read-write

CORDIC_DAC_OUT : when high cordic to dac
bits : 11 - 11 (1 bit)
access : read-write

TIF_EN : test interface enable
bits : 12 - 12 (1 bit)
access : read-write

IMR_INV : datapath mixer nco if selection
bits : 13 - 13 (1 bit)
access : read-write

CLK_TX_GATE_DIS : clock tx gate disable
bits : 14 - 14 (1 bit)
access : read-write

BUF_FULL_OFFRF_DIS : (new standard)______when high rf always on in rx_en other wise when buffer full rf will be off.
bits : 15 - 15 (1 bit)
access : read-write

CLK_BUST_GATE_DIS : clock burst gate disable
bits : 16 - 16 (1 bit)
access : read-write

CLK_RX_GATE_DIS : clock rx gate disable
bits : 17 - 17 (1 bit)
access : read-write

CLK_LPDET_GATE_DIS : clock lp mode detector gate disable
bits : 18 - 18 (1 bit)
access : read-write

CLK_HPDET_GATE_DIS : clock hp mode detector gate disable
bits : 19 - 19 (1 bit)
access : read-write

CLK_RFE_GATE_DIS : clock rfe gate disable
bits : 20 - 20 (1 bit)
access : read-write

IQSWAP_XOR : iq swap xor.
bits : 21 - 21 (1 bit)
access : read-write

DAC_TEST_EN : dac test enable dac input comes from register
bits : 23 - 23 (1 bit)
access : read-write

DAC_TEST : dac input data value
bits : 24 - 31 (8 bit)
access : read-write

SNR_EST : snr estimation
bits : 0 - 7 (8 bit)
access : read-only

CNR_EST : cnr estimation
bits : 8 - 13 (6 bit)
access : read-only

AGC_RSSI : signal rssi db value.
bits : 16 - 23 (8 bit)
access : read-only

AGC_RSSI_READY : signal rssi valid.
bits : 24 - 24 (1 bit)
access : read-only

SNR_VLD : snr estimation valid.
bits : 25 - 25 (1 bit)
access : read-only

CNR_VLD : cnr estimation valid.
bits : 26 - 26 (1 bit)
access : read-only

TX_BUSY : tx busy signal.
bits : 27 - 27 (1 bit)
access : read-only

VALID_PCK_NUM : received valid packet number.
bits : 0 - 15 (16 bit)
access : read-only

AA_ERR_NUM : access address error number.
bits : 16 - 21 (6 bit)
access : read-only

CRC_ERROR : indicator of packet crc error.
bits : 29 - 29 (1 bit)
access : read-only

BURST_DET : indicator of burst detection
bits : 30 - 30 (1 bit)
access : read-only

DP_STATUS_VLD_0 : data path status valid after access address valid.
bits : 31 - 31 (1 bit)
access : read-only

PROP_AA_ADDR_IN : prop mode when access address is 5 byte the access address is {prop_aa_addr_in aa_addr_in} otherwise is aa_addr_in
bits : 0 - 7 (8 bit)
access : read-write

PROP_CRC_NUM : prop mode crc number
bits : 8 - 9 (2 bit)
access : read-write

PROP_AA_NUM : prop mode network address number
bits : 12 - 13 (2 bit)
access : read-write

PROP_PRE_NUM : prop mode preamble number
bits : 16 - 18 (3 bit)
access : read-write

PROP_DATA_RATE : prop mode data rate
bits : 20 - 21 (2 bit)
access : read-write

PROP_DIRECTION_RATE : prop direction find mode sample rate
bits : 22 - 23 (2 bit)
access : read-write

PROP_DIRECTION_MODE : prop direction find mode just work at prop mode.
bits : 24 - 24 (1 bit)
access : read-write

RX_ALWAYS_ON : rx always on
bits : 25 - 25 (1 bit)
access : read-write

TX_ALWAYS_ON : tx always on
bits : 26 - 26 (1 bit)
access : read-write

TX_POWER_DONE_TIME : tx power down time in ant mode and prop mode unit is us.
bits : 27 - 31 (5 bit)
access : read-write

FD_CFO_TRACK : normalized cfo tracking estimation.
bits : 0 - 10 (11 bit)
access : read-only

CFO_EST_FD : normalized lp cfo initial estimation.
bits : 16 - 26 (11 bit)
access : read-only

RESAMPLER_PH : resampler phase.
bits : 0 - 9 (10 bit)
access : read-only

HP_CFO : normalized hp cfo estimation.
bits : 16 - 27 (12 bit)
access : read-only

HP_CFO_VLD : hp mode cfo estimation result valid
bits : 31 - 31 (1 bit)
access : read-only

CFO_COMP : ______cfo user programmed.
bits : 0 - 14 (15 bit)
access : read-write

DCNOTCH_GIN : dc notch coefficient
bits : 16 - 17 (2 bit)
access : read-write

FAGC_GAIN : fine agc gain.
bits : 0 - 10 (11 bit)
access : read-write

FAGC_INI_VAL : fagc gain initial value
bits : 11 - 11 (1 bit)
access : read-write

CNR_IDX_DELTA : cnr index delta.
bits : 12 - 15 (4 bit)
access : read-write

FAGC_REF : fine agc signal reference.
bits : 16 - 23 (8 bit)
access : read-write

CORDIC_MIN_VIN_TH : cordic input signal min threshold
bits : 24 - 27 (4 bit)
access : read-write

FREQ_TRADE_EN : enable frequency trade when cordic input signal small than cordic_min_vin_th
bits : 28 - 28 (1 bit)
access : read-write

CHN_SHIFT : channel filter shift
bits : 29 - 31 (3 bit)
access : read-write

SYNC_WORD_IN0 : manul sync word [3932]
bits : 0 - 7 (8 bit)
access : read-write

SYNC_WORD_WEN : when high enable manul sync word
bits : 8 - 8 (1 bit)
access : read-write

SYNC_P_SEL : no description available
bits : 15 - 15 (1 bit)
access : read-write

RD_EXBIT_EN : read extra 8 samples after sync
bits : 16 - 16 (1 bit)
access : read-write

RFAGC_TRACK_DLY : buffer settle threshold from 1us to 127us step is 1us
bits : 17 - 19 (3 bit)
access : read-write

PROP_DF_16US : prop mode direct found waiting 16 us.
bits : 24 - 31 (8 bit)
access : read-write

SYNC_WORD_IN1 : manul sync word [310]
bits : 0 - 31 (32 bit)
access : read-write

XCORR_PAR_TH3 : xcorr trigger par threshold3
bits : 0 - 5 (6 bit)
access : read-write

XCORR_PAR_TH2 : xcorr trigger par threshold2
bits : 8 - 13 (6 bit)
access : read-write

XCORR_PAR_TH1 : xcorr trigger par threshold1
bits : 16 - 21 (6 bit)
access : read-write

XCORR_PAR_TH0 : xcorr trigger par threshold0
bits : 24 - 29 (6 bit)
access : read-write

XCORR_POW_TH3 : xcorr power threshold3
bits : 0 - 5 (6 bit)
access : read-write

XCORR_POW_TH2 : xcorr power threshold2
bits : 8 - 13 (6 bit)
access : read-write

XCORR_POW_TH1 : xcorr power threshold1
bits : 16 - 21 (6 bit)
access : read-write

XCORR_POW_TH0 : xcorr power threshold0
bits : 24 - 29 (6 bit)
access : read-write

GAIN_TED : ted gain
bits : 0 - 1 (2 bit)
access : read-write

SYNC_DIN_SAT_VALUE : <u 1 2>sync din amplitude limit value 0 to 1.75 correspond to 2 to 3.75
bits : 4 - 6 (3 bit)
access : read-write

SYNC_DIN_SAT_EN : sync din amplitude limit enable
bits : 7 - 7 (1 bit)
access : read-write

CNT_SETTLE_IDX : buffer settle threshold from 32 to 256 step is 32
bits : 8 - 10 (3 bit)
access : read-write

TRIG_XCORR_CNT : correlation search window size.
bits : 12 - 15 (4 bit)
access : read-write

XCORR_RSSI_TH3 : xcorr triger rssi threshold0
bits : 16 - 19 (4 bit)
access : read-write

XCORR_RSSI_TH2 : xcorr triger rssi threshold0
bits : 20 - 23 (4 bit)
access : read-write

XCORR_RSSI_TH1 : xcorr triger rssi threshold0
bits : 24 - 27 (4 bit)
access : read-write

XCORR_RSSI_TH0 : xcorr triger rssi threshold0
bits : 28 - 31 (4 bit)
access : read-write

HP_TRAIN_SIZ : hp mode training size.
bits : 0 - 4 (5 bit)
access : read-write

HP_HIDX_GAIN : h index reference gain when hp mode default is 1.0
bits : 8 - 15 (8 bit)
access : read-write

H_REF_GAIN : h index reference gain when frequency offset track default is 1.0
bits : 16 - 21 (6 bit)
access : read-write

DET_FR_IDX : pdu cfo tracking loop gain
bits : 24 - 25 (2 bit)
access : read-write

CFO_FR_IDX : aa cfo tracking loop gain
bits : 28 - 29 (2 bit)
access : read-write

HP_BMC_P_TRACK : p paramter in search period of frequency offset iir of bmc
bits : 0 - 5 (6 bit)
access : read-write

HP_BMC_P_TRAIN : p paramter in training period of frequency offset iir of bmc
bits : 8 - 13 (6 bit)
access : read-write

HP_BMC_CZ1 : cz1 parameter.
bits : 16 - 21 (6 bit)
access : read-write

BUF_IDX_DELTA : buffer index delta
bits : 24 - 27 (4 bit)
access : read-write

WMF2_DSAMP_IDX : wmf2 down sampling position -4 to 3
bits : 28 - 30 (3 bit)
access : read-write

HP_TRAIN_SIZ_FIX : when high hp mode training size same as cfo tracking.
bits : 31 - 31 (1 bit)
access : read-write

SNR_EST_REF : signal amplitude used in snr estimation whose unit is db
bits : 0 - 7 (8 bit)
access : read-write

SNR_EST_LEN : symbol number used in snr estimation when pdu length is less than 4 8 32 will be used otherwise the value configured from register will be used
bits : 8 - 9 (2 bit)
access : read-write

SNR_EST_EN : snr estimation in time domain enable
bits : 12 - 12 (1 bit)
access : read-write

HP_BMC_Q_TRACK : q paramter in search period of phase offset iir of bmc
bits : 16 - 23 (8 bit)
access : read-write

HP_BMC_Q_TRAIN : q paramter in training period of phase offset iir of bmc
bits : 24 - 31 (8 bit)
access : read-write

MAX_XCORR : xcorr_org value at the max par position
bits : 0 - 9 (10 bit)
access : read-only

PKT_OFFSET_COM : time from access addres last bit to trigger finish.
bits : 16 - 24 (9 bit)
access : read-only

NIDX : noise db buffer index
bits : 28 - 31 (4 bit)
access : read-only

MAX_PAR_SPWR : spwr value at the max par position
bits : 0 - 9 (10 bit)
access : read-only

MAX_PAR_XCORR : xcorr*xcorr value at the max par position
bits : 16 - 25 (10 bit)
access : read-only

AA_ADDR_IN : access address user programmed.
bits : 0 - 31 (32 bit)
access : read-write

IQSWAP_SEL : when high adc data iq swap with analog iqswap. datapath mixer nco if selection changed with analog iqswap.
bits : 0 - 0 (1 bit)
access : read-write

AA_ERROR_EN : when high it will reset datapath when aa error.
bits : 1 - 1 (1 bit)
access : read-write

AA_ERROR_CNR_EN : when high the aa error reset condition is cnr > threshold and aa error. when low it don care cnr.
bits : 2 - 2 (1 bit)
access : read-write

AA_ERROR_CNR_SEL : when high the cnr threshold is 24. when low the cnr threshold is 32.
bits : 3 - 3 (1 bit)
access : read-write

DP_INTERRUPT0 : datapath interrupt0
bits : 0 - 0 (1 bit)
access : read-only

DP_INTERRUPT1 : datapath interrupt1
bits : 1 - 1 (1 bit)
access : read-only

DP_INTERRUPT2 : datapath interrupt2
bits : 2 - 2 (1 bit)
access : read-only

DP_INTERRUPT : datapath interrupt
bits : 3 - 3 (1 bit)
access : read-only

DP_INTERRUPT0_SEL : datapath interrupt0 selection
bits : 16 - 19 (4 bit)
access : read-write

DP_INTERRUPT1_SEL : datapath interrupt1 selection
bits : 20 - 23 (4 bit)
access : read-write

DP_INTERRUPT2_SEL : datapath interrupt2 selection
bits : 24 - 27 (4 bit)
access : read-write

DP_INTERRUPT0_MSK : datapath interrupt0 msk
bits : 28 - 28 (1 bit)
access : read-write

DP_INTERRUPT1_MSK : datapath interrupt1 msk
bits : 29 - 29 (1 bit)
access : read-write

DP_INTERRUPT2_MSK : datapath interrupt2 msk
bits : 30 - 30 (1 bit)
access : read-write

DP_INTERRUPT_MSK : datapath interrupt msk
bits : 31 - 31 (1 bit)
access : read-write

HP_TRAIN_POSITION : when high use the bits just ahead of pdu for rsve training. when low the training bit starts at the track bits.
bits : 0 - 0 (1 bit)
access : read-write

CORDIC_IN_SCALE : when high cordic input will be auto scaled(shift) according to the magnitude of real/imag data.
bits : 1 - 1 (1 bit)
access : read-write

PAR_AUTO_HIGHER_SEL : when high par auto higher 1/4 when low par auto higher 1/8 it will work together with par_auto_higher_en and rssi_good_dbm.
bits : 2 - 2 (1 bit)
access : read-write

PAR_AUTO_HIGHER_EN : when high when signal is good ( rssi large than rssi_good_dbm) it will auto higher the par threshold.
bits : 3 - 3 (1 bit)
access : read-write

SNR_GOOD_TH : threshold for snr(fd mode calculated use aa) to reset datapath cooperate with cnr snr and aa error.
bits : 4 - 6 (3 bit)
access : read-write

CNR_GOOD_TH : threshold for cnr to reset datapath cooperate with cnr snr and aa error.
bits : 8 - 13 (6 bit)
access : read-write

RSSI_GOOD_TH : threshold for rssi to reset datapath cooperate with cnr snr and aa error.
bits : 16 - 23 (8 bit)
access : read-write

RSSI_GOOD_DBM : when rssi dbm large than the -rssi_good_dbm the signal is good enough to higher the par threshold if the function enable.
bits : 24 - 31 (8 bit)
access : read-write

SWITCH_MAP_SEL_8F : switch antenna map selection 8 to f
bits : 0 - 1 (2 bit)
access : read-write

SWITCH_MAP_SEL_07 : switch antenna map selection 0 to 7
bits : 2 - 3 (2 bit)
access : read-write

EXT_ANTENNA_NUM : user programmed switch antenna number
bits : 4 - 7 (4 bit)
access : read-write

EXT_ANTENNA_NUM_WEN : user programmed switch antenna enable
bits : 8 - 8 (1 bit)
access : read-write

BUFFER_BP : when high, bypass buffer, and not write/read buffer for datapath power test
bits : 16 - 16 (1 bit)
access : read-write

TEST_TD_POWER : when high, test rfe,td detector power, other module don't work, the cordic work or not decided by resampler_bp
bits : 17 - 17 (1 bit)
access : read-write

TEST_FD_POWER : when high, test rfe, cordic and fd detector power, other module don't work
bits : 18 - 18 (1 bit)
access : read-write

TEST_SYNC_POWER : when high, test rfe. Cordic and sync power. Other module don't work
bits : 19 - 19 (1 bit)
access : read-write

TEST_RFE_CORDIC_POWER : when high, test rfe and cordic power, other module don't work
bits : 20 - 20 (1 bit)
access : read-write

TEST_RFE_POWER : when high, test rfe power, other module don't work
bits : 21 - 21 (1 bit)
access : read-write

ADC01_SAMPLE_TIME : when high, will exchange the adc0/adc1 sample time, to avoid the error sample time for adc0/adc1
bits : 22 - 22 (1 bit)
access : read-write

PHY_RATE_MUX : ble data rate used in datapath, 0: 1mbps 1: 2mbps
bits : 23 - 23 (1 bit)
access : read-only

PHY_RATE_REG : user programmed phy data rate
bits : 24 - 24 (1 bit)
access : read-write

PHY_RATE_WEN : 0: phy rate comes from ble ip 1:phy rate comes from regsiter phy_rate_reg
bits : 25 - 25 (1 bit)
access : read-write

PDU_RSSI_WAIT_TIME : 0:wait 0us 1: wait 4us
bits : 26 - 26 (1 bit)
access : read-write

PDU_RSSI_WIN_LEN : select estimation length for pdu rssi calculate
bits : 27 - 27 (1 bit)
access : read-write

CAL_PDU_RSSI_EN : calculate rssi use pdu data enbale.
bits : 28 - 28 (1 bit)
access : read-write

PROP_CRC_AA_DIS : prop mode crc check disable check access address.
bits : 29 - 29 (1 bit)
access : read-write

PROP_AA_LSB_FIRST : prop mode access address lsb first for cbt test.
bits : 30 - 30 (1 bit)
access : read-write

PRE_NUM_WEN : preamble number write enable
bits : 31 - 31 (1 bit)
access : read-write

SWITCH_MAP_1 : switch antenna map 1
bits : 0 - 13 (14 bit)
access : read-write

SWITCH_MAP_0 : switch antenna map 0
bits : 16 - 29 (14 bit)
access : read-write

SWITCH_MAP_3 : switch antenna map 3
bits : 0 - 13 (14 bit)
access : read-write

SWITCH_MAP_2 : switch antenna map 2
bits : 16 - 29 (14 bit)
access : read-write

SWITCH_MAP_5 : switch antenna map 5
bits : 0 - 13 (14 bit)
access : read-write

SWITCH_MAP_4 : switch antenna map 4
bits : 16 - 29 (14 bit)
access : read-write

SWITCH_MAP_7 : switch antenna map 7
bits : 0 - 13 (14 bit)
access : read-write

SWITCH_MAP_6 : switch antenna map 6
bits : 16 - 29 (14 bit)
access : read-write

PDU_DATA0 : pdu data 0 to 1 byte
bits : 0 - 15 (16 bit)
access : read-write

PATTERN_SEL : pattern selection
bits : 16 - 19 (4 bit)
access : read-write

TEST_PATTERN_EN : enable test pattern.
bits : 20 - 20 (1 bit)
access : read-write

PROP_PREAMBLE_WEN : when high enable manual prop mode preamble.
bits : 23 - 23 (1 bit)
access : read-write

PROP_PREAMBLE : prop mode preamble.
bits : 24 - 31 (8 bit)
access : read-write