Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
SPI Configuration register
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : SPI enable.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Disabled. The SPI is disabled and the internal state machine and counters are reset.
0x1 : ENABLED
Enabled. The SPI is enabled for operation.
End of enumeration elements list.
MASTER : Master mode select.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : SLAVE_MODE
Slave mode. The SPI will operate in slave mode. SCK, MOSI, and the SSEL signals are inputs, MISO is an output.
0x1 : MASTER_MODE
Master mode. The SPI will operate in master mode. SCK, MOSI, and the SSEL signals are outputs, MISO is an input.
End of enumeration elements list.
LSBF : LSB First mode enable.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : STANDARD
Standard. Data is transmitted and received in standard MSB first order.
0x1 : REVERSE
Reverse. Data is transmitted and received in reverse order (LSB first).
End of enumeration elements list.
CPHA : Clock Phase select.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : CHANGE
Change. The SPI captures serial data on the first clock transition of the transfer (when the clock changes away from the rest state). Data is changed on the following edge.
0x1 : CAPTURE
Capture. The SPI changes serial data on the first clock transition of the transfer (when the clock changes away from the rest state). Data is captured on the following edge.
End of enumeration elements list.
CPOL : Clock Polarity select.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : LOW
Low. The rest state of the clock (between transfers) is low.
0x1 : HIGH
High. The rest state of the clock (between transfers) is high.
End of enumeration elements list.
LOOP : Loopback mode enable. Loopback mode applies only to Master mode, and connects transmit and receive data connected together to allow simple software testing.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Disabled.
0x1 : ENABLED
Enabled.
End of enumeration elements list.
SPOL0 : SSEL0 Polarity select.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : LOW
Low. The SSEL0 pin is active low.
0x1 : HIGH
High. The SSEL0 pin is active high.
End of enumeration elements list.
SPOL1 : SSEL1 Polarity select.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : LOW
Low. The SSEL1 pin is active low.
0x1 : HIGH
High. The SSEL1 pin is active high.
End of enumeration elements list.
SPOL2 : SSEL2 Polarity select.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : LOW
Low. The SSEL2 pin is active low.
0x1 : HIGH
High. The SSEL2 pin is active high.
End of enumeration elements list.
SPOL3 : SSEL3 Polarity select.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : LOW
Low. The SSEL3 pin is active low.
0x1 : HIGH
High. The SSEL3 pin is active high.
End of enumeration elements list.
SPI Delay register
address_offset : 0x404 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRE_DELAY : Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted.
bits : 0 - 3 (4 bit)
access : read-write
POST_DELAY : Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted.
bits : 4 - 7 (4 bit)
access : read-write
FRAME_DELAY : If the EOF flag is set, controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted.
bits : 8 - 11 (4 bit)
access : read-write
TRANSFER_DELAY : Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times. 0x2 = The minimum time that SSEL is deasserted is 3 SPI clock times. 0xF = The minimum time that SSEL is deasserted is 16 SPI clock times.
bits : 12 - 15 (4 bit)
access : read-write
SPI Status. Some status flags can be cleared by writing a 1 to that bit position.
address_offset : 0x408 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SSA : Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted, in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy, and allows waking up the device from reduced power modes when a slave mode access begins. This flag is cleared by software.
bits : 4 - 4 (1 bit)
access : write-only
SSD : Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted, in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software.
bits : 5 - 5 (1 bit)
access : write-only
STALLED : Stalled status flag. This indicates whether the SPI is currently in a stall condition.
bits : 6 - 6 (1 bit)
access : read-only
ENDTRANSFER : End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress, as if the EOT flag had been set prior to the last transmission. This capability is included to support cases where it is not known when transmit data is written that it will be the end of a transfer. The bit is cleared when the transmitter becomes idle as the transfer comes to an end. Forcing an end of transfer in this manner causes any specified FRAME_DELAY and TRANSFER_DELAY to be inserted.
bits : 7 - 7 (1 bit)
access : read-write
MSTIDLE : Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data.
bits : 8 - 8 (1 bit)
access : read-only
SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set.
address_offset : 0x40C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SSAEN : Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Disabled. No interrupt will be generated when any Slave Select transitions from deasserted to asserted.
0x1 : ENABLED
Enabled. An interrupt will be generated when any Slave Select transitions from deasserted to asserted.
End of enumeration elements list.
SSDEN : Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Disabled. No interrupt will be generated when all asserted Slave Selects transition to deasserted.
0x1 : ENABLED
Enabled. An interrupt will be generated when all asserted Slave Selects transition to deasserted.
End of enumeration elements list.
MSTIDLEEN : Master idle interrupt enable.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
No interrupt will be generated when the SPI master function is idle.
0x1 : ENABLED
An interrupt will be generated when the SPI master function is fully idle.
End of enumeration elements list.
SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared.
address_offset : 0x410 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SSAEN : Writing 1 clears the corresponding bit in the INTENSET register.
bits : 4 - 4 (1 bit)
access : write-only
SSDEN : Writing 1 clears the corresponding bit in the INTENSET register.
bits : 5 - 5 (1 bit)
access : write-only
MSTIDLE : Writing 1 clears the corresponding bit in the INTENSET register.
bits : 8 - 8 (1 bit)
access : write-only
SPI clock Divider
address_offset : 0x424 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIVVAL : Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1, the value 1 results in FCLK/2, up to the maximum possible divide value of 0xFFFF, which results in FCLK/65536.
bits : 0 - 15 (16 bit)
access : read-write
SPI Interrupt Status
address_offset : 0x428 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SSA : Slave Select Assert.
bits : 4 - 4 (1 bit)
access : read-only
SSD : Slave Select Deassert.
bits : 5 - 5 (1 bit)
access : read-only
MSTIDLE : Master Idle status flag.
bits : 8 - 8 (1 bit)
access : read-only
FIFO configuration and enable register.
address_offset : 0xE00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLETX : Enable the transmit FIFO.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
The transmit FIFO is not enabled.
0x1 : ENABLED
The transmit FIFO is enabled.
End of enumeration elements list.
ENABLERX : Enable the receive FIFO.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
The transmit FIFO is not enabled.
0x1 : ENABLED
The transmit FIFO is enabled.
End of enumeration elements list.
SIZE : FIFO size configuration. This is a read-only field. 0x1 = FIFO is configured as 8 entries of 16 bits. 0x0, 0x2, 0x3 = not applicable to SPI.
bits : 4 - 5 (2 bit)
access : read-only
DMATX : DMA configuration for transmit.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : NOT_TRIGGERED
DMA is not used for the transmit function.
0x1 : TRIGGERED
Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled.
End of enumeration elements list.
DMARX : DMA configuration for receive.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : NOT_TRIGGERED
DMA is not used for the receive function.
0x1 : TRIGGERED
Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled.
End of enumeration elements list.
EMPTYTX : Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied.
bits : 16 - 16 (1 bit)
access : write-only
EMPTYRX : Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied.
bits : 17 - 17 (1 bit)
access : write-only
FIFO status register.
address_offset : 0xE04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXERR : TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit.
bits : 0 - 0 (1 bit)
access : read-write
RXERR : RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit.
bits : 1 - 1 (1 bit)
access : read-write
PERINT : Peripheral interrupt. When 1, this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral' STAT register.
bits : 3 - 3 (1 bit)
access : read-only
TXEMPTY : Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data.
bits : 4 - 4 (1 bit)
access : read-only
TXNOTFULL : Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be written. When 0, the transmit FIFO is full and another write would cause it to overflow.
bits : 5 - 5 (1 bit)
access : read-only
RXNOTEMPTY : Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty.
bits : 6 - 6 (1 bit)
access : read-only
RXFULL : Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow.
bits : 7 - 7 (1 bit)
access : read-only
TXLVL : Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be 0.
bits : 8 - 12 (5 bit)
access : read-only
RXLVL : Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be 1.
bits : 16 - 20 (5 bit)
access : read-only
FIFO trigger settings for interrupt and DMA request.
address_offset : 0xE08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXLVLENA : Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Transmit FIFO level does not generate a FIFO level trigger.
0x1 : ENABLED
An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register.
End of enumeration elements list.
RXLVLENA : Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Receive FIFO level does not generate a FIFO level trigger.
0x1 : ENABLED
An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register.
End of enumeration elements list.
TXLVL : Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode See -Hardware Wake-up control register-. 0 = trigger when the TX FIFO becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 7 = 1 = trigger when the TX FIFO level decreases to 7 entries (is no longer full).
bits : 8 - 11 (4 bit)
access : read-write
RXLVL : Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode See -Hardware Wake-up control register-. 0 = trigger when the RX FIFO has received one entry (is no longer empty). 1 = trigger when the RX FIFO has received two entries. 7 = trigger when the RX FIFO has received 8 entries (has become full).
bits : 16 - 19 (4 bit)
access : read-write
FIFO interrupt enable set (enable) and read register.
address_offset : 0xE10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXERR : Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
No interrupt will be generated for a transmit error.
0x1 : ENABLED
An interrupt will be generated when a transmit error occurs.
End of enumeration elements list.
RXERR : Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
No interrupt will be generated for a receive error.
0x1 : ENABLED
An interrupt will be generated when a receive error occurs.
End of enumeration elements list.
TXLVL : Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
No interrupt will be generated based on the TX FIFO level.
0x1 : ENABLED
If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases to the level specified by TXLVL in the FIFOTRIG register.
End of enumeration elements list.
RXLVL : Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
No interrupt will be generated based on the RX FIFO level.
0x1 : ENABLED
If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level increases to the level specified by RXLVL in the FIFOTRIG register.
End of enumeration elements list.
FIFO interrupt enable clear (disable) and read register.
address_offset : 0xE14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXERR : Writing one clears the corresponding bits in the FIFOINTENSET register.
bits : 0 - 0 (1 bit)
access : read-write
RXERR : Writing one clears the corresponding bits in the FIFOINTENSET register.
bits : 1 - 1 (1 bit)
access : read-write
TXLVL : Writing one clears the corresponding bits in the FIFOINTENSET register.
bits : 2 - 2 (1 bit)
access : read-write
RXLVL : Writing one clears the corresponding bits in the FIFOINTENSET register.
bits : 3 - 3 (1 bit)
access : read-write
FIFO interrupt status register.
address_offset : 0xE18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXERR : TX FIFO error.
bits : 0 - 0 (1 bit)
access : read-only
RXERR : RX FIFO error.
bits : 1 - 1 (1 bit)
access : read-only
TXLVL : Transmit FIFO level interrupt.
bits : 2 - 2 (1 bit)
access : read-only
RXLVL : Receive FIFO level interrupt.
bits : 3 - 3 (1 bit)
access : read-only
PERINT : Peripheral interrupt.
bits : 4 - 4 (1 bit)
access : read-only
FIFO write data.
address_offset : 0xE20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXDATA : Transmit data to the FIFO.
bits : 0 - 15 (16 bit)
access : write-only
TXSSEL0_N : Transmit Slave Select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default. Remark: The active state of the SSEL0 pin is configured by bits in the CFG register.
bits : 16 - 16 (1 bit)
access : write-only
Enumeration:
0 : ASSERTED
SSEL0 asserted.
0x1 : NOT_ASSERTED
SSEL0 not asserted.
End of enumeration elements list.
TXSSEL1_N : Transmit Slave Select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default. Remark: The active state of the SSEL1 pin is configured by bits in the CFG register.
bits : 17 - 17 (1 bit)
access : write-only
Enumeration:
0 : ASSERTED
SSEL1 asserted.
0x1 : NOT_ASSERTED
SSEL1 not asserted.
End of enumeration elements list.
TXSSEL2_N : Transmit Slave Select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default. Remark: The active state of the SSEL2 pin is configured by bits in the CFG register.
bits : 18 - 18 (1 bit)
access : write-only
Enumeration:
0 : ASSERTED
SSEL2 asserted.
0x1 : NOT_ASSERTED
SSEL2 not asserted.
End of enumeration elements list.
TXSSEL3_N : Transmit Slave Select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default. Remark: The active state of the SSEL3 pin is configured by bits in the CFG register.
bits : 19 - 19 (1 bit)
access : write-only
Enumeration:
0 : ASSERTED
SSEL3 asserted.
0x1 : NOT_ASSERTED
SSEL3 not asserted.
End of enumeration elements list.
EOT : End of Transfer. The asserted SSEL will be deasserted at the end of a transfer, and remain so for at least the time specified by the Transfer_delay value in the DLY register.
bits : 20 - 20 (1 bit)
access : write-only
Enumeration:
0 : NOT_DEASSERTED
SSEL not deasserted. This piece of data is not treated as the end of a transfer. SSEL will not be deasserted at the end of this data.
0x1 : DEASSERTED
SSEL deasserted. This piece of data is treated as the end of a transfer. SSEL will be deasserted at the end of this piece of data.
End of enumeration elements list.
EOF : End of Frame. Between frames, a delay may be inserted, as defined by the FRAME_DELAY value in the DLY register. The end of a frame may not be particularly meaningful if the FRAME_DELAY value = 0. This control can be used as part of the support for frame lengths greater than 16 bits.
bits : 21 - 21 (1 bit)
access : write-only
Enumeration:
0 : NOT_EOF
Data not EOF. This piece of data transmitted is not treated as the end of a frame.
0x1 : EOF
Data EOF. This piece of data is treated as the end of a frame, causing the FRAME_DELAY time to be inserted before subsequent data is transmitted.
End of enumeration elements list.
RXIGNORE : Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver.Setting this bit simplifies the transmit process and can be used with the DMA.
bits : 22 - 22 (1 bit)
access : write-only
Enumeration:
0 : READ
Read received data. Received data must be read in order to allow transmission to progress. In slave mode, an overrun error will occur if received data is not read before new data is received.
0x1 : IGNORE
Ignore received data. Received data is ignored, allowing transmission without reading unneeded received data. No receiver flags are generated.
End of enumeration elements list.
LEN : Data Length. Specifies the data length from 1 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0 = Data transfer is 1 bit in length. Note: when LEN = 0, the underrun status is not meaningful. 0x1 = Data transfer is 2 bits in length. 0x2 = Data transfer is 3 bits in length. 0xF = Data transfer is 16 bits in length.
bits : 24 - 27 (4 bit)
access : write-only
FIFO read data.
address_offset : 0xE30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXDATA : Received data from the FIFO.
bits : 0 - 15 (16 bit)
access : read-only
RXSSEL0_N : Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG.
bits : 16 - 16 (1 bit)
access : read-only
RXSSEL1_N : Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG.
bits : 17 - 17 (1 bit)
access : read-only
RXSSEL2_N : Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG.
bits : 18 - 18 (1 bit)
access : read-only
RXSSEL3_N : Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG.
bits : 19 - 19 (1 bit)
access : read-only
SOT : Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e., any previous transfer has ended). This information can be used to identify the first piece of data in cases where the transfer length is greater than 16 bit.
bits : 20 - 20 (1 bit)
access : read-only
FIFO data read with no FIFO pop.
address_offset : 0xE40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXDATA : Received data from the FIFO.
bits : 0 - 15 (16 bit)
access : read-only
RXSSEL0_N : Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG.
bits : 16 - 16 (1 bit)
access : read-only
RXSSEL1_N : Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG.
bits : 17 - 17 (1 bit)
access : read-only
RXSSEL2_N : Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG.
bits : 18 - 18 (1 bit)
access : read-only
RXSSEL3_N : Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG.
bits : 19 - 19 (1 bit)
access : read-only
SOT : Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e., any previous transfer has ended). This information can be used to identify the first piece of data in cases where the transfer length is greater than 16 bit.
bits : 20 - 20 (1 bit)
access : read-only
SPI module Identification. This value appears in the shared Flexcomm peripheral ID register when SPI is selected.
address_offset : 0xFFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
APERTURE : Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture.
bits : 0 - 7 (8 bit)
access : read-only
MINOR_REV : Minor revision of module implementation, starting at 0. Minor revision of module implementation, starting at 0. Software compatibility is expected between minor revisions.
bits : 8 - 11 (4 bit)
access : read-only
MAJOR_REV : Major revision of module implementation, starting at 0. There may not be software compatibility between major revisions.
bits : 12 - 15 (4 bit)
access : read-only
ID : Unique module identifier for this IP block.
bits : 16 - 31 (16 bit)
access : read-only
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