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RTC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x30 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CTRL

CAL

CNT_VAL

CNT2_CTRL

THR_INT

THR_RST

CNT2

STATUS

SEC


CTRL

RTC control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEC_INT_EN CFG CAL_EN

SEC_INT_EN : RTC second interrupt enable
bits : 0 - 0 (1 bit)
access : read-write

CFG : RTC second configuration control. This bit is self-cleared after synchronization
bits : 2 - 2 (1 bit)
access : read-write

CAL_EN : Calibration enable
bits : 8 - 8 (1 bit)
access : read-write


CAL

RTC calibration register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAL CAL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PPM DIR

PPM : RTC calibration ppm value the precision is 1 ppm.
bits : 0 - 15 (16 bit)
access : read-write

DIR : RTC calibration direction indicator
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : FORWARD

forward calibrate

0x1 : BACKWARD

backward calibrate

End of enumeration elements list.


CNT_VAL

RTC count value register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CNT_VAL CNT_VAL read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT

CNT : RTC counter current value read only.
bits : 0 - 14 (15 bit)
access : read-only


CNT2_CTRL

Free running control register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNT2_CTRL CNT2_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT2_EN CNT2_INT_EN CNT2_WAKEUP CNT2_RST

CNT2_EN : 1 to enable free running counter
bits : 0 - 0 (1 bit)
access : read-write

CNT2_INT_EN : 1 to enable free running interrupt
bits : 1 - 1 (1 bit)
access : read-write

CNT2_WAKEUP : 1 to enable free running wakeup
bits : 2 - 2 (1 bit)
access : read-write

CNT2_RST : 1 to enable free running reset
bits : 3 - 3 (1 bit)
access : read-write


THR_INT

interrupt threshold of free running counter register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

THR_INT THR_INT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 THR_INT

THR_INT : The Threshold of free running counter is to generate free running interrupt.
bits : 0 - 31 (32 bit)
access : read-write


THR_RST

reset threshold of free running counter register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

THR_RST THR_RST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 THR_RST

THR_RST : The Threshold of free running counter is to generate free running reset.
bits : 0 - 31 (32 bit)
access : read-write


CNT2

free running count value
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CNT2 CNT2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT2

CNT2 : The current value of free running counter
bits : 0 - 31 (32 bit)
access : read-only


STATUS

RTC status register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATUS STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEC_INT CTRL_SYNC STATUS_SYNC SEC_SYNC CALIB_SYNC FREE_SYNC THR_INT_SYNC THR_RST_SYNC FREE_RUNNING_INT

SEC_INT : Second interrupt flag
bits : 0 - 0 (1 bit)
access : read-write

CTRL_SYNC : Control Register synchronization busy indicator
bits : 8 - 8 (1 bit)
access : read-only

STATUS_SYNC : Status Register synchronization busy indicator
bits : 9 - 9 (1 bit)
access : read-only

SEC_SYNC : Second configuration Register synchronization busy indicator
bits : 10 - 10 (1 bit)
access : read-only

CALIB_SYNC : Calibration Register synchronization busy indicator
bits : 12 - 12 (1 bit)
access : read-only

FREE_SYNC : Free running counter control Register synchronization busy indicator
bits : 16 - 16 (1 bit)
access : read-only

THR_INT_SYNC : Free running counter interrupt Threshold Register synchronization busy indicator
bits : 17 - 17 (1 bit)
access : read-only

THR_RST_SYNC : Free running counter Reset Threshold Register synchronization busy indicator
bits : 18 - 18 (1 bit)
access : read-only

FREE_RUNNING_INT : Free running interrupt status.
bits : 31 - 31 (1 bit)
access : read-only


SEC

RTC second register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEC SEC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEC

SEC : Second configuration register.
bits : 0 - 31 (32 bit)
access : read-write



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