\n
address_offset : 0x0 Bytes (0x0)
size : 0x30 byte (0x0)
mem_usage : registers
protection : not protected
RTC control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEC_INT_EN : RTC second interrupt enable
bits : 0 - 0 (1 bit)
access : read-write
CFG : RTC second configuration control. This bit is self-cleared after synchronization
bits : 2 - 2 (1 bit)
access : read-write
CAL_EN : Calibration enable
bits : 8 - 8 (1 bit)
access : read-write
RTC calibration register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PPM : RTC calibration ppm value the precision is 1 ppm.
bits : 0 - 15 (16 bit)
access : read-write
DIR : RTC calibration direction indicator
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : FORWARD
forward calibrate
0x1 : BACKWARD
backward calibrate
End of enumeration elements list.
RTC count value register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CNT : RTC counter current value read only.
bits : 0 - 14 (15 bit)
access : read-only
Free running control register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT2_EN : 1 to enable free running counter
bits : 0 - 0 (1 bit)
access : read-write
CNT2_INT_EN : 1 to enable free running interrupt
bits : 1 - 1 (1 bit)
access : read-write
CNT2_WAKEUP : 1 to enable free running wakeup
bits : 2 - 2 (1 bit)
access : read-write
CNT2_RST : 1 to enable free running reset
bits : 3 - 3 (1 bit)
access : read-write
interrupt threshold of free running counter register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
THR_INT : The Threshold of free running counter is to generate free running interrupt.
bits : 0 - 31 (32 bit)
access : read-write
reset threshold of free running counter register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
THR_RST : The Threshold of free running counter is to generate free running reset.
bits : 0 - 31 (32 bit)
access : read-write
free running count value
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CNT2 : The current value of free running counter
bits : 0 - 31 (32 bit)
access : read-only
RTC status register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEC_INT : Second interrupt flag
bits : 0 - 0 (1 bit)
access : read-write
CTRL_SYNC : Control Register synchronization busy indicator
bits : 8 - 8 (1 bit)
access : read-only
STATUS_SYNC : Status Register synchronization busy indicator
bits : 9 - 9 (1 bit)
access : read-only
SEC_SYNC : Second configuration Register synchronization busy indicator
bits : 10 - 10 (1 bit)
access : read-only
CALIB_SYNC : Calibration Register synchronization busy indicator
bits : 12 - 12 (1 bit)
access : read-only
FREE_SYNC : Free running counter control Register synchronization busy indicator
bits : 16 - 16 (1 bit)
access : read-only
THR_INT_SYNC : Free running counter interrupt Threshold Register synchronization busy indicator
bits : 17 - 17 (1 bit)
access : read-only
THR_RST_SYNC : Free running counter Reset Threshold Register synchronization busy indicator
bits : 18 - 18 (1 bit)
access : read-only
FREE_RUNNING_INT : Free running interrupt status.
bits : 31 - 31 (1 bit)
access : read-only
RTC second register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEC : Second configuration register.
bits : 0 - 31 (32 bit)
access : read-write
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