Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
USART Configuration register. Basic USART configuration settings that typically are not changed during operation.
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : USART Enable.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0, all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control bits remain unchanged. When re-enabled, the USART will immediately be ready to transmit because the transmitter has been reset and is therefore available.
0x1 : ENABLED
Enabled. The USART is enabled for operation.
End of enumeration elements list.
DATALEN : Selects the data size for the USART.
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0 : _7_BIT
7 bit Data length.
0x1 : _8_BIT
8 bit Data length.
0x2 : _9_BIT
9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET bit in the CTL register.
End of enumeration elements list.
PARITYSEL : Selects what type of parity is used by the USART.
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : NO_PARITY
No parity.
0x2 : EVEN_PARITY
Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even, and the number of 1s in a received character is expected to be even.
0x3 : ODD_PARITY
Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd, and the number of 1s in a received character is expected to be odd.
End of enumeration elements list.
STOPLEN : Number of stop bits appended to transmitted data. Only a single stop bit is required for received data.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : _1_BIT
1 stop bit.
0x1 : _2_BITS
2 stop bits. This setting should only be used for asynchronous communication.
End of enumeration elements list.
MODE32K : Selects standard or 32 kHz clocking mode.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Disabled. USART uses standard clocking.
0x1 : ENABLED
Enabled. USART uses the 32 kHz clock from the RTC oscillator as the clock source to the BRG, and uses a special bit clocking scheme.
End of enumeration elements list.
LINMODE : LIN break mode enable.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Disabled. Break detect and generate is configured for normal operation.
0x1 : ENABLED
Enabled. Break detect and generate is configured for LIN bus operation.
End of enumeration elements list.
CTSEN : CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin, or from the USART'-s own RTS if loopback mode is enabled.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
No flow control. The transmitter does not receive any automatic flow control signal.
0x1 : ENABLED
Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes.
End of enumeration elements list.
SYNCEN : Selects synchronous or asynchronous operation.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : ASYNCHRONOUS_MODE
Asynchronous mode.
0x1 : SYNCHRONOUS_MODE
Synchronous mode.
End of enumeration elements list.
CLKPOL : Selects the clock polarity and sampling edge of received data in synchronous mode.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : FALLING_EDGE
Falling edge. Un_RXD is sampled on the falling edge of SCLK.
0x1 : RISING_EDGE
Rising edge. Un_RXD is sampled on the rising edge of SCLK.
End of enumeration elements list.
SYNCMST : Synchronous mode Master select.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : SLAVE
Slave. When synchronous mode is enabled, the USART is a slave.
0x1 : MASTER
Master. When synchronous mode is enabled, the USART is a master.
End of enumeration elements list.
LOOP : Selects data loopback mode.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : NORMAL
Normal operation.
0x1 : LOOPBACK
Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD and Un_RTS activity will also appear on external pins if these functions are configured to appear on device pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN.
End of enumeration elements list.
OETA : Output Enable Turnaround time enable for RS-485 operation.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Disabled. If selected by OESEL, the Output Enable signal deasserted at the end of the last stop bit of a transmission.
0x1 : ENABLED
Enabled. If selected by OESEL, the Output Enable signal remains asserted for one character time after the end of the last stop bit of a transmission. OE will also remain asserted if another transmit begins before it is deasserted.
End of enumeration elements list.
AUTOADDR : Automatic Address matching enable.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Disabled. When addressing is enabled by ADDRDET, address matching is done by software. This provides the possibility of versatile addressing (e.g. respond to more than one address).
0x1 : ENABLED
Enabled. When addressing is enabled by ADDRDET, address matching is done by hardware, using the value in the ADDR register as the address to match.
End of enumeration elements list.
OESEL : Output Enable Select.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : STANDARD
Standard. The RTS signal is used as the standard flow control function.
0x1 : RS_485
RS-485. The RTS signal configured to provide an output enable signal to control an RS-485 transceiver.
End of enumeration elements list.
OEPOL : Output Enable Polarity.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : LOW
Low. If selected by OESEL, the output enable is active low.
0x1 : HIGH
High. If selected by OESEL, the output enable is active high.
End of enumeration elements list.
RXPOL : Receive data polarity.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : STANDARD
Standard. The RX signal is used as it arrives from the pin. This means that the RX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1.
0x1 : INVERTED
Inverted. The RX signal is inverted before being used by the USART. This means that the RX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0.
End of enumeration elements list.
TXPOL : Transmit data polarity.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : STANDARD
Standard. The TX signal is sent out without change. This means that the TX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1.
0x1 : INVERTED
Inverted. The TX signal is inverted by the USART before being sent out. This means that the TX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0.
End of enumeration elements list.
Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared.
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXIDLECLR : Writing 1 clears the corresponding bit in the INTENSET register.
bits : 3 - 3 (1 bit)
access : write-only
DELTACTSCLR : Writing 1 clears the corresponding bit in the INTENSET register.
bits : 5 - 5 (1 bit)
access : write-only
TXDISCLR : Writing 1 clears the corresponding bit in the INTENSET register.
bits : 6 - 6 (1 bit)
access : write-only
DELTARXBRKCLR : Writing 1 clears the corresponding bit in the INTENSET register.
bits : 11 - 11 (1 bit)
access : write-only
STARTCLR : Writing 1 clears the corresponding bit in the INTENSET register.
bits : 12 - 12 (1 bit)
access : write-only
FRAMERRCLR : Writing 1 clears the corresponding bit in the INTENSET register.
bits : 13 - 13 (1 bit)
access : write-only
PARITYERRCLR : Writing 1 clears the corresponding bit in the INTENSET register.
bits : 14 - 14 (1 bit)
access : write-only
RXNOISECLR : Writing 1 clears the corresponding bit in the INTENSET register.
bits : 15 - 15 (1 bit)
access : write-only
ABERRCLR : Writing 1 clears the corresponding bit in the INTENSET register.
bits : 16 - 16 (1 bit)
access : write-only
Baud Rate Generator register. 16-bit integer baud rate divisor value.
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BRGVAL : This value is used to divide the USART input clock to determine the baud rate, based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided by 3 before use by the USART function. 0xFFFF = FCLK is divided by 65,536 before use by the USART function.
bits : 0 - 15 (16 bit)
access : read-write
Interrupt status register. Reflects interrupts that are currently enabled.
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXIDLE : Transmitter Idle status.
bits : 3 - 3 (1 bit)
access : read-only
DELTACTS : This bit is set when a change in the state of the CTS input is detected.
bits : 5 - 5 (1 bit)
access : read-only
TXDISINT : Transmitter Disabled Interrupt flag.
bits : 6 - 6 (1 bit)
access : read-only
DELTARXBRK : This bit is set when a change in the state of receiver break detection occurs.
bits : 11 - 11 (1 bit)
access : read-only
START : This bit is set when a start is detected on the receiver input.
bits : 12 - 12 (1 bit)
access : read-only
FRAMERRINT : Framing Error interrupt flag.
bits : 13 - 13 (1 bit)
access : read-only
PARITYERRINT : Parity Error interrupt flag.
bits : 14 - 14 (1 bit)
access : read-only
RXNOISEINT : Received Noise interrupt flag.
bits : 15 - 15 (1 bit)
access : read-only
ABERRINT : Auto baud Error Interrupt flag.
bits : 16 - 16 (1 bit)
access : read-only
Oversample selection register for asynchronous communication.
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OSRVAL : Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive each data bit. 0xF= 16 function clocks are used to transmit and receive each data bit.
bits : 0 - 3 (4 bit)
access : read-write
Address register for automatic address matching.
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDRESS : 8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1).
bits : 0 - 7 (8 bit)
access : read-write
USART Control register. USART control settings that are more likely to change during operation.
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXBRKEN : Break Enable.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : NORMAL
Normal operation.
0x1 : CONTINOUS
Continuous break. Continuous break is sent immediately when this bit is set, and remains until this bit is cleared. A break may be sent without danger of corrupting any currently transmitting character if the transmitter is first disabled (TXDIS in CTL is set) and then waiting for the transmitter to be disabled (TXDISINT in STAT = 1) before writing 1 to TXBRKEN.
End of enumeration elements list.
ADDRDET : Enable address detect mode.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Disabled. The USART presents all incoming data.
0x1 : ENABLED
Enabled. The USART receiver ignores incoming data that does not have the most significant bit of the data (typically the 9th bit) = 1. When the data MSB bit = 1, the receiver treats the incoming data normally, generating a received data interrupt. Software can then check the data to see if this is an address that should be handled. If it is, the ADDRDET bit is cleared by software and further incoming data is handled normally.
End of enumeration elements list.
TXDIS : Transmit Disable.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : ENABLED
Not disabled. USART transmitter is not disabled.
0x1 : DISABLED
Disabled. USART transmitter is disabled after any character currently being transmitted is complete. This feature can be used to facilitate software flow control.
End of enumeration elements list.
CC : Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : CLOCK_ON_CHARACTER
Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to complete a character that is being received.
0x1 : CONTINOUS_CLOCK
Continuous clock. SCLK runs continuously in synchronous mode, allowing characters to be received on Un_RxD independently from transmission on Un_TXD).
End of enumeration elements list.
CLRCCONRX : Clear Continuous Clock.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : NO_EFFECT
No effect. No effect on the CC bit.
0x1 : AUTO_CLEAR
Auto-clear. The CC bit is automatically cleared when a complete character has been received. This bit is cleared at the same time.
End of enumeration elements list.
AUTOBAUD : Autobaud enable.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Disabled. USART is in normal operating mode.
0x1 : ENABLED
Enabled. USART is in autobaud mode. This bit should only be set when the USART receiver is idle. The first start bit of RX is measured and used the update the BRG register to match the received data rate. AUTOBAUD is cleared once this process is complete, or if there is an AERR.
End of enumeration elements list.
USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them.
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXIDLE : Receiver Idle. When 0, indicates that the receiver is currently in the process of receiving data. When 1, indicates that the receiver is not currently in the process of receiving data.
bits : 1 - 1 (1 bit)
access : read-only
TXIDLE : Transmitter Idle. When 0, indicates that the transmitter is currently in the process of sending data.When 1, indicate that the transmitter is not currently in the process of sending data.
bits : 3 - 3 (1 bit)
access : read-only
CTS : This bit reflects the current state of the CTS signal, regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled.
bits : 4 - 4 (1 bit)
access : read-only
DELTACTS : This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software.
bits : 5 - 5 (1 bit)
access : write-only
TXDISSTAT : Transmitter Disabled Status flag. When 1, this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1).
bits : 6 - 6 (1 bit)
access : read-only
RXBRK : Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the character would be missing. RXBRK is cleared when the Un_RXD pin goes high.
bits : 10 - 10 (1 bit)
access : read-only
DELTARXBRK : This bit is set when a change in the state of receiver break detection occurs. Cleared by software.
bits : 11 - 11 (1 bit)
access : write-only
START : This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software.
bits : 12 - 12 (1 bit)
access : write-only
FRAMERRINT : Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source.
bits : 13 - 13 (1 bit)
access : write-only
PARITYERRINT : Parity Error interrupt flag. This flag is set when a parity error is detected in a received character.
bits : 14 - 14 (1 bit)
access : write-only
RXNOISEINT : Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit, except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a received data bit contains one disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or loss of synchronization during data reception.
bits : 15 - 15 (1 bit)
access : write-only
ABERR : Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the end of the start bit that is being measured, essentially an auto baud time-out.
bits : 16 - 16 (1 bit)
access : write-only
Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set.
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXIDLEEN : When 1, enables an interrupt when the transmitter becomes idle (TXIDLE = 1).
bits : 3 - 3 (1 bit)
access : read-write
DELTACTSEN : When 1, enables an interrupt when there is a change in the state of the CTS input.
bits : 5 - 5 (1 bit)
access : read-write
TXDISEN : When 1, enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details.
bits : 6 - 6 (1 bit)
access : read-write
DELTARXBRKEN : When 1, enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted).
bits : 11 - 11 (1 bit)
access : read-write
STARTEN : When 1, enables an interrupt when a received start bit has been detected.
bits : 12 - 12 (1 bit)
access : read-write
FRAMERREN : When 1, enables an interrupt when a framing error has been detected.
bits : 13 - 13 (1 bit)
access : read-write
PARITYERREN : When 1, enables an interrupt when a parity error has been detected.
bits : 14 - 14 (1 bit)
access : read-write
RXNOISEEN : When 1, enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354.
bits : 15 - 15 (1 bit)
access : read-write
ABERREN : When 1, enables an interrupt when an auto baud error occurs.
bits : 16 - 16 (1 bit)
access : read-write
FIFO configuration and enable register.
address_offset : 0xE00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLETX : Enable the transmit FIFO.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
The transmit FIFO is not enabled.
0x1 : ENABLED
The transmit FIFO is enabled.
End of enumeration elements list.
ENABLERX : Enable the receive FIFO.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
The receive FIFO is not enabled.
0x1 : ENABLED
The receive FIFO is enabled.
End of enumeration elements list.
SIZE : FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART.
bits : 4 - 5 (2 bit)
access : read-only
DMATX : DMA configuration for transmit.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
DMA is not used for the transmit function.
0x1 : ENABLED
Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled.
End of enumeration elements list.
DMARX : DMA configuration for receive.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
DMA is not used for the receive function.
0x1 : ENABLED
Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled.
End of enumeration elements list.
EMPTYTX : Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied.
bits : 16 - 16 (1 bit)
access : read-write
EMPTYRX : Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied.
bits : 17 - 17 (1 bit)
access : read-write
FIFO status register.
address_offset : 0xE04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXERR : TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit.
bits : 0 - 0 (1 bit)
access : read-write
RXERR : RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit.
bits : 1 - 1 (1 bit)
access : read-write
PERINT : Peripheral interrupt. When 1, this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral'-s STAT register.
bits : 3 - 3 (1 bit)
access : read-only
TXEMPTY : Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data.
bits : 4 - 4 (1 bit)
access : read-only
TXNOTFULL : Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be written. When 0, the transmit FIFO is full and another write would cause it to overflow.
bits : 5 - 5 (1 bit)
access : read-only
RXNOTEMPTY : Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty.
bits : 6 - 6 (1 bit)
access : read-only
RXFULL : Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow.
bits : 7 - 7 (1 bit)
access : read-only
TXLVL : Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be 0.
bits : 8 - 12 (5 bit)
access : read-only
RXLVL : Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be 1.
bits : 16 - 20 (5 bit)
access : read-only
FIFO trigger settings for interrupt and DMA request.
address_offset : 0xE08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXLVLENA : Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Transmit FIFO level does not generate a FIFO level trigger.
0x1 : ENABLED
An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register.
End of enumeration elements list.
RXLVLENA : Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Receive FIFO level does not generate a FIFO level trigger.
0x1 : ENABLED
An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register.
End of enumeration elements list.
TXLVL : Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX FIFO level decreases to 15 entries (is no longer full).
bits : 8 - 11 (4 bit)
access : read-write
RXLVL : Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX FIFO has received 16 entries (has become full).
bits : 16 - 19 (4 bit)
access : read-write
FIFO interrupt enable set (enable) and read register.
address_offset : 0xE10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXERR : Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
No interrupt will be generated for a transmit error.
0x1 : ENABLED
An interrupt will be generated when a transmit error occurs.
End of enumeration elements list.
RXERR : Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
No interrupt will be generated for a receive error.
0x1 : ENABLED
An interrupt will be generated when a receive error occurs.
End of enumeration elements list.
TXLVL : Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
No interrupt will be generated based on the TX FIFO level.
0x1 : ENABLED
If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases to the level specified by TXLVL in the FIFOTRIG register.
End of enumeration elements list.
RXLVL : Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
No interrupt will be generated based on the RX FIFO level.
0x1 : ENABLED
If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level increases to the level specified by RXLVL in the FIFOTRIG register.
End of enumeration elements list.
FIFO interrupt enable clear (disable) and read register.
address_offset : 0xE14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXERR : Writing one clears the corresponding bits in the FIFOINTENSET register.
bits : 0 - 0 (1 bit)
access : read-write
RXERR : Writing one clears the corresponding bits in the FIFOINTENSET register.
bits : 1 - 1 (1 bit)
access : read-write
TXLVL : Writing one clears the corresponding bits in the FIFOINTENSET register.
bits : 2 - 2 (1 bit)
access : read-write
RXLVL : Writing one clears the corresponding bits in the FIFOINTENSET register.
bits : 3 - 3 (1 bit)
access : read-write
FIFO interrupt status register.
address_offset : 0xE18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXERR : TX FIFO error.
bits : 0 - 0 (1 bit)
access : read-only
RXERR : RX FIFO error.
bits : 1 - 1 (1 bit)
access : read-only
TXLVL : Transmit FIFO level interrupt.
bits : 2 - 2 (1 bit)
access : read-only
RXLVL : Receive FIFO level interrupt.
bits : 3 - 3 (1 bit)
access : read-only
PERINT : Peripheral interrupt.
bits : 4 - 4 (1 bit)
access : read-only
FIFO write data.
address_offset : 0xE20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXDATA : Transmit data to the FIFO.
bits : 0 - 8 (9 bit)
access : write-only
FIFO read data.
address_offset : 0xE30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXDATA : Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings.
bits : 0 - 8 (9 bit)
access : read-only
FRAMERR : Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO, and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source.
bits : 13 - 13 (1 bit)
access : read-only
PARITYERR : Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character.
bits : 14 - 14 (1 bit)
access : read-only
RXNOISE : Received Noise flag. See description of the RxNoiseInt bit in Table 354.
bits : 15 - 15 (1 bit)
access : read-only
FIFO data read with no FIFO pop.
address_offset : 0xE40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXDATA : Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings.
bits : 0 - 8 (9 bit)
access : read-only
FRAMERR : Framing Error status flag. This bit reflects the status for the data it is read along with from the FIFO, and indicates that the character was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source.
bits : 13 - 13 (1 bit)
access : read-only
PARITYERR : Parity Error status flag. This bit reflects the status for the data it is read along with from the FIFO. This bit will be set when a parity error is detected in a received character.
bits : 14 - 14 (1 bit)
access : read-only
RXNOISE : Received Noise flag. See description of the RxNoiseInt bit in Table 354.
bits : 15 - 15 (1 bit)
access : read-only
USART module Identification. This value appears in the shared Flexcomm peripheral ID register when USART is selected.
address_offset : 0xFFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
APERTURE : Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture.
bits : 0 - 7 (8 bit)
access : read-only
MINOR_REV : Minor revision of module implementation, starting at 0. Minor revision of module implementation, starting at 0. Software compatibility is expected between minor revisions.
bits : 8 - 11 (4 bit)
access : read-only
MAJOR_REV : Major revision of module implementation, starting at 0. There may not be software compatibility between major revisions.
bits : 12 - 15 (4 bit)
access : read-only
ID : Unique module identifier for this IP block.
bits : 16 - 31 (16 bit)
access : read-only
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