\n
address_offset : 0x0 Bytes (0x0)
size : 0x1C byte (0x0)
mem_usage : registers
protection : not protected
AGC control register 0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PPF_INTRPT_MOD : Control whether fsm can interrupt
bits : 0 - 1 (2 bit)
access : read-write
FREZ_MOD : Control whether fsm can restore last value when correalation trigh happens
bits : 2 - 3 (2 bit)
access : read-write
RRF_GAIN_SEL : LNA gain controlGAIN=26-12*LNA_GAIN_SEL
bits : 4 - 6 (3 bit)
access : read-write
RRF_WEN : Lna gain write enable
bits : 7 - 7 (1 bit)
access : read-write
PPF_GAIN : PPF gain controlGain=36-3*PPF_GAIN
bits : 8 - 11 (4 bit)
access : read-write
PPF_WEN : Ppf gain write enable
bits : 12 - 12 (1 bit)
access : read-write
PKWT_TH_DIG_1 : PKWT_TH_DIG + PKWT_TH_DIG_ADD in ccode
bits : 13 - 17 (5 bit)
access : read-write
PD_CLR_EN : Force clear analog PD
bits : 18 - 18 (1 bit)
access : read-write
PD_RST_LEN : Pd disable time when reset0h0us 1h8us 2h16us 7h56us
bits : 19 - 21 (3 bit)
access : read-write
RFAGC_FSYNC_DET_DIS : Use to control rfagc gain adjust0brfagc stops when sync 1brfagc always on
bits : 22 - 22 (1 bit)
access : read-write
RFAGC_DIRECTION_FREEZE : Use to disable rfagc gain adjust when switching antenna at direction found mode0b rfagc enable 1brfagc disable
bits : 23 - 23 (1 bit)
access : read-write
DOWN_24_EN : Lna decrease 24dbm0bdisable 1benable
bits : 24 - 24 (1 bit)
access : read-write
SWITCH_PD_RST_LEN : Pd disable time when direction found rfagc reset00b2us 01b4us 10b8us 11b16us
bits : 25 - 26 (2 bit)
access : read-write
GLNA_MAX_REDU : Lna max gain reduce 12dbm0bdisable 1benable
bits : 27 - 27 (1 bit)
access : read-write
AGC control register 4
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETL_TH_PD1 : no description available
bits : 0 - 3 (4 bit)
access : read-write
SETL_TH_PD2 : no description available
bits : 4 - 7 (4 bit)
access : read-write
SETL_TH_PD3_1 : no description available
bits : 8 - 13 (6 bit)
access : read-write
SETL_TH_PD3_2 : no description available
bits : 14 - 19 (6 bit)
access : read-write
GF2_STAT24_TH : no description available
bits : 20 - 23 (4 bit)
access : read-write
AGC control register 5
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TEST_CTRL : no description available
bits : 0 - 3 (4 bit)
access : read-write
AGC status register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
GLNA_CODE_OUT : no description available
bits : 0 - 2 (3 bit)
access : read-only
GF2_CODE_OUT : no description available
bits : 3 - 6 (4 bit)
access : read-only
RFAGC_TRIGGER_O : no description available
bits : 7 - 7 (1 bit)
access : read-only
RF_GAIN : no description available
bits : 8 - 14 (7 bit)
access : read-only
NUM_GAIN_ADJ : no description available
bits : 15 - 19 (5 bit)
access : read-only
CUR_STAT : no description available
bits : 20 - 22 (3 bit)
access : read-only
AGC control register 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PD3_TH_REG : Pd3 threshold
bits : 0 - 2 (3 bit)
access : read-write
PD3_TH_HYST_REG : Desired upper boundary
bits : 3 - 6 (4 bit)
access : read-write
PKWT_TH_ANA_1 : PKWT_TH_ANA + PKWT_TH_ANA_ADD
bits : 7 - 12 (6 bit)
access : read-write
PKWT_TH_ANA_0 : PKWT_TH_ANA in ccode
bits : 13 - 17 (5 bit)
access : read-write
PKWT_TH_DIG_0 : PKWT_TH_DIG in ccode
bits : 18 - 22 (5 bit)
access : read-write
SETL_TH_PPF_2 : SETL_TH_PPF_2 + DLY_DIG 1 in ccode
bits : 23 - 27 (5 bit)
access : read-write
AGC control register 2
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PPF_PDVTH_LOW : PPF peak detect threshold select
bits : 8 - 8 (1 bit)
access : read-write
RRF_MG_PK : LNA medium gain peak detect threshold selectAMP=(400-25* LNA_MG_PK)mv
bits : 9 - 11 (3 bit)
access : read-write
RRF_HG_PK : LNA high gain peak detect threshold selectAMP=(100-8* LNA_HG_PK)mv
bits : 12 - 14 (3 bit)
access : read-write
AGC control register 3
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GF2_PAR00 : no description available
bits : 0 - 3 (4 bit)
access : read-write
GF2_PAR01 : no description available
bits : 4 - 7 (4 bit)
access : read-write
GF2_PAR10 : no description available
bits : 8 - 11 (4 bit)
access : read-write
SETL_TH_OVSHT_DIG : no description available
bits : 12 - 14 (3 bit)
access : read-write
SETL_TH_OVSHT_INTRPT : no description available
bits : 15 - 17 (3 bit)
access : read-write
SETL_TH_OVSHT : no description available
bits : 18 - 20 (3 bit)
access : read-write
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