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FLASH

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xB0 byte (0x0)
mem_usage : registers
protection : not protected

Registers

INI_RD_EN

SMART_CTRL

INTEN

INT_STAT

INTCLR

LOCK_STAT0

LOCK_STAT1

LOCK_STAT2

LOCK_STAT3

LOCK_STAT4

LOCK_STAT5

LOCK_STAT6

LOCK_STAT7

ERASE_CTRL

LOCK_STAT8

STATUS1

ERR_INFOL1

ERR_INFOL2

ERR_INFOL3

ERR_INFOH1

ERR_INFOH2

ERR_INFOH3

ERASE_TIME

DEBUG_PASSWORD

ERASE_PASSWORD

TIME_CTRL


INI_RD_EN

flash initial read register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INI_RD_EN INI_RD_EN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INI_RD_EN

INI_RD_EN : enable contoller to automatically read GDR repaired information and lock bit
bits : 0 - 0 (1 bit)
access : read-write


SMART_CTRL

smart erase control register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SMART_CTRL SMART_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRGML_EN PRGMH_EN SMART_WRITEL_EN SMART_WRITEH_EN SMART_ERASEL_EN SMART_ERASEH_EN MAX_WRITE MAX_ERASE

PRGML_EN : It enable Low 256KB Flash write operation;
bits : 0 - 0 (1 bit)
access : read-write

PRGMH_EN : It enable High 256KB Flash write operation;
bits : 1 - 1 (1 bit)
access : read-write

SMART_WRITEL_EN : It enable Low 256KB Flash Smart program flow. When smart write is done, hardware automatically clear it
bits : 2 - 2 (1 bit)
access : read-write

SMART_WRITEH_EN : It enable High 256KB Flash Smart program flow. When smart write is done, hardware automatically clear it
bits : 3 - 3 (1 bit)
access : read-write

SMART_ERASEL_EN : It enable Low 256KB Flash Smart erase flow; When smart erase is done, hardware automatically clear it
bits : 4 - 4 (1 bit)
access : read-write

SMART_ERASEH_EN : It enable High 256KB Flash Smart erase flow; When smart erase is done, hardware automatically clear it
bits : 5 - 5 (1 bit)
access : read-write

MAX_WRITE : When smart program is used, this is the maximum retry number for one write operation.
bits : 8 - 11 (4 bit)
access : read-write

MAX_ERASE : When smart erase is used, this is the maximum retry number for one erase operation.
bits : 12 - 17 (6 bit)
access : read-write


INTEN

interrupt enable register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTEN INTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AHBL_INTEN LOCKL_INTEN ERASEL_INTEN WRITEL_INTEN WRBUFL_INTEN AHBH_INTEN LOCKH_INTEN ERASEH_INTEN WRITEH_INTEN WRBUFH_INTEN FLASH_INTEN

AHBL_INTEN : low 256K flash AHB error interrupt enable
bits : 0 - 0 (1 bit)
access : read-write

LOCKL_INTEN : low 256K flash lock error interrupt enable
bits : 1 - 1 (1 bit)
access : read-write

ERASEL_INTEN : low 256K flash erase status interrupt enable
bits : 2 - 2 (1 bit)
access : read-write

WRITEL_INTEN : low 256K flash write status interrupt enable
bits : 3 - 3 (1 bit)
access : read-write

WRBUFL_INTEN : low 256K flash write buffer status interrupt enable
bits : 4 - 4 (1 bit)
access : read-write

AHBH_INTEN : high 256K flash AHB error interrupt enable
bits : 8 - 8 (1 bit)
access : read-write

LOCKH_INTEN : high 256K flash lock error interrupt enable
bits : 9 - 9 (1 bit)
access : read-write

ERASEH_INTEN : high 256K flash erase status interrupt enable
bits : 10 - 10 (1 bit)
access : read-write

WRITEH_INTEN : high 256K flash write status interrupt enable
bits : 11 - 11 (1 bit)
access : read-write

WRBUFH_INTEN : high 256K flash write buffer status interrupt enable
bits : 12 - 12 (1 bit)
access : read-write

FLASH_INTEN : flash total interrupt enable
bits : 31 - 31 (1 bit)
access : read-write


INT_STAT

interrupt status register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INT_STAT INT_STAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AHBL_INT LOCKL_INT ERASEL_INT WRITEL_INT WRBUFL_INT WRITE_FAIL_L_INT ERASE_FAIL_L_INT AHBH_INT LOCKH_INT ERASEH_INT WRITEH_INT WRBUFH_INT WRITE_FAIL_H_INT ERASE_FAIL_H_INT

AHBL_INT : It is low 256KB Flash AHB error interrupt stat. 1 indicates AHB operation error AHB error include: Write/read unmapped space; AHB align rules violation; Byte/half-word Flash write operation;
bits : 0 - 0 (1 bit)
access : read-write

LOCKL_INT : It is low 256KB Flash Lock page be accessed interrupt status
bits : 1 - 1 (1 bit)
access : read-write

ERASEL_INT : It is low 256KB Erase operation done interrupt status If erase is used, it indicates one erase is done.
bits : 2 - 2 (1 bit)
access : read-write

WRITEL_INT : It is low 256KB write operation done interrupt status If write is used, it indicates one program is done.
bits : 3 - 3 (1 bit)
access : read-write

WRBUFL_INT : It is low 256KB Write Buffer empty interrupt status 0 = write buffer is not empty 1 = write buffer is empty It is auto cleared when write buffer is written. It is enabled only when PRGML_EN is enabled and write buffer is empty
bits : 4 - 4 (1 bit)
access : read-write

WRITE_FAIL_L_INT : When smart write of low 256KB Flash is enable, 0 = Smart write is successful, 1 = Smart write is fail.
bits : 5 - 5 (1 bit)
access : read-write

ERASE_FAIL_L_INT : When smart erase of low 256KB Flash is enable, 0 = Smart erase is successful, 1 = Smart erase is fail.
bits : 6 - 6 (1 bit)
access : read-write

AHBH_INT : it is high 256KB Flash AHB error interrupt stat 1 indicates AHB operation error AHB error include: Write/read unmapped space; AHB align rules violation; Byte/half-word Flash write operation;
bits : 8 - 8 (1 bit)
access : read-write

LOCKH_INT : it is high 256KB Flash Lock page be accessed interrupt status
bits : 9 - 9 (1 bit)
access : read-write

ERASEH_INT : it is high 256KB Flash Erase operation done interrupt status If erase is used, it indicates one erase is done.
bits : 10 - 10 (1 bit)
access : read-write

WRITEH_INT : it is high 256KB Flash write operation done interrupt status If write is used, it indicates one program is done.
bits : 11 - 11 (1 bit)
access : read-write

WRBUFH_INT : it is high 256KB Flash Write Buffer empty interrupt status 0 = write buffer is not empty 1 = write buffer is empty It is auto cleared when write buffer is written. It is enabled only when PRGMH_EN is enabled and write buffer is empty
bits : 12 - 12 (1 bit)
access : read-write

WRITE_FAIL_H_INT : When smart write of high 256KB Flash is enable, 0 = Smart write is successful, 1 = Smart write is fail.
bits : 13 - 13 (1 bit)
access : read-write

ERASE_FAIL_H_INT : When smart erase of high 256KB Flash is enable, 0 = Smart erase is successful, 1 = Smart erase is fail.
bits : 14 - 14 (1 bit)
access : read-write


INTCLR

interrupt clear register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTCLR INTCLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AHBL_INTCLR LOCKL_INTCLR ERASEL_INTCLR WRITEL_INTCLR AHBH_INTCLR LOCKH_INTCLR ERASEH_INTCLR WRITEH_INTCLR

AHBL_INTCLR : low 256K flash AHB error interrupt clear
bits : 0 - 0 (1 bit)
access : read-write

LOCKL_INTCLR : low 256K flash lock error interrupt clear
bits : 1 - 1 (1 bit)
access : read-write

ERASEL_INTCLR : low 256K flash erase status interrupt clear
bits : 2 - 2 (1 bit)
access : read-write

WRITEL_INTCLR : low 256K flash write status interrupt clear
bits : 3 - 3 (1 bit)
access : read-write

AHBH_INTCLR : high 256K flash AHB error interrupt clear
bits : 8 - 8 (1 bit)
access : read-write

LOCKH_INTCLR : high 256K flash lock error interrupt clear
bits : 9 - 9 (1 bit)
access : read-write

ERASEH_INTCLR : high 256K flash erase status interrupt clear
bits : 10 - 10 (1 bit)
access : read-write

WRITEH_INTCLR : high 256K flash write status interrupt clear
bits : 11 - 11 (1 bit)
access : read-write


LOCK_STAT0

lock control register 0
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

LOCK_STAT0 LOCK_STAT0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PAGE_LOCK0

PAGE_LOCK0 : Low 256K flash main memory page 0-31 write and erase lock status
bits : 0 - 31 (32 bit)
access : read-only


LOCK_STAT1

no description available
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

LOCK_STAT1 LOCK_STAT1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PAGE_LOCK1

PAGE_LOCK1 : Low 256K flash main memory page 32-63 write and erase lock status
bits : 0 - 31 (32 bit)
access : read-only


LOCK_STAT2

no description available
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

LOCK_STAT2 LOCK_STAT2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PAGE_LOCK2

PAGE_LOCK2 : Low 256K flash main memory page 64-95 write and erase lock status
bits : 0 - 31 (32 bit)
access : read-only


LOCK_STAT3

no description available
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

LOCK_STAT3 LOCK_STAT3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PAGE_LOCK3

PAGE_LOCK3 : Low 256K flash main memory page 96-127 write and erase lock status
bits : 0 - 31 (32 bit)
access : read-only


LOCK_STAT4

no description available
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

LOCK_STAT4 LOCK_STAT4 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PAGE_LOCK4

PAGE_LOCK4 : high 256K flash main memory page 0-31 write and erase lock status
bits : 0 - 31 (32 bit)
access : read-only


LOCK_STAT5

no description available
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

LOCK_STAT5 LOCK_STAT5 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PAGE_LOCK5

PAGE_LOCK5 : high 256K flash main memory page 32-63 write and erase lock status
bits : 0 - 31 (32 bit)
access : read-only


LOCK_STAT6

no description available
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

LOCK_STAT6 LOCK_STAT6 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PAGE_LOCK6

PAGE_LOCK6 : high 256K flash main memory page 64-95 write and erase lock status
bits : 0 - 31 (32 bit)
access : read-only


LOCK_STAT7

no description available
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

LOCK_STAT7 LOCK_STAT7 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PAGE_LOCK7

PAGE_LOCK7 : high 256K flash main memory page 96-127 write and erase lock status
bits : 0 - 31 (32 bit)
access : read-only


ERASE_CTRL

flash erase control register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ERASE_CTRL ERASE_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PAGE_IDXL PAGE_IDXH HALF_ERASEL_EN HALF_ERASEH_EN PAGE_ERASEL_EN PAGE_ERASEH_EN

PAGE_IDXL : Low 256KB page erase index
bits : 0 - 6 (7 bit)
access : read-write

PAGE_IDXH : High 256KB page erase index
bits : 8 - 14 (7 bit)
access : read-write

HALF_ERASEL_EN : Write '1' to Enable Mass Erase Low 256KB Flash; Write '0' is inactive. This bit is set by software and reset at the end of low 256KB flash mass erase operation by hardware.
bits : 28 - 28 (1 bit)
access : read-write

HALF_ERASEH_EN : Write '1' to Enable Mass Erase High 256KB Flash; Write '0' is inactive. This bit is set by software and reset at the end of high 256KB flash mass erase operation by hardware.
bits : 29 - 29 (1 bit)
access : read-write

PAGE_ERASEL_EN : Low 256KB block page erase enable. This bit initiates a page erase operation when set. This bit is set by software and reset at the end of page erase operation by hardware.
bits : 30 - 30 (1 bit)
access : read-write

PAGE_ERASEH_EN : High 256KB block page erase enable. This bit initiates a page erase operation when set. This bit is set by software and reset at the end of page erase operation by hardware.
bits : 31 - 31 (1 bit)
access : read-write


LOCK_STAT8

no description available
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LOCK_STAT8 LOCK_STAT8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MASS_ERASE_LOCK FSH_PROTECT MEM_PROTECT

MASS_ERASE_LOCK : Mass erase operation lock status 0 : Mass erase operation is locked 1 : Mass erase operation is unlocked
bits : 0 - 0 (1 bit)
access : read-write

FSH_PROTECT : SWD flash protection status 0 : flash is unprotected 1 : flash is protected
bits : 1 - 1 (1 bit)
access : read-write

MEM_PROTECT : SWD memory protection status 0 : Memory is unprotected 1 : Memory is protected
bits : 2 - 2 (1 bit)
access : read-write


STATUS1

no description available
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STATUS1 STATUS1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FSH_ERA_BUSY_L FSH_WR_BUSY_L DBG_ERA_DONE_L FSH_ERA_BUSY_H FSH_WR_BUSY_H DBG_ERA_DONE_H INI_RD_DONE FSH_STA RESERVED

FSH_ERA_BUSY_L : flash block 0 erase operation status 0 : no flash block 0 erase operation in progress. 1 : flash block 0 erase operation is in progress.
bits : 9 - 9 (1 bit)
access : read-only

FSH_WR_BUSY_L : flash block 0 write operation status: 0 : no flash block 0 write operation in progress. 1 : flash block 0 write operation is in progress.
bits : 10 - 10 (1 bit)
access : read-only

DBG_ERA_DONE_L : A flash block 0 debug initiated smart mass erase status. 0 : no debug port initiated flash block 0 smart mass erase operation in progress. 1 : debug port initiated flash block 0 smart mass erase operation in progress.
bits : 11 - 11 (1 bit)
access : read-only

FSH_ERA_BUSY_H : flash block 1 erase operation status 0 : no flash block 1 erase operation in progress. 1 : flash block 1 erase operation is in progress.
bits : 12 - 12 (1 bit)
access : read-only

FSH_WR_BUSY_H : flash block 1 write operation status: 0 : no flash block 1 write operation in progress. 1 : flash block 1 write operation is in progress.
bits : 13 - 13 (1 bit)
access : read-only

DBG_ERA_DONE_H : A flash block 1 debug initiated smart mass erase status. 0 : no debug port initiated flash block 1 smart mass erase operation in progress. 1 : debug port initiated flash block 1 smart mass erase operation in progress.
bits : 14 - 14 (1 bit)
access : read-only

INI_RD_DONE : flash initial read done.
bits : 15 - 15 (1 bit)
access : read-only

FSH_STA : when 0 means data information is 0x55AA.
bits : 26 - 26 (1 bit)
access : read-only

RESERVED : reserved
bits : 27 - 31 (5 bit)
access : read-only


ERR_INFOL1

no description available
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ERR_INFOL1 ERR_INFOL1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WR_FAILEDL_ADDR SMART_FAILL_CTR

WR_FAILEDL_ADDR : When a flash block 0 smart write fails, the address is stored in this bit filed
bits : 0 - 17 (18 bit)
access : read-only

SMART_FAILL_CTR : The amount of fails during a smart write or smart erase is stored in this bit field
bits : 18 - 23 (6 bit)
access : read-only


ERR_INFOL2

no description available
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ERR_INFOL2 ERR_INFOL2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WR_FAILEDL_DATA

WR_FAILEDL_DATA : When a flash block 0 smart write fails, the data is stored in this bit field
bits : 0 - 31 (32 bit)
access : read-only


ERR_INFOL3

no description available
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ERR_INFOL3 ERR_INFOL3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERA_FAILEDL_INFO

ERA_FAILEDL_INFO : When a smart erase on flash block 0 fails, the address is stored in this bit field
bits : 0 - 17 (18 bit)
access : read-only


ERR_INFOH1

no description available
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ERR_INFOH1 ERR_INFOH1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WR_FAILEDH_ADDR SMART_FAILH_CTR

WR_FAILEDH_ADDR : When a flash block 1 smart write fails, the address is stored in this bit field
bits : 0 - 17 (18 bit)
access : read-only

SMART_FAILH_CTR : The amount of fails during a msart write or smart erase is stored int his bit field
bits : 18 - 23 (6 bit)
access : read-only


ERR_INFOH2

no description available
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ERR_INFOH2 ERR_INFOH2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WR_FAILEDH_DATA

WR_FAILEDH_DATA : When a flash block 1 smart write fails, the data is stored in this bit field
bits : 0 - 31 (32 bit)
access : read-only


ERR_INFOH3

no description available
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ERR_INFOH3 ERR_INFOH3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERA_FAILEDH_INFO

ERA_FAILEDH_INFO : when a smart erase on flash block 1 fails, the address is stored in this bit field
bits : 0 - 17 (18 bit)
access : read-only


ERASE_TIME

flash erase time setting register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ERASE_TIME ERASE_TIME read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERASE_TIME_BASE

ERASE_TIME_BASE : Erase time, which is used to control Terase, Tme and Tsme. An 8MHz clock is to count the erase time. The maximum time of erase is 100ms. Default value is 640000 cycles in 8 MHz, that's 80 ms. User should set a pessimistic value to avoid possible error in erase operation.
bits : 0 - 19 (20 bit)
access : read-write


DEBUG_PASSWORD

no description available
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEBUG_PASSWORD DEBUG_PASSWORD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DEBUG_PASSWORD

DEBUG_PASSWORD : An SWD initiated smart mass erase operation will only be issued if this register is programmed with the value 0xCA1E093F.
bits : 0 - 31 (32 bit)
access : read-write


ERASE_PASSWORD

no description available
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ERASE_PASSWORD ERASE_PASSWORD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERASE_PASSWORD

ERASE_PASSWORD : When this register is programmed with the value 0xCA1E093F, a FW initiated mass erase or page erase operation will bypass the current lock and protection scheme.
bits : 0 - 31 (32 bit)
access : read-write


TIME_CTRL

flash operation time setting register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIME_CTRL TIME_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRGM_CYCLE TIME_BASE

PRGM_CYCLE : Time base of some flash timing parameters, which represents 2 us. Default value is 64 cycles in 32 MHz (ahb clock). It is used in write and erase operations.
bits : 0 - 11 (12 bit)
access : read-write

TIME_BASE : Max write operation times in one program, which are used to control Terase and Tme. User should set a pessimistic value to avoid possible error in erase/page erase operation. When user do write operation: It is used to limit allowed write numbers. (Max 21 ms-Tnvs-Tpgs-Tpgh-Tnvh)/18us = 1167 This register is only used when common write.
bits : 12 - 19 (8 bit)
access : read-write



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