DEVCMDSTAT

LPM

EPSKIP

EPINUSE

EPBUFCFG

INTSTAT

INTEN

INTSETSTAT

EPTOGGLE

INFO

EPLISTSTART

DATABUFSTART

DEV_ADDR : USB device address. After bus reset, the address is reset to 0x00. If the enable bit is set, the device will respond on packets for function address DEV_ADDR. When receiving a SetAddress Control Request from the USB host, software must program the new address before completing the status phase of the SetAddress Control Request.
bits : 0 - 6 (7 bit)
access : read-write

DEV_EN : USB device enable. If this bit is set, the HW will start responding on packets for function address DEV_ADDR.
bits : 7 - 7 (1 bit)
access : read-write

SETUP : SETUP token received. If a SETUP token is received and acknowledged by the device, this bit is set. As long as this bit is set all received IN and OUT tokens will be NAKed by HW. SW must clear this bit by writing a one. If this bit is zero, HW will handle the tokens to the CTRL EP0 as indicated by the CTRL EP0 IN and OUT data information programmed by SW.
bits : 8 - 8 (1 bit)
access : read-write

FORCE_NEEDCLK : Forces the NEEDCLK output to always be on:
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LPM_SUP : LPM Supported:
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTONNAK_AO : Interrupt on NAK for interrupt and bulk OUT EP
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTONNAK_AI : Interrupt on NAK for interrupt and bulk IN EP
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTONNAK_CO : Interrupt on NAK for control OUT EP
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTONNAK_CI : Interrupt on NAK for control IN EP
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DCON : Device status - connect. The connect bit must be set by SW to indicate that the device must signal a connect. The pull-up resistor on USB_DP will be enabled when this bit is set and the VBUSDEBOUNCED bit is one.
bits : 16 - 16 (1 bit)
access : read-write

DSUS : Device status - suspend. The suspend bit indicates the current suspend state. It is set to 1 when the device hasn'-t seen any activity on its upstream port for more than 3 milliseconds. It is reset to 0 on any activity. When the device is suspended (Suspend bit DSUS = 1) and the software writes a 0 to it, the device will generate a remote wake-up. This will only happen when the device is connected (Connect bit = 1). When the device is not connected or not suspended, a writing a 0 has no effect. Writing a 1 never has an effect.
bits : 17 - 17 (1 bit)
access : read-write

LPM_SUS : Device status - LPM Suspend. This bit represents the current LPM suspend state. It is set to 1 by HW when the device has acknowledged the LPM request from the USB host and the Token Retry Time of 10 ms has elapsed. When the device is in the LPM suspended state (LPM suspend bit = 1) and the software writes a zero to this bit, the device will generate a remote walk-up. Software can only write a zero to this bit when the LPM_REWP bit is set to 1. HW resets this bit when it receives a host initiated resume. HW only updates the LPM_SUS bit when the LPM_SUPP bit is equal to one.
bits : 19 - 19 (1 bit)
access : read-write

LPM_REWP : LPM Remote Wake-up Enabled by USB host. HW sets this bit to one when the bRemoteWake bit in the LPM extended token is set to 1. HW will reset this bit to 0 when it receives the host initiated LPM resume, when a remote wake-up is sent by the device or when a USB bus reset is received. Software can use this bit to check if the remote wake-up feature is enabled by the host for the LPM transaction.
bits : 20 - 20 (1 bit)
access : read-only

DCON_C : Device status - connect change. The Connect Change bit is set when the device'-s pull-up resistor is disconnected because VBus disappeared. The bit is reset by writing a one to it.
bits : 24 - 24 (1 bit)
access : read-write

DSUS_C : Device status - suspend change. The suspend change bit is set to 1 when the suspend bit toggles. The suspend bit can toggle because: - The device goes in the suspended state - The device is disconnected - The device receives resume signaling on its upstream port. The bit is reset by writing a one to it.
bits : 25 - 25 (1 bit)
access : read-write

DRES_C : Device status - reset change. This bit is set when the device received a bus reset. On a bus reset the device will automatically go to the default state (unconfigured and responding to address 0). The bit is reset by writing a one to it.
bits : 26 - 26 (1 bit)
access : read-write

VBUSDEBOUNCED : This bit indicates if Vbus is detected or not. The bit raises immediately when Vbus becomes high. It drops to zero if Vbus is low for at least 3 ms. If this bit is high and the DCon bit is set, the HW will enable the pull-up resistor to signal a connect.
bits : 28 - 28 (1 bit)
access : read-only

HIRD_HW : Host Initiated Resume Duration - HW. This is the HIRD value from the last received LPM token
bits : 0 - 3 (4 bit)
access : read-only

HIRD_SW : Host Initiated Resume Duration - SW. This is the time duration required by the USB device system to come out of LPM initiated suspend after receiving the host initiated LPM resume.
bits : 4 - 7 (4 bit)
access : read-write

DATA_PENDING : As long as this bit is set to one and LPM supported bit is set to one, HW will return a NYET handshake on every LPM token it receives. If LPM supported bit is set to one and this bit is zero, HW will return an ACK handshake on every LPM token it receives. If SW has still data pending and LPM is supported, it must set this bit to 1.
bits : 8 - 8 (1 bit)
access : read-write

SKIP : Endpoint skip: Writing 1 to one of these bits, will indicate to HW that it must deactivate the buffer assigned to this endpoint and return control back to software. When HW has deactivated the endpoint, it will clear this bit, but it will not modify the EPINUSE bit. An interrupt will be generated when the Active bit goes from 1 to 0. Note: In case of double-buffering, HW will only clear the Active bit of the buffer indicated by the EPINUSE bit.
bits : 0 - 29 (30 bit)
access : read-write

BUF : Buffer in use: This register has one bit per physical endpoint. 0: HW is accessing buffer 0. 1: HW is accessing buffer 1.
bits : 2 - 9 (8 bit)
access : read-write

BUF_SB : Buffer usage: This register has one bit per physical endpoint. 0: Single-buffer. 1: Double-buffer. If the bit is set to single-buffer (0), it will not toggle the corresponding EPINUSE bit when it clears the active bit. If the bit is set to double-buffer (1), HW will toggle the EPINUSE bit when it clears the Active bit for the buffer.
bits : 2 - 9 (8 bit)
access : read-write

EP0OUT : Interrupt status register bit for the Control EP0 OUT direction. This bit will be set if NBytes transitions to zero or the skip bit is set by software or a SETUP packet is successfully received for the control EP0. If the IntOnNAK_CO is set, this bit will also be set when a NAK is transmitted for the Control EP0 OUT direction. Software can clear this bit by writing a one to it.
bits : 0 - 0 (1 bit)
access : read-write

EP0IN : Interrupt status register bit for the Control EP0 IN direction. This bit will be set if NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_CI is set, this bit will also be set when a NAK is transmitted for the Control EP0 IN direction. Software can clear this bit by writing a one to it.
bits : 1 - 1 (1 bit)
access : read-write

EP1OUT : Interrupt status register bit for the EP1 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP1 OUT direction. Software can clear this bit by writing a one to it.
bits : 2 - 2 (1 bit)
access : read-write

EP1IN : Interrupt status register bit for the EP1 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP1 IN direction. Software can clear this bit by writing a one to it.
bits : 3 - 3 (1 bit)
access : read-write

EP2OUT : Interrupt status register bit for the EP2 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP2 OUT direction. Software can clear this bit by writing a one to it.
bits : 4 - 4 (1 bit)
access : read-write

EP2IN : Interrupt status register bit for the EP2 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP2 IN direction. Software can clear this bit by writing a one to it.
bits : 5 - 5 (1 bit)
access : read-write

EP3OUT : Interrupt status register bit for the EP3 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP3 OUT direction. Software can clear this bit by writing a one to it.
bits : 6 - 6 (1 bit)
access : read-write

EP3IN : Interrupt status register bit for the EP3 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP3 IN direction. Software can clear this bit by writing a one to it.
bits : 7 - 7 (1 bit)
access : read-write

EP4OUT : Interrupt status register bit for the EP4 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP4 OUT direction. Software can clear this bit by writing a one to it.
bits : 8 - 8 (1 bit)
access : read-write

EP4IN : Interrupt status register bit for the EP4 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP4 IN direction. Software can clear this bit by writing a one to it.
bits : 9 - 9 (1 bit)
access : read-write

EP5OUT : Interrupt status register bit for the EP5 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP5 OUT direction. Software can clear this bit by writing a one to it.
bits : 10 - 10 (1 bit)
access : read-write

EP5IN : Interrupt status register bit for the EP5 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP5 IN direction. Software can clear this bit by writing a one to it.
bits : 11 - 11 (1 bit)
access : read-write

EP6OUT : Interrupt status register bit for the EP6 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP6 OUT direction. Software can clear this bit by writing a one to it.
bits : 12 - 12 (1 bit)
access : read-write

EP6IN : Interrupt status register bit for the EP6 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP6 IN direction. Software can clear this bit by writing a one to it.
bits : 13 - 13 (1 bit)
access : read-write

EP7OUT : Interrupt status register bit for the EP7 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP7 OUT direction. Software can clear this bit by writing a one to it.
bits : 14 - 14 (1 bit)
access : read-write

EP7IN : Interrupt status register bit for the EP7 IN direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP7 IN direction. Software can clear this bit by writing a one to it.
bits : 15 - 15 (1 bit)
access : read-write

FRAME_INT : Frame interrupt. This bit is set to one every millisecond when the VbusDebounced bit and the DCON bit are set. This bit can be used by software when handling isochronous endpoints. Software can clear this bit by writing a one to it.
bits : 30 - 30 (1 bit)
access : read-write

DEV_INT : Device status interrupt. This bit is set by HW when one of the bits in the Device Status Change register are set. Software can clear this bit by writing a one to it.
bits : 31 - 31 (1 bit)
access : read-write

EP_INT_EN : If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing bit.
bits : 0 - 15 (16 bit)
access : read-write

FRAME_INT_EN : If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing bit.
bits : 30 - 30 (1 bit)
access : read-write

DEV_INT_EN : If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing bit.
bits : 31 - 31 (1 bit)
access : read-write

EP_SET_INT : If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. When this register is read, the same value as the USB interrupt status register is returned.
bits : 0 - 15 (16 bit)
access : read-write

FRAME_SET_INT : If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. When this register is read, the same value as the USB interrupt status register is returned.
bits : 30 - 30 (1 bit)
access : read-write

DEV_SET_INT : If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. When this register is read, the same value as the USB interrupt status register is returned.
bits : 31 - 31 (1 bit)
access : read-write

TOGGLE : Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding endpoint.
bits : 0 - 15 (16 bit)
access : read-only

FRAME_NR : Frame number. This contains the frame number of the last successfully received SOF. In case no SOF was received by the device at the beginning of a frame, the frame number returned is that of the last successfully received SOF. In case the SOF frame number contained a CRC error, the frame number returned will be the corrupted frame number as received by the device.
bits : 0 - 10 (11 bit)
access : read-only

ERR_CODE : The error code which last occurred:
bits : 11 - 14 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

EP_LIST : Start address of the USB EP Command/Status List.
bits : 8 - 31 (24 bit)
access : read-write

DA_BUF : Start address of the buffer pointer page where all endpoint data buffers are located.
bits : 22 - 31 (10 bit)
access : read-write