\n
address_offset : 0x0 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x4 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x8 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xD0 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xC0 Bytes (0x0)
size : 0x5 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xD4 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xD8 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
SRAM Parity Error Operation After Detection Register
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OAD : Operation after Detection
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#1 : 1
Reset
#0 : 0
Non maskable interrupt.
End of enumeration elements list.
SRAM Protection Register
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRAMPRCR : Register Write Control
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable writes to protected registers
#1 : 1
Enable writes to protected registers.
End of enumeration elements list.
KW : Write Key Code
bits : 1 - 6 (6 bit)
access : write-only
Enumeration:
#1111000 : 1111000
Writing to the RAMPRCR bit is valid, when the KEY bits are written 1111000b.
End of enumeration elements list.
RAM Wait State Control Register
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECCRAMWRWTEN : ECCRAM Write Wait Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Not add wait state in write access cycle to SRAM0 (ECC area)
#1 : 1
Add wait state in write access cycle to SRAM0 (ECC area)
End of enumeration elements list.
ECCRAMRDWTEN : ECCRAM Read wait enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : 0
Not add wait state in read access cycle to SRAM0 (ECC area)
#1 : 1
Add wait state in read access cycle to SRAM0 (ECC area)
End of enumeration elements list.
SRAM0WTEN : SRAM0 Wait Enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Not add wait state in read access cycle to SRAM0
#1 : 1
Add wait state in read access cycle to SRAM0
End of enumeration elements list.
SRAM1WTEN : SRAM1 Wait Enable
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : 0
Not add wait state in read access cycle to SRAM1
#1 : 1
Add wait state in read access cycle to SRAM1
End of enumeration elements list.
SRAMHSWTEN : SRAMHS Wait Enable
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : 0
Not add wait state in read access cycle to SRAMHS
#1 : 1
Add wait state in read access cycle to SRAMHS
End of enumeration elements list.
ECC Operating Mode Control Register
address_offset : 0xC0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECCMOD : ECC Operating Mode Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
Disable ECC function
#01 : 01
Setting prohibited
#10 : 10
Enable ECC function without error checking
#11 : 11
Enable ECC function with error checking
End of enumeration elements list.
ECC 2-Bit Error Status Register
address_offset : 0xC1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC2ERR : ECC 2-Bit Error Status
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
No 2-bit ECC error occurred
#1 : 1
2-bit ECC error occurred.
End of enumeration elements list.
ECC 1-Bit Error Information Update Enable Register
address_offset : 0xC2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
E1STSEN : ECC 1-Bit Error Information Update Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disables updating of the 1-bit ECC error information.
#1 : 1
Enables updating of the 1-bit ECC error information.
End of enumeration elements list.
ECC 1-Bit Error Status Register
address_offset : 0xC3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC1ERR : ECC 1-Bit Error Status
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
No 1-bit ECC error occurred
#1 : 1
1-bit ECC error occurred
End of enumeration elements list.
ECC Protection Register
address_offset : 0xC4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECCPRCR : Register Write Control
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable writes to the protected registers
#1 : 1
Enable writes to the protected registers
End of enumeration elements list.
KW : Write Key Code
bits : 1 - 6 (6 bit)
access : write-only
Enumeration:
#1111000 : 1111000
Writing to the ECCRAMPRCR bit is valid, when the KEY bits are written 1111000b.
End of enumeration elements list.
ECC Protection Register 2
address_offset : 0xD0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECCPRCR2 : Register Write Control
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Disable writes to the protected registers
#1 : 1
Enable writes to the protected registers.
End of enumeration elements list.
KW2 : Write Key Code
bits : 1 - 6 (6 bit)
access : write-only
Enumeration:
#1111000 : 1111000
These bits enable or disable writes to the ECCPRCR2 bit..
End of enumeration elements list.
ECC Test Control Register
address_offset : 0xD4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSTBYP : ECC Bypass Select
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
ECC bypass disabled.
#1 : 1
ECC bypass enabled.
End of enumeration elements list.
SRAM ECC Error Operation After Detection Register
address_offset : 0xD8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OAD : Operation after Detection
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : 0
Non-maskable interrupt
#1 : 1
Reset
End of enumeration elements list.
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