\n
address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
No Description
address_offset : 0x0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IPVERSION : IP Version
bits : 0 - 31 (32 bit)
access : read-only
No Description
address_offset : 0x10 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
INITIALIZE : Initialize CRC
bits : 0 - 0 (1 bit)
access : write-only
No Description
address_offset : 0x14 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
INPUTDATA : Input Data
bits : 0 - 15 (16 bit)
access : write-only
No Description
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INIT : CRC Initialization Value
bits : 0 - 31 (32 bit)
access : read-write
No Description
address_offset : 0x1C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : CRC Data Register
bits : 0 - 31 (32 bit)
access : read-only
No Description
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POLY : CRC Polynomial Value
bits : 0 - 31 (32 bit)
access : read-write
No Description
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Enable peripheral clock to this module
bits : 0 - 0 (1 bit)
access : read-write
No Description
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INPUTINV : Input Invert
bits : 0 - 0 (1 bit)
access : read-write
OUTPUTINV : Output Invert
bits : 1 - 1 (1 bit)
access : read-write
CRCWIDTH : None
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0 : CRCWIDTH8
8 bit (1 Byte) CRC code
1 : CRCWIDTH16
16 bit (2 Bytes) CRC code
2 : CRCWIDTH24
24 bit (3 Bytes) CRC code
3 : CRCWIDTH32
32 bit (4 Bytes) CRC code
End of enumeration elements list.
INPUTBITORDER : CRC input bit ordering setting
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : LSBFIRST
The least significant data bit is first input to the CRC generator.
1 : MSBFIRST
The most significant data bit is first input to the CRC generator.
End of enumeration elements list.
BYTEREVERSE : Reverse CRC byte ordering over air
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NORMAL
The least significant byte of the CRC register is transferred first over air via the Frame Controller.
1 : REVERSED
The most significant byte of the CRC register is transferred first over air via the Frame Controller.
End of enumeration elements list.
BITREVERSE : Reverse CRC bit ordering over air
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : NORMAL
The bit ordering of CRC data is the same as defined by the BITORDER field in the Frame Controller.
1 : REVERSED
The bit ordering of CRC data is the opposite as defined by the BITORDER field in the Frame Controller.
End of enumeration elements list.
BITSPERWORD : Number of bits per input word
bits : 8 - 11 (4 bit)
access : read-write
PADCRCINPUT : Pad CRC input data
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : X0
No zero-padding of CRC input data is applied
1 : X1
CRC input data is zero-padded, such that the number of bytes over which the CRC value is calculated at least equals the length of the calculated CRC value.
End of enumeration elements list.
No Description
address_offset : 0xC Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BUSY : CRC Running
bits : 0 - 0 (1 bit)
access : read-only
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