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JPEG

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

JPEG_CONFR0 (CONFR0)

JPEG_CONFR4 (CONFR4)

QMEM2_12

QMEM2_13

QMEM2_14

QMEM2_15

QMEM3_0

QMEM3_1

QMEM3_2

QMEM3_3

QMEM3_4

QMEM3_5

QMEM3_6

QMEM3_7

QMEM3_8

QMEM3_9

QMEM3_10

QMEM3_11

JPEG_CONFR5 (CONFR5)

QMEM3_12

QMEM3_13

QMEM3_14

QMEM3_15

HUFFMIN_0

HUFFMIN_1

HUFFMIN_2

HUFFMIN_3

HUFFMIN_4

HUFFMIN_5

HUFFMIN_6

HUFFMIN_7

HUFFMIN_8

HUFFMIN_9

HUFFMIN_10

HUFFMIN_11

JPEG_CONFR6 (CONFR6)

HUFFMIN_12

HUFFMIN_13

HUFFMIN_14

HUFFMIN_15

HUFFBASE0

HUFFBASE1

HUFFBASE2

HUFFBASE3

HUFFBASE4

HUFFBASE5

HUFFBASE6

HUFFBASE7

HUFFBASE8

HUFFBASE9

HUFFBASE10

HUFFBASE11

JPEG_CONFR7 (CONFR7)

HUFFBASE12

HUFFBASE13

HUFFBASE14

HUFFBASE15

HUFFBASE16

HUFFBASE17

HUFFBASE18

HUFFBASE19

HUFFBASE20

HUFFBASE21

HUFFBASE22

HUFFBASE23

HUFFBASE24

HUFFBASE25

HUFFBASE26

HUFFBASE27

HUFFBASE28

HUFFBASE29

HUFFBASE30

HUFFBASE31

HUFFSYMB0

HUFFSYMB1

HUFFSYMB2

HUFFSYMB3

HUFFSYMB4

HUFFSYMB5

HUFFSYMB6

HUFFSYMB7

HUFFSYMB8

HUFFSYMB9

HUFFSYMB10

HUFFSYMB11

HUFFSYMB12

HUFFSYMB13

HUFFSYMB14

HUFFSYMB15

HUFFSYMB16

HUFFSYMB17

HUFFSYMB18

HUFFSYMB19

HUFFSYMB20

HUFFSYMB21

HUFFSYMB22

HUFFSYMB23

HUFFSYMB24

HUFFSYMB25

HUFFSYMB26

HUFFSYMB27

HUFFSYMB28

HUFFSYMB29

HUFFSYMB30

HUFFSYMB31

HUFFSYMB32

HUFFSYMB33

HUFFSYMB34

HUFFSYMB35

HUFFSYMB36

HUFFSYMB37

HUFFSYMB38

HUFFSYMB39

HUFFSYMB40

HUFFSYMB41

HUFFSYMB42

HUFFSYMB43

HUFFSYMB44

HUFFSYMB45

HUFFSYMB46

HUFFSYMB47

HUFFSYMB48

HUFFSYMB49

HUFFSYMB50

HUFFSYMB51

HUFFSYMB52

HUFFSYMB53

HUFFSYMB54

HUFFSYMB55

HUFFSYMB56

HUFFSYMB57

HUFFSYMB58

HUFFSYMB59

JPEG_CR (CR)

HUFFSYMB60

HUFFSYMB61

HUFFSYMB62

HUFFSYMB63

HUFFSYMB64

HUFFSYMB65

HUFFSYMB66

HUFFSYMB67

HUFFSYMB68

HUFFSYMB69

HUFFSYMB70

HUFFSYMB71

HUFFSYMB72

HUFFSYMB73

HUFFSYMB74

HUFFSYMB75

JPEG_SR (SR)

HUFFSYMB76

HUFFSYMB77

HUFFSYMB78

HUFFSYMB79

HUFFSYMB80

HUFFSYMB81

HUFFSYMB82

HUFFSYMB83

DHTMEM0

DHTMEM2

DHTMEM3

DHTMEM4

DHTMEM5

DHTMEM6

DHTMEM7

DHTMEM8

JPEG_CFR (CFR)

DHTMEM9

DHTMEM10

DHTMEM11

DHTMEM12

DHTMEM13

DHTMEM14

DHTMEM15

DHTMEM16

DHTMEM17

DHTMEM18

DHTMEM19

DHTMEM20

DHTMEM21

DHTMEM22

DHTMEM23

DHTMEM24

DHTMEM25

DHTMEM26

DHTMEM27

DHTMEM28

DHTMEM29

DHTMEM30

DHTMEM31

DHTMEM32

DHTMEM33

DHTMEM34

DHTMEM35

DHTMEM36

DHTMEM37

DHTMEM38

DHTMEM39

DHTMEM40

JPEG_CONFR1 (CONFR1)

JPEG_DIR (DIR)

DHTMEM41

DHTMEM42

DHTMEM43

DHTMEM44

DHTMEM45

DHTMEM46

DHTMEM47

DHTMEM48

DHTMEM49

DHTMEM50

DHTMEM51

DHTMEM52

DHTMEM53

DHTMEM54

DHTMEM55

DHTMEM56

JPEG_DOR (DOR)

DHTMEM57

DHTMEM58

DHTMEM59

DHTMEM60

DHTMEM61

DHTMEM62

DHTMEM63

DHTMEM64

DHTMEM65

DHTMEM66

DHTMEM67

DHTMEM68

DHTMEM69

DHTMEM70

DHTMEM71

DHTMEM72

DHTMEM73

DHTMEM74

DHTMEM75

DHTMEM76

DHTMEM77

DHTMEM78

DHTMEM79

DHTMEM80

DHTMEM81

DHTMEM82

DHTMEM83

DHTMEM84

DHTMEM85

DHTMEM86

DHTMEM87

DHTMEM88

DHTMEM89

DHTMEM90

DHTMEM91

DHTMEM92

DHTMEM93

DHTMEM94

DHTMEM95

DHTMEM96

DHTMEM97

DHTMEM98

DHTMEM99

DHTMEM100

DHTMEM101

DHTMEM102

DHTMEM103

QMEM0_0

HUFFENC_AC0_0

HUFFENC_AC0_1

HUFFENC_AC0_2

HUFFENC_AC0_3

HUFFENC_AC0_4

HUFFENC_AC0_5

HUFFENC_AC0_6

HUFFENC_AC0_7

HUFFENC_AC0_8

HUFFENC_AC0_9

HUFFENC_AC0_10

HUFFENC_AC0_11

HUFFENC_AC0_12

HUFFENC_AC0_13

HUFFENC_AC0_14

HUFFENC_AC0_15

QMEM0_1

HUFFENC_AC0_16

HUFFENC_AC0_17

HUFFENC_AC0_18

HUFFENC_AC0_19

HUFFENC_AC0_20

HUFFENC_AC0_21

HUFFENC_AC0_22

HUFFENC_AC0_23

HUFFENC_AC0_24

HUFFENC_AC0_25

HUFFENC_AC0_26

HUFFENC_AC0_27

HUFFENC_AC0_28

HUFFENC_AC0_29

HUFFENC_AC0_30

HUFFENC_AC0_31

QMEM0_2

HUFFENC_AC0_32

HUFFENC_AC0_33

HUFFENC_AC0_34

HUFFENC_AC0_35

HUFFENC_AC0_36

HUFFENC_AC0_37

HUFFENC_AC0_38

HUFFENC_AC0_39

HUFFENC_AC0_40

HUFFENC_AC0_41

HUFFENC_AC0_42

HUFFENC_AC0_43

HUFFENC_AC0_44

HUFFENC_AC0_45

HUFFENC_AC0_46

HUFFENC_AC0_47

QMEM0_3

HUFFENC_AC0_48

HUFFENC_AC0_49

HUFFENC_AC0_50

HUFFENC_AC0_51

HUFFENC_AC0_52

HUFFENC_AC0_53

HUFFENC_AC0_54

HUFFENC_AC0_55

HUFFENC_AC0_56

HUFFENC_AC0_57

HUFFENC_AC0_58

HUFFENC_AC0_59

HUFFENC_AC0_60

HUFFENC_AC0_61

HUFFENC_AC0_62

HUFFENC_AC0_63

QMEM0_4

HUFFENC_AC0_64

HUFFENC_AC0_65

HUFFENC_AC0_66

HUFFENC_AC0_67

HUFFENC_AC0_68

HUFFENC_AC0_69

HUFFENC_AC0_70

HUFFENC_AC0_71

HUFFENC_AC0_72

HUFFENC_AC0_73

HUFFENC_AC0_74

HUFFENC_AC0_75

HUFFENC_AC0_76

HUFFENC_AC0_77

HUFFENC_AC0_78

HUFFENC_AC0_79

QMEM0_5

HUFFENC_AC0_80

HUFFENC_AC0_81

HUFFENC_AC0_82

HUFFENC_AC0_83

HUFFENC_AC0_84

HUFFENC_AC0_85

HUFFENC_AC0_86

HUFFENC_AC0_87

HUFFENC_AC1_0

HUFFENC_AC1_1

HUFFENC_AC1_2

HUFFENC_AC1_3

HUFFENC_AC1_4

HUFFENC_AC1_5

HUFFENC_AC1_6

HUFFENC_AC1_7

QMEM0_6

HUFFENC_AC1_8

HUFFENC_AC1_9

HUFFENC_AC1_10

HUFFENC_AC1_11

HUFFENC_AC1_12

HUFFENC_AC1_13

HUFFENC_AC1_14

HUFFENC_AC1_15

HUFFENC_AC1_16

HUFFENC_AC1_17

HUFFENC_AC1_18

HUFFENC_AC1_19

HUFFENC_AC1_20

HUFFENC_AC1_21

HUFFENC_AC1_22

HUFFENC_AC1_23

QMEM0_7

HUFFENC_AC1_24

HUFFENC_AC1_25

HUFFENC_AC1_26

HUFFENC_AC1_27

HUFFENC_AC1_28

HUFFENC_AC1_29

HUFFENC_AC1_30

HUFFENC_AC1_31

HUFFENC_AC1_32

HUFFENC_AC1_33

HUFFENC_AC1_34

HUFFENC_AC1_35

HUFFENC_AC1_36

HUFFENC_AC1_37

HUFFENC_AC1_38

HUFFENC_AC1_39

QMEM0_8

HUFFENC_AC1_40

HUFFENC_AC1_41

HUFFENC_AC1_42

HUFFENC_AC1_43

HUFFENC_AC1_44

HUFFENC_AC1_45

HUFFENC_AC1_46

HUFFENC_AC1_47

HUFFENC_AC1_48

HUFFENC_AC1_49

HUFFENC_AC1_50

HUFFENC_AC1_51

HUFFENC_AC1_52

HUFFENC_AC1_53

HUFFENC_AC1_54

HUFFENC_AC1_55

QMEM0_9

HUFFENC_AC1_56

HUFFENC_AC1_57

HUFFENC_AC1_58

HUFFENC_AC1_59

HUFFENC_AC1_60

HUFFENC_AC1_61

HUFFENC_AC1_62

HUFFENC_AC1_63

HUFFENC_AC1_64

HUFFENC_AC1_65

HUFFENC_AC1_66

HUFFENC_AC1_67

HUFFENC_AC1_68

HUFFENC_AC1_69

HUFFENC_AC1_70

HUFFENC_AC1_71

QMEM0_10

HUFFENC_AC1_72

HUFFENC_AC1_73

HUFFENC_AC1_74

HUFFENC_AC1_75

HUFFENC_AC1_76

HUFFENC_AC1_77

HUFFENC_AC1_78

HUFFENC_AC1_79

HUFFENC_AC1_80

HUFFENC_AC1_81

HUFFENC_AC1_82

HUFFENC_AC1_83

HUFFENC_AC1_84

HUFFENC_AC1_85

HUFFENC_AC1_86

HUFFENC_AC1_87

QMEM0_11

HUFFENC_DC0_0

HUFFENC_DC0_1

HUFFENC_DC0_2

HUFFENC_DC0_3

HUFFENC_DC0_4

HUFFENC_DC0_5

HUFFENC_DC0_6

HUFFENC_DC0_7

HUFFENC_DC1_0

HUFFENC_DC1_1

HUFFENC_DC1_2

HUFFENC_DC1_3

HUFFENC_DC1_4

HUFFENC_DC1_5

HUFFENC_DC1_6

HUFFENC_DC1_7

JPEG_CONFR2 (CONFR2)

QMEM0_12

QMEM0_13

QMEM0_14

QMEM0_15

QMEM1_0

QMEM1_1

QMEM1_2

QMEM1_3

QMEM1_4

QMEM1_5

QMEM1_6

QMEM1_7

QMEM1_8

QMEM1_9

QMEM1_10

QMEM1_11

JPEG_CONFR3 (CONFR3)

QMEM1_12

QMEM1_13

QMEM1_14

QMEM1_15

QMEM2_0

QMEM2_1

QMEM2_2

QMEM2_3

QMEM2_4

QMEM2_5

QMEM2_6

QMEM2_7

QMEM2_8

QMEM2_9

QMEM2_10

QMEM2_11


JPEG_CONFR0 (CONFR0)

JPEG codec configuration register 0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

JPEG_CONFR0 JPEG_CONFR0 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 START

START : Start
bits : 0 - 0 (1 bit)


JPEG_CONFR4 (CONFR4)

JPEG codec configuration register 4
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

JPEG_CONFR4 JPEG_CONFR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HD HA QT NB VSF HSF

HD : Huffman DC
bits : 0 - 0 (1 bit)

HA : Huffman AC
bits : 1 - 1 (1 bit)

QT : Quantization Table
bits : 2 - 3 (2 bit)

NB : Number of Block
bits : 4 - 7 (4 bit)

VSF : Vertical Sampling Factor
bits : 8 - 11 (4 bit)

HSF : Horizontal Sampling Factor
bits : 12 - 15 (4 bit)


QMEM2_12

JPEG quantization tables
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QMEM2_12 QMEM2_12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QMem_RAM

QMem_RAM : QMem RAM
bits : 0 - 31 (32 bit)


QMEM2_13

JPEG quantization tables
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QMEM2_13 QMEM2_13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QMem_RAM

QMem_RAM : QMem RAM
bits : 0 - 31 (32 bit)


QMEM2_14

JPEG quantization tables
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QMEM2_14 QMEM2_14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QMem_RAM

QMem_RAM : QMem RAM
bits : 0 - 31 (32 bit)


QMEM2_15

JPEG quantization tables
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QMEM2_15 QMEM2_15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QMem_RAM

QMem_RAM : QMem RAM
bits : 0 - 31 (32 bit)


QMEM3_0

JPEG quantization tables
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QMEM3_0 QMEM3_0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QMem_RAM

QMem_RAM : QMem RAM
bits : 0 - 31 (32 bit)


QMEM3_1

JPEG quantization tables
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QMEM3_1 QMEM3_1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QMem_RAM

QMem_RAM : QMem RAM
bits : 0 - 31 (32 bit)


QMEM3_2

JPEG quantization tables
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QMEM3_2 QMEM3_2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QMem_RAM

QMem_RAM : QMem RAM
bits : 0 - 31 (32 bit)


QMEM3_3

JPEG quantization tables
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QMEM3_3 QMEM3_3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QMem_RAM

QMem_RAM : QMem RAM
bits : 0 - 31 (32 bit)


QMEM3_4

JPEG quantization tables
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QMEM3_4 QMEM3_4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QMem_RAM

QMem_RAM : QMem RAM
bits : 0 - 31 (32 bit)


QMEM3_5

JPEG quantization tables
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QMEM3_5 QMEM3_5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QMem_RAM

QMem_RAM : QMem RAM
bits : 0 - 31 (32 bit)


QMEM3_6

JPEG quantization tables
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QMEM3_6 QMEM3_6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QMem_RAM

QMem_RAM : QMem RAM
bits : 0 - 31 (32 bit)


QMEM3_7

JPEG quantization tables
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QMEM3_7 QMEM3_7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QMem_RAM

QMem_RAM : QMem RAM
bits : 0 - 31 (32 bit)


QMEM3_8

JPEG quantization tables
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QMEM3_8 QMEM3_8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QMem_RAM

QMem_RAM : QMem RAM
bits : 0 - 31 (32 bit)


QMEM3_9

JPEG quantization tables
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QMEM3_9 QMEM3_9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QMem_RAM

QMem_RAM : QMem RAM
bits : 0 - 31 (32 bit)


QMEM3_10

JPEG quantization tables
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QMEM3_10 QMEM3_10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QMem_RAM

QMem_RAM : QMem RAM
bits : 0 - 31 (32 bit)


QMEM3_11

JPEG quantization tables
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QMEM3_11 QMEM3_11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QMem_RAM

QMem_RAM : QMem RAM
bits : 0 - 31 (32 bit)


JPEG_CONFR5 (CONFR5)

JPEG codec configuration register 5
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

JPEG_CONFR5 JPEG_CONFR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HD HA QT NB VSF HSF

HD : Huffman DC
bits : 0 - 0 (1 bit)

HA : Huffman AC
bits : 1 - 1 (1 bit)

QT : Quantization Table
bits : 2 - 3 (2 bit)

NB : Number of Block
bits : 4 - 7 (4 bit)

VSF : Vertical Sampling Factor
bits : 8 - 11 (4 bit)

HSF : Horizontal Sampling Factor
bits : 12 - 15 (4 bit)


QMEM3_12

JPEG quantization tables
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QMEM3_12 QMEM3_12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QMem_RAM

QMem_RAM : QMem RAM
bits : 0 - 31 (32 bit)


QMEM3_13

JPEG quantization tables
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QMEM3_13 QMEM3_13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QMem_RAM

QMem_RAM : QMem RAM
bits : 0 - 31 (32 bit)


QMEM3_14

JPEG quantization tables
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QMEM3_14 QMEM3_14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QMem_RAM

QMem_RAM : QMem RAM
bits : 0 - 31 (32 bit)


QMEM3_15

JPEG quantization tables
address_offset : 0x14C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QMEM3_15 QMEM3_15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QMem_RAM

QMem_RAM : QMem RAM
bits : 0 - 31 (32 bit)


HUFFMIN_0

JPEG HuffMin tables
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFMIN_0 HUFFMIN_0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffMin_RAM

HuffMin_RAM : HuffMin RAM
bits : 0 - 31 (32 bit)


HUFFMIN_1

JPEG HuffMin tables
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFMIN_1 HUFFMIN_1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffMin_RAM

HuffMin_RAM : HuffMin RAM
bits : 0 - 31 (32 bit)


HUFFMIN_2

JPEG HuffMin tables
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFMIN_2 HUFFMIN_2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffMin_RAM

HuffMin_RAM : HuffMin RAM
bits : 0 - 31 (32 bit)


HUFFMIN_3

JPEG HuffMin tables
address_offset : 0x15C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFMIN_3 HUFFMIN_3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffMin_RAM

HuffMin_RAM : HuffMin RAM
bits : 0 - 31 (32 bit)


HUFFMIN_4

JPEG HuffMin tables
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFMIN_4 HUFFMIN_4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffMin_RAM

HuffMin_RAM : HuffMin RAM
bits : 0 - 31 (32 bit)


HUFFMIN_5

JPEG HuffMin tables
address_offset : 0x164 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFMIN_5 HUFFMIN_5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffMin_RAM

HuffMin_RAM : HuffMin RAM
bits : 0 - 31 (32 bit)


HUFFMIN_6

JPEG HuffMin tables
address_offset : 0x168 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFMIN_6 HUFFMIN_6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffMin_RAM

HuffMin_RAM : HuffMin RAM
bits : 0 - 31 (32 bit)


HUFFMIN_7

JPEG HuffMin tables
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFMIN_7 HUFFMIN_7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffMin_RAM

HuffMin_RAM : HuffMin RAM
bits : 0 - 31 (32 bit)


HUFFMIN_8

JPEG HuffMin tables
address_offset : 0x170 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFMIN_8 HUFFMIN_8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffMin_RAM

HuffMin_RAM : HuffMin RAM
bits : 0 - 31 (32 bit)


HUFFMIN_9

JPEG HuffMin tables
address_offset : 0x174 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFMIN_9 HUFFMIN_9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffMin_RAM

HuffMin_RAM : HuffMin RAM
bits : 0 - 31 (32 bit)


HUFFMIN_10

JPEG HuffMin tables
address_offset : 0x178 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFMIN_10 HUFFMIN_10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffMin_RAM

HuffMin_RAM : HuffMin RAM
bits : 0 - 31 (32 bit)


HUFFMIN_11

JPEG HuffMin tables
address_offset : 0x17C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFMIN_11 HUFFMIN_11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffMin_RAM

HuffMin_RAM : HuffMin RAM
bits : 0 - 31 (32 bit)


JPEG_CONFR6 (CONFR6)

JPEG codec configuration register 6
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

JPEG_CONFR6 JPEG_CONFR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HD HA QT NB VSF HSF

HD : Huffman DC
bits : 0 - 0 (1 bit)

HA : Huffman AC
bits : 1 - 1 (1 bit)

QT : Quantization Table
bits : 2 - 3 (2 bit)

NB : Number of Block
bits : 4 - 7 (4 bit)

VSF : Vertical Sampling Factor
bits : 8 - 11 (4 bit)

HSF : Horizontal Sampling Factor
bits : 12 - 15 (4 bit)


HUFFMIN_12

JPEG HuffMin tables
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFMIN_12 HUFFMIN_12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffMin_RAM

HuffMin_RAM : HuffMin RAM
bits : 0 - 31 (32 bit)


HUFFMIN_13

JPEG HuffMin tables
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFMIN_13 HUFFMIN_13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffMin_RAM

HuffMin_RAM : HuffMin RAM
bits : 0 - 31 (32 bit)


HUFFMIN_14

JPEG HuffMin tables
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFMIN_14 HUFFMIN_14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffMin_RAM

HuffMin_RAM : HuffMin RAM
bits : 0 - 31 (32 bit)


HUFFMIN_15

JPEG HuffMin tables
address_offset : 0x18C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFMIN_15 HUFFMIN_15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffMin_RAM

HuffMin_RAM : HuffMin RAM
bits : 0 - 31 (32 bit)


HUFFBASE0

JPEG HuffSymb tables
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFBASE0 HUFFBASE0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffBase_RAM_0 HuffBase_RAM_1

HuffBase_RAM_0 : HuffBase RAM
bits : 0 - 8 (9 bit)

HuffBase_RAM_1 : HuffBase RAM
bits : 16 - 24 (9 bit)


HUFFBASE1

JPEG HuffSymb tables
address_offset : 0x194 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFBASE1 HUFFBASE1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffBase_RAM_0 HuffBase_RAM_1

HuffBase_RAM_0 : HuffBase RAM
bits : 0 - 8 (9 bit)

HuffBase_RAM_1 : HuffBase RAM
bits : 16 - 24 (9 bit)


HUFFBASE2

JPEG HuffSymb tables
address_offset : 0x198 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFBASE2 HUFFBASE2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffBase_RAM_0 HuffBase_RAM_1

HuffBase_RAM_0 : HuffBase RAM
bits : 0 - 8 (9 bit)

HuffBase_RAM_1 : HuffBase RAM
bits : 16 - 24 (9 bit)


HUFFBASE3

JPEG HuffSymb tables
address_offset : 0x19C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFBASE3 HUFFBASE3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffBase_RAM_0 HuffBase_RAM_1

HuffBase_RAM_0 : HuffBase RAM
bits : 0 - 8 (9 bit)

HuffBase_RAM_1 : HuffBase RAM
bits : 16 - 24 (9 bit)


HUFFBASE4

JPEG HuffSymb tables
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFBASE4 HUFFBASE4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffBase_RAM_0 HuffBase_RAM_1

HuffBase_RAM_0 : HuffBase RAM
bits : 0 - 8 (9 bit)

HuffBase_RAM_1 : HuffBase RAM
bits : 16 - 24 (9 bit)


HUFFBASE5

JPEG HuffSymb tables
address_offset : 0x1A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFBASE5 HUFFBASE5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffBase_RAM_0 HuffBase_RAM_1

HuffBase_RAM_0 : HuffBase RAM
bits : 0 - 8 (9 bit)

HuffBase_RAM_1 : HuffBase RAM
bits : 16 - 24 (9 bit)


HUFFBASE6

JPEG HuffSymb tables
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFBASE6 HUFFBASE6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffBase_RAM_0 HuffBase_RAM_1

HuffBase_RAM_0 : HuffBase RAM
bits : 0 - 8 (9 bit)

HuffBase_RAM_1 : HuffBase RAM
bits : 16 - 24 (9 bit)


HUFFBASE7

JPEG HuffSymb tables
address_offset : 0x1AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFBASE7 HUFFBASE7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffBase_RAM_0 HuffBase_RAM_1

HuffBase_RAM_0 : HuffBase RAM
bits : 0 - 8 (9 bit)

HuffBase_RAM_1 : HuffBase RAM
bits : 16 - 24 (9 bit)


HUFFBASE8

JPEG HuffSymb tables
address_offset : 0x1B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFBASE8 HUFFBASE8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffBase_RAM_0 HuffBase_RAM_1

HuffBase_RAM_0 : HuffBase RAM
bits : 0 - 8 (9 bit)

HuffBase_RAM_1 : HuffBase RAM
bits : 16 - 24 (9 bit)


HUFFBASE9

JPEG HuffSymb tables
address_offset : 0x1B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFBASE9 HUFFBASE9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffBase_RAM_0 HuffBase_RAM_1

HuffBase_RAM_0 : HuffBase RAM
bits : 0 - 8 (9 bit)

HuffBase_RAM_1 : HuffBase RAM
bits : 16 - 24 (9 bit)


HUFFBASE10

JPEG HuffSymb tables
address_offset : 0x1B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFBASE10 HUFFBASE10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffBase_RAM_0 HuffBase_RAM_1

HuffBase_RAM_0 : HuffBase RAM
bits : 0 - 8 (9 bit)

HuffBase_RAM_1 : HuffBase RAM
bits : 16 - 24 (9 bit)


HUFFBASE11

JPEG HuffSymb tables
address_offset : 0x1BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFBASE11 HUFFBASE11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffBase_RAM_0 HuffBase_RAM_1

HuffBase_RAM_0 : HuffBase RAM
bits : 0 - 8 (9 bit)

HuffBase_RAM_1 : HuffBase RAM
bits : 16 - 24 (9 bit)


JPEG_CONFR7 (CONFR7)

JPEG codec configuration register 7
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

JPEG_CONFR7 JPEG_CONFR7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HD HA QT NB VSF HSF

HD : Huffman DC
bits : 0 - 0 (1 bit)

HA : Huffman AC
bits : 1 - 1 (1 bit)

QT : Quantization Table
bits : 2 - 3 (2 bit)

NB : Number of Block
bits : 4 - 7 (4 bit)

VSF : Vertical Sampling Factor
bits : 8 - 11 (4 bit)

HSF : Horizontal Sampling Factor
bits : 12 - 15 (4 bit)


HUFFBASE12

JPEG HuffSymb tables
address_offset : 0x1C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFBASE12 HUFFBASE12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffBase_RAM_0 HuffBase_RAM_1

HuffBase_RAM_0 : HuffBase RAM
bits : 0 - 8 (9 bit)

HuffBase_RAM_1 : HuffBase RAM
bits : 16 - 24 (9 bit)


HUFFBASE13

JPEG HuffSymb tables
address_offset : 0x1C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFBASE13 HUFFBASE13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffBase_RAM_0 HuffBase_RAM_1

HuffBase_RAM_0 : HuffBase RAM
bits : 0 - 8 (9 bit)

HuffBase_RAM_1 : HuffBase RAM
bits : 16 - 24 (9 bit)


HUFFBASE14

JPEG HuffSymb tables
address_offset : 0x1C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFBASE14 HUFFBASE14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffBase_RAM_0 HuffBase_RAM_1

HuffBase_RAM_0 : HuffBase RAM
bits : 0 - 8 (9 bit)

HuffBase_RAM_1 : HuffBase RAM
bits : 16 - 24 (9 bit)


HUFFBASE15

JPEG HuffSymb tables
address_offset : 0x1CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFBASE15 HUFFBASE15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffBase_RAM_0 HuffBase_RAM_1

HuffBase_RAM_0 : HuffBase RAM
bits : 0 - 8 (9 bit)

HuffBase_RAM_1 : HuffBase RAM
bits : 16 - 24 (9 bit)


HUFFBASE16

JPEG HuffSymb tables
address_offset : 0x1D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFBASE16 HUFFBASE16 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffBase_RAM_0 HuffBase_RAM_1

HuffBase_RAM_0 : HuffBase RAM
bits : 0 - 8 (9 bit)

HuffBase_RAM_1 : HuffBase RAM
bits : 16 - 24 (9 bit)


HUFFBASE17

JPEG HuffSymb tables
address_offset : 0x1D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFBASE17 HUFFBASE17 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffBase_RAM_0 HuffBase_RAM_1

HuffBase_RAM_0 : HuffBase RAM
bits : 0 - 8 (9 bit)

HuffBase_RAM_1 : HuffBase RAM
bits : 16 - 24 (9 bit)


HUFFBASE18

JPEG HuffSymb tables
address_offset : 0x1D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFBASE18 HUFFBASE18 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffBase_RAM_0 HuffBase_RAM_1

HuffBase_RAM_0 : HuffBase RAM
bits : 0 - 8 (9 bit)

HuffBase_RAM_1 : HuffBase RAM
bits : 16 - 24 (9 bit)


HUFFBASE19

JPEG HuffSymb tables
address_offset : 0x1DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFBASE19 HUFFBASE19 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffBase_RAM_0 HuffBase_RAM_1

HuffBase_RAM_0 : HuffBase RAM
bits : 0 - 8 (9 bit)

HuffBase_RAM_1 : HuffBase RAM
bits : 16 - 24 (9 bit)


HUFFBASE20

JPEG HuffSymb tables
address_offset : 0x1E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFBASE20 HUFFBASE20 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffBase_RAM_0 HuffBase_RAM_1

HuffBase_RAM_0 : HuffBase RAM
bits : 0 - 8 (9 bit)

HuffBase_RAM_1 : HuffBase RAM
bits : 16 - 24 (9 bit)


HUFFBASE21

JPEG HuffSymb tables
address_offset : 0x1E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFBASE21 HUFFBASE21 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffBase_RAM_0 HuffBase_RAM_1

HuffBase_RAM_0 : HuffBase RAM
bits : 0 - 8 (9 bit)

HuffBase_RAM_1 : HuffBase RAM
bits : 16 - 24 (9 bit)


HUFFBASE22

JPEG HuffSymb tables
address_offset : 0x1E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFBASE22 HUFFBASE22 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffBase_RAM_0 HuffBase_RAM_1

HuffBase_RAM_0 : HuffBase RAM
bits : 0 - 8 (9 bit)

HuffBase_RAM_1 : HuffBase RAM
bits : 16 - 24 (9 bit)


HUFFBASE23

JPEG HuffSymb tables
address_offset : 0x1EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFBASE23 HUFFBASE23 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffBase_RAM_0 HuffBase_RAM_1

HuffBase_RAM_0 : HuffBase RAM
bits : 0 - 8 (9 bit)

HuffBase_RAM_1 : HuffBase RAM
bits : 16 - 24 (9 bit)


HUFFBASE24

JPEG HuffSymb tables
address_offset : 0x1F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFBASE24 HUFFBASE24 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffBase_RAM_0 HuffBase_RAM_1

HuffBase_RAM_0 : HuffBase RAM
bits : 0 - 8 (9 bit)

HuffBase_RAM_1 : HuffBase RAM
bits : 16 - 24 (9 bit)


HUFFBASE25

JPEG HuffSymb tables
address_offset : 0x1F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFBASE25 HUFFBASE25 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffBase_RAM_0 HuffBase_RAM_1

HuffBase_RAM_0 : HuffBase RAM
bits : 0 - 8 (9 bit)

HuffBase_RAM_1 : HuffBase RAM
bits : 16 - 24 (9 bit)


HUFFBASE26

JPEG HuffSymb tables
address_offset : 0x1F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFBASE26 HUFFBASE26 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffBase_RAM_0 HuffBase_RAM_1

HuffBase_RAM_0 : HuffBase RAM
bits : 0 - 8 (9 bit)

HuffBase_RAM_1 : HuffBase RAM
bits : 16 - 24 (9 bit)


HUFFBASE27

JPEG HuffSymb tables
address_offset : 0x1FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFBASE27 HUFFBASE27 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffBase_RAM_0 HuffBase_RAM_1

HuffBase_RAM_0 : HuffBase RAM
bits : 0 - 8 (9 bit)

HuffBase_RAM_1 : HuffBase RAM
bits : 16 - 24 (9 bit)


HUFFBASE28

JPEG HuffSymb tables
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFBASE28 HUFFBASE28 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffBase_RAM_0 HuffBase_RAM_1

HuffBase_RAM_0 : HuffBase RAM
bits : 0 - 8 (9 bit)

HuffBase_RAM_1 : HuffBase RAM
bits : 16 - 24 (9 bit)


HUFFBASE29

JPEG HuffSymb tables
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFBASE29 HUFFBASE29 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffBase_RAM_0 HuffBase_RAM_1

HuffBase_RAM_0 : HuffBase RAM
bits : 0 - 8 (9 bit)

HuffBase_RAM_1 : HuffBase RAM
bits : 16 - 24 (9 bit)


HUFFBASE30

JPEG HuffSymb tables
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFBASE30 HUFFBASE30 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffBase_RAM_0 HuffBase_RAM_1

HuffBase_RAM_0 : HuffBase RAM
bits : 0 - 8 (9 bit)

HuffBase_RAM_1 : HuffBase RAM
bits : 16 - 24 (9 bit)


HUFFBASE31

JPEG HuffSymb tables
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFBASE31 HUFFBASE31 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffBase_RAM_0 HuffBase_RAM_1

HuffBase_RAM_0 : HuffBase RAM
bits : 0 - 8 (9 bit)

HuffBase_RAM_1 : HuffBase RAM
bits : 16 - 24 (9 bit)


HUFFSYMB0

JPEG HUFFSYMB tables
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFSYMB0 HUFFSYMB0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffSymb_RAM

HuffSymb_RAM : DHTSymb RAM
bits : 0 - 31 (32 bit)


HUFFSYMB1

JPEG HUFFSYMB tables
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFSYMB1 HUFFSYMB1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffSymb_RAM

HuffSymb_RAM : DHTSymb RAM
bits : 0 - 31 (32 bit)


HUFFSYMB2

JPEG HUFFSYMB tables
address_offset : 0x218 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFSYMB2 HUFFSYMB2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffSymb_RAM

HuffSymb_RAM : DHTSymb RAM
bits : 0 - 31 (32 bit)


HUFFSYMB3

JPEG HUFFSYMB tables
address_offset : 0x21C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFSYMB3 HUFFSYMB3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffSymb_RAM

HuffSymb_RAM : DHTSymb RAM
bits : 0 - 31 (32 bit)


HUFFSYMB4

JPEG HUFFSYMB tables
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFSYMB4 HUFFSYMB4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffSymb_RAM

HuffSymb_RAM : DHTSymb RAM
bits : 0 - 31 (32 bit)


HUFFSYMB5

JPEG HUFFSYMB tables
address_offset : 0x224 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFSYMB5 HUFFSYMB5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffSymb_RAM

HuffSymb_RAM : DHTSymb RAM
bits : 0 - 31 (32 bit)


HUFFSYMB6

JPEG HUFFSYMB tables
address_offset : 0x228 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFSYMB6 HUFFSYMB6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffSymb_RAM

HuffSymb_RAM : DHTSymb RAM
bits : 0 - 31 (32 bit)


HUFFSYMB7

JPEG HUFFSYMB tables
address_offset : 0x22C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFSYMB7 HUFFSYMB7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffSymb_RAM

HuffSymb_RAM : DHTSymb RAM
bits : 0 - 31 (32 bit)


HUFFSYMB8

JPEG HUFFSYMB tables
address_offset : 0x230 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFSYMB8 HUFFSYMB8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffSymb_RAM

HuffSymb_RAM : DHTSymb RAM
bits : 0 - 31 (32 bit)


HUFFSYMB9

JPEG HUFFSYMB tables
address_offset : 0x234 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFSYMB9 HUFFSYMB9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffSymb_RAM

HuffSymb_RAM : DHTSymb RAM
bits : 0 - 31 (32 bit)


HUFFSYMB10

JPEG HUFFSYMB tables
address_offset : 0x238 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFSYMB10 HUFFSYMB10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffSymb_RAM

HuffSymb_RAM : DHTSymb RAM
bits : 0 - 31 (32 bit)


HUFFSYMB11

JPEG HUFFSYMB tables
address_offset : 0x23C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFSYMB11 HUFFSYMB11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffSymb_RAM

HuffSymb_RAM : DHTSymb RAM
bits : 0 - 31 (32 bit)


HUFFSYMB12

JPEG HUFFSYMB tables
address_offset : 0x240 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFSYMB12 HUFFSYMB12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffSymb_RAM

HuffSymb_RAM : DHTSymb RAM
bits : 0 - 31 (32 bit)


HUFFSYMB13

JPEG HUFFSYMB tables
address_offset : 0x244 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFSYMB13 HUFFSYMB13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffSymb_RAM

HuffSymb_RAM : DHTSymb RAM
bits : 0 - 31 (32 bit)


HUFFSYMB14

JPEG HUFFSYMB tables
address_offset : 0x248 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFSYMB14 HUFFSYMB14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffSymb_RAM

HuffSymb_RAM : DHTSymb RAM
bits : 0 - 31 (32 bit)


HUFFSYMB15

JPEG HUFFSYMB tables
address_offset : 0x24C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFSYMB15 HUFFSYMB15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffSymb_RAM

HuffSymb_RAM : DHTSymb RAM
bits : 0 - 31 (32 bit)


HUFFSYMB16

JPEG HUFFSYMB tables
address_offset : 0x250 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFSYMB16 HUFFSYMB16 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffSymb_RAM

HuffSymb_RAM : DHTSymb RAM
bits : 0 - 31 (32 bit)


HUFFSYMB17

JPEG HUFFSYMB tables
address_offset : 0x254 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFSYMB17 HUFFSYMB17 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffSymb_RAM

HuffSymb_RAM : DHTSymb RAM
bits : 0 - 31 (32 bit)


HUFFSYMB18

JPEG HUFFSYMB tables
address_offset : 0x258 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFSYMB18 HUFFSYMB18 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffSymb_RAM

HuffSymb_RAM : DHTSymb RAM
bits : 0 - 31 (32 bit)


HUFFSYMB19

JPEG HUFFSYMB tables
address_offset : 0x25C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFSYMB19 HUFFSYMB19 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffSymb_RAM

HuffSymb_RAM : DHTSymb RAM
bits : 0 - 31 (32 bit)


HUFFSYMB20

JPEG HUFFSYMB tables
address_offset : 0x260 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFSYMB20 HUFFSYMB20 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffSymb_RAM

HuffSymb_RAM : DHTSymb RAM
bits : 0 - 31 (32 bit)


HUFFSYMB21

JPEG HUFFSYMB tables
address_offset : 0x264 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFSYMB21 HUFFSYMB21 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffSymb_RAM

HuffSymb_RAM : DHTSymb RAM
bits : 0 - 31 (32 bit)


HUFFSYMB22

JPEG HUFFSYMB tables
address_offset : 0x268 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFSYMB22 HUFFSYMB22 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffSymb_RAM

HuffSymb_RAM : DHTSymb RAM
bits : 0 - 31 (32 bit)


HUFFSYMB23

JPEG HUFFSYMB tables
address_offset : 0x26C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFSYMB23 HUFFSYMB23 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffSymb_RAM

HuffSymb_RAM : DHTSymb RAM
bits : 0 - 31 (32 bit)


HUFFSYMB24

JPEG HUFFSYMB tables
address_offset : 0x270 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFSYMB24 HUFFSYMB24 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffSymb_RAM

HuffSymb_RAM : DHTSymb RAM
bits : 0 - 31 (32 bit)


HUFFSYMB25

JPEG HUFFSYMB tables
address_offset : 0x274 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFSYMB25 HUFFSYMB25 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffSymb_RAM

HuffSymb_RAM : DHTSymb RAM
bits : 0 - 31 (32 bit)


HUFFSYMB26

JPEG HUFFSYMB tables
address_offset : 0x278 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFSYMB26 HUFFSYMB26 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffSymb_RAM

HuffSymb_RAM : DHTSymb RAM
bits : 0 - 31 (32 bit)


HUFFSYMB27

JPEG HUFFSYMB tables
address_offset : 0x27C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFSYMB27 HUFFSYMB27 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffSymb_RAM

HuffSymb_RAM : DHTSymb RAM
bits : 0 - 31 (32 bit)


HUFFSYMB28

JPEG HUFFSYMB tables
address_offset : 0x280 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFSYMB28 HUFFSYMB28 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffSymb_RAM

HuffSymb_RAM : DHTSymb RAM
bits : 0 - 31 (32 bit)


HUFFSYMB29

JPEG HUFFSYMB tables
address_offset : 0x284 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFSYMB29 HUFFSYMB29 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffSymb_RAM

HuffSymb_RAM : DHTSymb RAM
bits : 0 - 31 (32 bit)


HUFFSYMB30

JPEG HUFFSYMB tables
address_offset : 0x288 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFSYMB30 HUFFSYMB30 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffSymb_RAM

HuffSymb_RAM : DHTSymb RAM
bits : 0 - 31 (32 bit)


HUFFSYMB31

JPEG HUFFSYMB tables
address_offset : 0x28C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFSYMB31 HUFFSYMB31 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffSymb_RAM

HuffSymb_RAM : DHTSymb RAM
bits : 0 - 31 (32 bit)


HUFFSYMB32

JPEG HUFFSYMB tables
address_offset : 0x290 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFSYMB32 HUFFSYMB32 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffSymb_RAM

HuffSymb_RAM : DHTSymb RAM
bits : 0 - 31 (32 bit)


HUFFSYMB33

JPEG HUFFSYMB tables
address_offset : 0x294 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFSYMB33 HUFFSYMB33 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffSymb_RAM

HuffSymb_RAM : DHTSymb RAM
bits : 0 - 31 (32 bit)


HUFFSYMB34

JPEG HUFFSYMB tables
address_offset : 0x298 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFSYMB34 HUFFSYMB34 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffSymb_RAM

HuffSymb_RAM : DHTSymb RAM
bits : 0 - 31 (32 bit)


HUFFSYMB35

JPEG HUFFSYMB tables
address_offset : 0x29C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFSYMB35 HUFFSYMB35 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffSymb_RAM

HuffSymb_RAM : DHTSymb RAM
bits : 0 - 31 (32 bit)


HUFFSYMB36

JPEG HUFFSYMB tables
address_offset : 0x2A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFSYMB36 HUFFSYMB36 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffSymb_RAM

HuffSymb_RAM : DHTSymb RAM
bits : 0 - 31 (32 bit)


HUFFSYMB37

JPEG HUFFSYMB tables
address_offset : 0x2A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFSYMB37 HUFFSYMB37 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffSymb_RAM

HuffSymb_RAM : DHTSymb RAM
bits : 0 - 31 (32 bit)


HUFFSYMB38

JPEG HUFFSYMB tables
address_offset : 0x2A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFSYMB38 HUFFSYMB38 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffSymb_RAM

HuffSymb_RAM : DHTSymb RAM
bits : 0 - 31 (32 bit)


HUFFSYMB39

JPEG HUFFSYMB tables
address_offset : 0x2AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFSYMB39 HUFFSYMB39 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffSymb_RAM

HuffSymb_RAM : DHTSymb RAM
bits : 0 - 31 (32 bit)


HUFFSYMB40

JPEG HUFFSYMB tables
address_offset : 0x2B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFSYMB40 HUFFSYMB40 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffSymb_RAM

HuffSymb_RAM : DHTSymb RAM
bits : 0 - 31 (32 bit)


HUFFSYMB41

JPEG HUFFSYMB tables
address_offset : 0x2B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFSYMB41 HUFFSYMB41 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffSymb_RAM

HuffSymb_RAM : DHTSymb RAM
bits : 0 - 31 (32 bit)


HUFFSYMB42

JPEG HUFFSYMB tables
address_offset : 0x2B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFSYMB42 HUFFSYMB42 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffSymb_RAM

HuffSymb_RAM : DHTSymb RAM
bits : 0 - 31 (32 bit)


HUFFSYMB43

JPEG HUFFSYMB tables
address_offset : 0x2BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFSYMB43 HUFFSYMB43 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffSymb_RAM

HuffSymb_RAM : DHTSymb RAM
bits : 0 - 31 (32 bit)


HUFFSYMB44

JPEG HUFFSYMB tables
address_offset : 0x2C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFSYMB44 HUFFSYMB44 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffSymb_RAM

HuffSymb_RAM : DHTSymb RAM
bits : 0 - 31 (32 bit)


HUFFSYMB45

JPEG HUFFSYMB tables
address_offset : 0x2C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFSYMB45 HUFFSYMB45 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffSymb_RAM

HuffSymb_RAM : DHTSymb RAM
bits : 0 - 31 (32 bit)


HUFFSYMB46

JPEG HUFFSYMB tables
address_offset : 0x2C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFSYMB46 HUFFSYMB46 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffSymb_RAM

HuffSymb_RAM : DHTSymb RAM
bits : 0 - 31 (32 bit)


HUFFSYMB47

JPEG HUFFSYMB tables
address_offset : 0x2CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFSYMB47 HUFFSYMB47 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffSymb_RAM

HuffSymb_RAM : DHTSymb RAM
bits : 0 - 31 (32 bit)


HUFFSYMB48

JPEG HUFFSYMB tables
address_offset : 0x2D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFSYMB48 HUFFSYMB48 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffSymb_RAM

HuffSymb_RAM : DHTSymb RAM
bits : 0 - 31 (32 bit)


HUFFSYMB49

JPEG HUFFSYMB tables
address_offset : 0x2D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFSYMB49 HUFFSYMB49 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffSymb_RAM

HuffSymb_RAM : DHTSymb RAM
bits : 0 - 31 (32 bit)


HUFFSYMB50

JPEG HUFFSYMB tables
address_offset : 0x2D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFSYMB50 HUFFSYMB50 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffSymb_RAM

HuffSymb_RAM : DHTSymb RAM
bits : 0 - 31 (32 bit)


HUFFSYMB51

JPEG HUFFSYMB tables
address_offset : 0x2DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFSYMB51 HUFFSYMB51 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffSymb_RAM

HuffSymb_RAM : DHTSymb RAM
bits : 0 - 31 (32 bit)


HUFFSYMB52

JPEG HUFFSYMB tables
address_offset : 0x2E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFSYMB52 HUFFSYMB52 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffSymb_RAM

HuffSymb_RAM : DHTSymb RAM
bits : 0 - 31 (32 bit)


HUFFSYMB53

JPEG HUFFSYMB tables
address_offset : 0x2E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFSYMB53 HUFFSYMB53 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffSymb_RAM

HuffSymb_RAM : DHTSymb RAM
bits : 0 - 31 (32 bit)


HUFFSYMB54

JPEG HUFFSYMB tables
address_offset : 0x2E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFSYMB54 HUFFSYMB54 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffSymb_RAM

HuffSymb_RAM : DHTSymb RAM
bits : 0 - 31 (32 bit)


HUFFSYMB55

JPEG HUFFSYMB tables
address_offset : 0x2EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFSYMB55 HUFFSYMB55 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffSymb_RAM

HuffSymb_RAM : DHTSymb RAM
bits : 0 - 31 (32 bit)


HUFFSYMB56

JPEG HUFFSYMB tables
address_offset : 0x2F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFSYMB56 HUFFSYMB56 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffSymb_RAM

HuffSymb_RAM : DHTSymb RAM
bits : 0 - 31 (32 bit)


HUFFSYMB57

JPEG HUFFSYMB tables
address_offset : 0x2F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFSYMB57 HUFFSYMB57 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffSymb_RAM

HuffSymb_RAM : DHTSymb RAM
bits : 0 - 31 (32 bit)


HUFFSYMB58

JPEG HUFFSYMB tables
address_offset : 0x2F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFSYMB58 HUFFSYMB58 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffSymb_RAM

HuffSymb_RAM : DHTSymb RAM
bits : 0 - 31 (32 bit)


HUFFSYMB59

JPEG HUFFSYMB tables
address_offset : 0x2FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFSYMB59 HUFFSYMB59 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffSymb_RAM

HuffSymb_RAM : DHTSymb RAM
bits : 0 - 31 (32 bit)


JPEG_CR (CR)

JPEG control register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

JPEG_CR JPEG_CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JCEN IFTIE IFNFIE OFTIE OFNEIE EOCIE HPDIE IDMAEN ODMAEN IFF OFF

JCEN : JPEG Core Enable
bits : 0 - 0 (1 bit)
access : read-write

IFTIE : Input FIFO Threshold Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write

IFNFIE : Input FIFO Not Full Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write

OFTIE : Output FIFO Threshold Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-write

OFNEIE : Output FIFO Not Empty Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write

EOCIE : End of Conversion Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write

HPDIE : Header Parsing Done Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write

IDMAEN : Input DMA Enable
bits : 11 - 11 (1 bit)
access : read-write

ODMAEN : Output DMA Enable
bits : 12 - 12 (1 bit)
access : read-write

IFF : Input FIFO Flush
bits : 13 - 13 (1 bit)
access : read-only

OFF : Output FIFO Flush
bits : 14 - 14 (1 bit)
access : read-only


HUFFSYMB60

JPEG HUFFSYMB tables
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFSYMB60 HUFFSYMB60 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffSymb_RAM

HuffSymb_RAM : DHTSymb RAM
bits : 0 - 31 (32 bit)


HUFFSYMB61

JPEG HUFFSYMB tables
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFSYMB61 HUFFSYMB61 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffSymb_RAM

HuffSymb_RAM : DHTSymb RAM
bits : 0 - 31 (32 bit)


HUFFSYMB62

JPEG HUFFSYMB tables
address_offset : 0x308 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFSYMB62 HUFFSYMB62 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffSymb_RAM

HuffSymb_RAM : DHTSymb RAM
bits : 0 - 31 (32 bit)


HUFFSYMB63

JPEG HUFFSYMB tables
address_offset : 0x30C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFSYMB63 HUFFSYMB63 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffSymb_RAM

HuffSymb_RAM : DHTSymb RAM
bits : 0 - 31 (32 bit)


HUFFSYMB64

JPEG HUFFSYMB tables
address_offset : 0x310 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFSYMB64 HUFFSYMB64 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffSymb_RAM

HuffSymb_RAM : DHTSymb RAM
bits : 0 - 31 (32 bit)


HUFFSYMB65

JPEG HUFFSYMB tables
address_offset : 0x314 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFSYMB65 HUFFSYMB65 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffSymb_RAM

HuffSymb_RAM : DHTSymb RAM
bits : 0 - 31 (32 bit)


HUFFSYMB66

JPEG HUFFSYMB tables
address_offset : 0x318 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFSYMB66 HUFFSYMB66 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffSymb_RAM

HuffSymb_RAM : DHTSymb RAM
bits : 0 - 31 (32 bit)


HUFFSYMB67

JPEG HUFFSYMB tables
address_offset : 0x31C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFSYMB67 HUFFSYMB67 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffSymb_RAM

HuffSymb_RAM : DHTSymb RAM
bits : 0 - 31 (32 bit)


HUFFSYMB68

JPEG HUFFSYMB tables
address_offset : 0x320 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFSYMB68 HUFFSYMB68 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffSymb_RAM

HuffSymb_RAM : DHTSymb RAM
bits : 0 - 31 (32 bit)


HUFFSYMB69

JPEG HUFFSYMB tables
address_offset : 0x324 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFSYMB69 HUFFSYMB69 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffSymb_RAM

HuffSymb_RAM : DHTSymb RAM
bits : 0 - 31 (32 bit)


HUFFSYMB70

JPEG HUFFSYMB tables
address_offset : 0x328 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFSYMB70 HUFFSYMB70 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffSymb_RAM

HuffSymb_RAM : DHTSymb RAM
bits : 0 - 31 (32 bit)


HUFFSYMB71

JPEG HUFFSYMB tables
address_offset : 0x32C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFSYMB71 HUFFSYMB71 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffSymb_RAM

HuffSymb_RAM : DHTSymb RAM
bits : 0 - 31 (32 bit)


HUFFSYMB72

JPEG HUFFSYMB tables
address_offset : 0x330 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFSYMB72 HUFFSYMB72 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffSymb_RAM

HuffSymb_RAM : DHTSymb RAM
bits : 0 - 31 (32 bit)


HUFFSYMB73

JPEG HUFFSYMB tables
address_offset : 0x334 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFSYMB73 HUFFSYMB73 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffSymb_RAM

HuffSymb_RAM : DHTSymb RAM
bits : 0 - 31 (32 bit)


HUFFSYMB74

JPEG HUFFSYMB tables
address_offset : 0x338 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFSYMB74 HUFFSYMB74 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffSymb_RAM

HuffSymb_RAM : DHTSymb RAM
bits : 0 - 31 (32 bit)


HUFFSYMB75

JPEG HUFFSYMB tables
address_offset : 0x33C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFSYMB75 HUFFSYMB75 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffSymb_RAM

HuffSymb_RAM : DHTSymb RAM
bits : 0 - 31 (32 bit)


JPEG_SR (SR)

JPEG status register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

JPEG_SR JPEG_SR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IFTF IFNFF OFTF OFNEF EOCF HPDF COF

IFTF : Input FIFO Threshold Flag
bits : 1 - 1 (1 bit)

IFNFF : Input FIFO Not Full Flag
bits : 2 - 2 (1 bit)

OFTF : Output FIFO Threshold Flag
bits : 3 - 3 (1 bit)

OFNEF : Output FIFO Not Empty Flag
bits : 4 - 4 (1 bit)

EOCF : End of Conversion Flag
bits : 5 - 5 (1 bit)

HPDF : Header Parsing Done Flag
bits : 6 - 6 (1 bit)

COF : Codec Operation Flag
bits : 7 - 7 (1 bit)


HUFFSYMB76

JPEG HUFFSYMB tables
address_offset : 0x340 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFSYMB76 HUFFSYMB76 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffSymb_RAM

HuffSymb_RAM : DHTSymb RAM
bits : 0 - 31 (32 bit)


HUFFSYMB77

JPEG HUFFSYMB tables
address_offset : 0x344 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFSYMB77 HUFFSYMB77 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffSymb_RAM

HuffSymb_RAM : DHTSymb RAM
bits : 0 - 31 (32 bit)


HUFFSYMB78

JPEG HUFFSYMB tables
address_offset : 0x348 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFSYMB78 HUFFSYMB78 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffSymb_RAM

HuffSymb_RAM : DHTSymb RAM
bits : 0 - 31 (32 bit)


HUFFSYMB79

JPEG HUFFSYMB tables
address_offset : 0x34C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFSYMB79 HUFFSYMB79 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffSymb_RAM

HuffSymb_RAM : DHTSymb RAM
bits : 0 - 31 (32 bit)


HUFFSYMB80

JPEG HUFFSYMB tables
address_offset : 0x350 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFSYMB80 HUFFSYMB80 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffSymb_RAM

HuffSymb_RAM : DHTSymb RAM
bits : 0 - 31 (32 bit)


HUFFSYMB81

JPEG HUFFSYMB tables
address_offset : 0x354 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFSYMB81 HUFFSYMB81 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffSymb_RAM

HuffSymb_RAM : DHTSymb RAM
bits : 0 - 31 (32 bit)


HUFFSYMB82

JPEG HUFFSYMB tables
address_offset : 0x358 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFSYMB82 HUFFSYMB82 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffSymb_RAM

HuffSymb_RAM : DHTSymb RAM
bits : 0 - 31 (32 bit)


HUFFSYMB83

JPEG HUFFSYMB tables
address_offset : 0x35C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFSYMB83 HUFFSYMB83 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HuffSymb_RAM

HuffSymb_RAM : DHTSymb RAM
bits : 0 - 31 (32 bit)


DHTMEM0

JPEG DHTMem tables
address_offset : 0x360 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM0 DHTMEM0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM2

JPEG DHTMem tables
address_offset : 0x364 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM2 DHTMEM2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM3

JPEG DHTMem tables
address_offset : 0x368 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM3 DHTMEM3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM4

JPEG DHTMem tables
address_offset : 0x36C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM4 DHTMEM4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM5

JPEG DHTMem tables
address_offset : 0x370 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM5 DHTMEM5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM6

JPEG DHTMem tables
address_offset : 0x374 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM6 DHTMEM6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM7

JPEG DHTMem tables
address_offset : 0x378 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM7 DHTMEM7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM8

JPEG DHTMem tables
address_offset : 0x37C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM8 DHTMEM8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


JPEG_CFR (CFR)

JPEG clear flag register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

JPEG_CFR JPEG_CFR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CEOCF CHPDF

CEOCF : Clear End of Conversion Flag
bits : 5 - 5 (1 bit)

CHPDF : Clear Header Parsing Done Flag
bits : 6 - 6 (1 bit)


DHTMEM9

JPEG DHTMem tables
address_offset : 0x380 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM9 DHTMEM9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM10

JPEG DHTMem tables
address_offset : 0x384 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM10 DHTMEM10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM11

JPEG DHTMem tables
address_offset : 0x388 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM11 DHTMEM11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM12

JPEG DHTMem tables
address_offset : 0x38C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM12 DHTMEM12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM13

JPEG DHTMem tables
address_offset : 0x390 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM13 DHTMEM13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM14

JPEG DHTMem tables
address_offset : 0x394 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM14 DHTMEM14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM15

JPEG DHTMem tables
address_offset : 0x398 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM15 DHTMEM15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM16

JPEG DHTMem tables
address_offset : 0x39C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM16 DHTMEM16 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM17

JPEG DHTMem tables
address_offset : 0x3A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM17 DHTMEM17 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM18

JPEG DHTMem tables
address_offset : 0x3A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM18 DHTMEM18 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM19

JPEG DHTMem tables
address_offset : 0x3A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM19 DHTMEM19 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM20

JPEG DHTMem tables
address_offset : 0x3AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM20 DHTMEM20 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM21

JPEG DHTMem tables
address_offset : 0x3B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM21 DHTMEM21 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM22

JPEG DHTMem tables
address_offset : 0x3B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM22 DHTMEM22 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM23

JPEG DHTMem tables
address_offset : 0x3B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM23 DHTMEM23 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM24

JPEG DHTMem tables
address_offset : 0x3BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM24 DHTMEM24 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM25

JPEG DHTMem tables
address_offset : 0x3C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM25 DHTMEM25 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM26

JPEG DHTMem tables
address_offset : 0x3C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM26 DHTMEM26 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM27

JPEG DHTMem tables
address_offset : 0x3C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM27 DHTMEM27 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM28

JPEG DHTMem tables
address_offset : 0x3CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM28 DHTMEM28 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM29

JPEG DHTMem tables
address_offset : 0x3D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM29 DHTMEM29 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM30

JPEG DHTMem tables
address_offset : 0x3D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM30 DHTMEM30 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM31

JPEG DHTMem tables
address_offset : 0x3D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM31 DHTMEM31 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM32

JPEG DHTMem tables
address_offset : 0x3DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM32 DHTMEM32 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM33

JPEG DHTMem tables
address_offset : 0x3E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM33 DHTMEM33 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM34

JPEG DHTMem tables
address_offset : 0x3E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM34 DHTMEM34 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM35

JPEG DHTMem tables
address_offset : 0x3E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM35 DHTMEM35 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM36

JPEG DHTMem tables
address_offset : 0x3EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM36 DHTMEM36 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM37

JPEG DHTMem tables
address_offset : 0x3F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM37 DHTMEM37 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM38

JPEG DHTMem tables
address_offset : 0x3F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM38 DHTMEM38 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM39

JPEG DHTMem tables
address_offset : 0x3F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM39 DHTMEM39 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM40

JPEG DHTMem tables
address_offset : 0x3FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM40 DHTMEM40 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


JPEG_CONFR1 (CONFR1)

JPEG codec configuration register 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

JPEG_CONFR1 JPEG_CONFR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NF DE COLORSPACE NS HDR YSIZE

NF : Number of color components
bits : 0 - 1 (2 bit)

DE : Decoding Enable
bits : 3 - 3 (1 bit)

COLORSPACE : Color Space
bits : 4 - 5 (2 bit)

NS : Number of components for Scan
bits : 6 - 7 (2 bit)

HDR : Header Processing
bits : 8 - 8 (1 bit)

YSIZE : Y Size
bits : 16 - 31 (16 bit)


JPEG_DIR (DIR)

JPEG data input register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

JPEG_DIR JPEG_DIR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATAIN

DATAIN : Data Input FIFO
bits : 0 - 31 (32 bit)


DHTMEM41

JPEG DHTMem tables
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM41 DHTMEM41 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM42

JPEG DHTMem tables
address_offset : 0x404 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM42 DHTMEM42 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM43

JPEG DHTMem tables
address_offset : 0x408 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM43 DHTMEM43 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM44

JPEG DHTMem tables
address_offset : 0x40C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM44 DHTMEM44 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM45

JPEG DHTMem tables
address_offset : 0x410 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM45 DHTMEM45 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM46

JPEG DHTMem tables
address_offset : 0x414 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM46 DHTMEM46 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM47

JPEG DHTMem tables
address_offset : 0x418 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM47 DHTMEM47 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM48

JPEG DHTMem tables
address_offset : 0x41C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM48 DHTMEM48 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM49

JPEG DHTMem tables
address_offset : 0x420 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM49 DHTMEM49 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM50

JPEG DHTMem tables
address_offset : 0x424 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM50 DHTMEM50 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM51

JPEG DHTMem tables
address_offset : 0x428 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM51 DHTMEM51 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM52

JPEG DHTMem tables
address_offset : 0x42C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM52 DHTMEM52 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM53

JPEG DHTMem tables
address_offset : 0x430 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM53 DHTMEM53 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM54

JPEG DHTMem tables
address_offset : 0x434 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM54 DHTMEM54 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM55

JPEG DHTMem tables
address_offset : 0x438 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM55 DHTMEM55 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM56

JPEG DHTMem tables
address_offset : 0x43C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM56 DHTMEM56 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


JPEG_DOR (DOR)

JPEG data output register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

JPEG_DOR JPEG_DOR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATAOUT

DATAOUT : Data Output FIFO
bits : 0 - 31 (32 bit)


DHTMEM57

JPEG DHTMem tables
address_offset : 0x440 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM57 DHTMEM57 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM58

JPEG DHTMem tables
address_offset : 0x444 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM58 DHTMEM58 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM59

JPEG DHTMem tables
address_offset : 0x448 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM59 DHTMEM59 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM60

JPEG DHTMem tables
address_offset : 0x44C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM60 DHTMEM60 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM61

JPEG DHTMem tables
address_offset : 0x450 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM61 DHTMEM61 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM62

JPEG DHTMem tables
address_offset : 0x454 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM62 DHTMEM62 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM63

JPEG DHTMem tables
address_offset : 0x458 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM63 DHTMEM63 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM64

JPEG DHTMem tables
address_offset : 0x45C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM64 DHTMEM64 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM65

JPEG DHTMem tables
address_offset : 0x460 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM65 DHTMEM65 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM66

JPEG DHTMem tables
address_offset : 0x464 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM66 DHTMEM66 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM67

JPEG DHTMem tables
address_offset : 0x468 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM67 DHTMEM67 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM68

JPEG DHTMem tables
address_offset : 0x46C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM68 DHTMEM68 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM69

JPEG DHTMem tables
address_offset : 0x470 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM69 DHTMEM69 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM70

JPEG DHTMem tables
address_offset : 0x474 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM70 DHTMEM70 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM71

JPEG DHTMem tables
address_offset : 0x478 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM71 DHTMEM71 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM72

JPEG DHTMem tables
address_offset : 0x47C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM72 DHTMEM72 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM73

JPEG DHTMem tables
address_offset : 0x480 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM73 DHTMEM73 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM74

JPEG DHTMem tables
address_offset : 0x484 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM74 DHTMEM74 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM75

JPEG DHTMem tables
address_offset : 0x488 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM75 DHTMEM75 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM76

JPEG DHTMem tables
address_offset : 0x48C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM76 DHTMEM76 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM77

JPEG DHTMem tables
address_offset : 0x490 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM77 DHTMEM77 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM78

JPEG DHTMem tables
address_offset : 0x494 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM78 DHTMEM78 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM79

JPEG DHTMem tables
address_offset : 0x498 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM79 DHTMEM79 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM80

JPEG DHTMem tables
address_offset : 0x49C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM80 DHTMEM80 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM81

JPEG DHTMem tables
address_offset : 0x4A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM81 DHTMEM81 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM82

JPEG DHTMem tables
address_offset : 0x4A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM82 DHTMEM82 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM83

JPEG DHTMem tables
address_offset : 0x4A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM83 DHTMEM83 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM84

JPEG DHTMem tables
address_offset : 0x4AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM84 DHTMEM84 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM85

JPEG DHTMem tables
address_offset : 0x4B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM85 DHTMEM85 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM86

JPEG DHTMem tables
address_offset : 0x4B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM86 DHTMEM86 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM87

JPEG DHTMem tables
address_offset : 0x4B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM87 DHTMEM87 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM88

JPEG DHTMem tables
address_offset : 0x4BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM88 DHTMEM88 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM89

JPEG DHTMem tables
address_offset : 0x4C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM89 DHTMEM89 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM90

JPEG DHTMem tables
address_offset : 0x4C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM90 DHTMEM90 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM91

JPEG DHTMem tables
address_offset : 0x4C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM91 DHTMEM91 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM92

JPEG DHTMem tables
address_offset : 0x4CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM92 DHTMEM92 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM93

JPEG DHTMem tables
address_offset : 0x4D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM93 DHTMEM93 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM94

JPEG DHTMem tables
address_offset : 0x4D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM94 DHTMEM94 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM95

JPEG DHTMem tables
address_offset : 0x4D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM95 DHTMEM95 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM96

JPEG DHTMem tables
address_offset : 0x4DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM96 DHTMEM96 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM97

JPEG DHTMem tables
address_offset : 0x4E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM97 DHTMEM97 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM98

JPEG DHTMem tables
address_offset : 0x4E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM98 DHTMEM98 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM99

JPEG DHTMem tables
address_offset : 0x4E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM99 DHTMEM99 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM100

JPEG DHTMem tables
address_offset : 0x4EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM100 DHTMEM100 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM101

JPEG DHTMem tables
address_offset : 0x4F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM101 DHTMEM101 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM102

JPEG DHTMem tables
address_offset : 0x4F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM102 DHTMEM102 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


DHTMEM103

JPEG DHTMem tables
address_offset : 0x4F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DHTMEM103 DHTMEM103 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


QMEM0_0

JPEG quantization tables
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QMEM0_0 QMEM0_0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QMem_RAM

QMem_RAM : QMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC0_0

JPEG encoder, AC Huffman table 0
address_offset : 0x500 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC0_0 HUFFENC_AC0_0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC0_1

JPEG encoder, AC Huffman table 0
address_offset : 0x504 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC0_1 HUFFENC_AC0_1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC0_2

JPEG encoder, AC Huffman table 0
address_offset : 0x508 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC0_2 HUFFENC_AC0_2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC0_3

JPEG encoder, AC Huffman table 0
address_offset : 0x50C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC0_3 HUFFENC_AC0_3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC0_4

JPEG encoder, AC Huffman table 0
address_offset : 0x510 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC0_4 HUFFENC_AC0_4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC0_5

JPEG encoder, AC Huffman table 0
address_offset : 0x514 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC0_5 HUFFENC_AC0_5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC0_6

JPEG encoder, AC Huffman table 0
address_offset : 0x518 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC0_6 HUFFENC_AC0_6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC0_7

JPEG encoder, AC Huffman table 0
address_offset : 0x51C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC0_7 HUFFENC_AC0_7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC0_8

JPEG encoder, AC Huffman table 0
address_offset : 0x520 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC0_8 HUFFENC_AC0_8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC0_9

JPEG encoder, AC Huffman table 0
address_offset : 0x524 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC0_9 HUFFENC_AC0_9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC0_10

JPEG encoder, AC Huffman table 0
address_offset : 0x528 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC0_10 HUFFENC_AC0_10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC0_11

JPEG encoder, AC Huffman table 0
address_offset : 0x52C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC0_11 HUFFENC_AC0_11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC0_12

JPEG encoder, AC Huffman table 0
address_offset : 0x530 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC0_12 HUFFENC_AC0_12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC0_13

JPEG encoder, AC Huffman table 0
address_offset : 0x534 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC0_13 HUFFENC_AC0_13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC0_14

JPEG encoder, AC Huffman table 0
address_offset : 0x538 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC0_14 HUFFENC_AC0_14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC0_15

JPEG encoder, AC Huffman table 0
address_offset : 0x53C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC0_15 HUFFENC_AC0_15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


QMEM0_1

JPEG quantization tables
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QMEM0_1 QMEM0_1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QMem_RAM

QMem_RAM : QMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC0_16

JPEG encoder, AC Huffman table 0
address_offset : 0x540 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC0_16 HUFFENC_AC0_16 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC0_17

JPEG encoder, AC Huffman table 0
address_offset : 0x544 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC0_17 HUFFENC_AC0_17 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC0_18

JPEG encoder, AC Huffman table 0
address_offset : 0x548 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC0_18 HUFFENC_AC0_18 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC0_19

JPEG encoder, AC Huffman table 0
address_offset : 0x54C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC0_19 HUFFENC_AC0_19 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC0_20

JPEG encoder, AC Huffman table 0
address_offset : 0x550 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC0_20 HUFFENC_AC0_20 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC0_21

JPEG encoder, AC Huffman table 0
address_offset : 0x554 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC0_21 HUFFENC_AC0_21 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC0_22

JPEG encoder, AC Huffman table 0
address_offset : 0x558 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC0_22 HUFFENC_AC0_22 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC0_23

JPEG encoder, AC Huffman table 0
address_offset : 0x55C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC0_23 HUFFENC_AC0_23 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC0_24

JPEG encoder, AC Huffman table 0
address_offset : 0x560 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC0_24 HUFFENC_AC0_24 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC0_25

JPEG encoder, AC Huffman table 0
address_offset : 0x564 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC0_25 HUFFENC_AC0_25 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC0_26

JPEG encoder, AC Huffman table 0
address_offset : 0x568 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC0_26 HUFFENC_AC0_26 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC0_27

JPEG encoder, AC Huffman table 0
address_offset : 0x56C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC0_27 HUFFENC_AC0_27 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC0_28

JPEG encoder, AC Huffman table 0
address_offset : 0x570 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC0_28 HUFFENC_AC0_28 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC0_29

JPEG encoder, AC Huffman table 0
address_offset : 0x574 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC0_29 HUFFENC_AC0_29 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC0_30

JPEG encoder, AC Huffman table 0
address_offset : 0x578 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC0_30 HUFFENC_AC0_30 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC0_31

JPEG encoder, AC Huffman table 0
address_offset : 0x57C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC0_31 HUFFENC_AC0_31 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


QMEM0_2

JPEG quantization tables
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QMEM0_2 QMEM0_2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QMem_RAM

QMem_RAM : QMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC0_32

JPEG encoder, AC Huffman table 0
address_offset : 0x580 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC0_32 HUFFENC_AC0_32 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC0_33

JPEG encoder, AC Huffman table 0
address_offset : 0x584 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC0_33 HUFFENC_AC0_33 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC0_34

JPEG encoder, AC Huffman table 0
address_offset : 0x588 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC0_34 HUFFENC_AC0_34 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC0_35

JPEG encoder, AC Huffman table 0
address_offset : 0x58C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC0_35 HUFFENC_AC0_35 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC0_36

JPEG encoder, AC Huffman table 0
address_offset : 0x590 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC0_36 HUFFENC_AC0_36 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC0_37

JPEG encoder, AC Huffman table 0
address_offset : 0x594 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC0_37 HUFFENC_AC0_37 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC0_38

JPEG encoder, AC Huffman table 0
address_offset : 0x598 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC0_38 HUFFENC_AC0_38 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC0_39

JPEG encoder, AC Huffman table 0
address_offset : 0x59C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC0_39 HUFFENC_AC0_39 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC0_40

JPEG encoder, AC Huffman table 0
address_offset : 0x5A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC0_40 HUFFENC_AC0_40 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC0_41

JPEG encoder, AC Huffman table 0
address_offset : 0x5A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC0_41 HUFFENC_AC0_41 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC0_42

JPEG encoder, AC Huffman table 0
address_offset : 0x5A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC0_42 HUFFENC_AC0_42 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC0_43

JPEG encoder, AC Huffman table 0
address_offset : 0x5AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC0_43 HUFFENC_AC0_43 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC0_44

JPEG encoder, AC Huffman table 0
address_offset : 0x5B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC0_44 HUFFENC_AC0_44 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC0_45

JPEG encoder, AC Huffman table 0
address_offset : 0x5B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC0_45 HUFFENC_AC0_45 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC0_46

JPEG encoder, AC Huffman table 0
address_offset : 0x5B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC0_46 HUFFENC_AC0_46 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC0_47

JPEG encoder, AC Huffman table 0
address_offset : 0x5BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC0_47 HUFFENC_AC0_47 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


QMEM0_3

JPEG quantization tables
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QMEM0_3 QMEM0_3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QMem_RAM

QMem_RAM : QMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC0_48

JPEG encoder, AC Huffman table 0
address_offset : 0x5C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC0_48 HUFFENC_AC0_48 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC0_49

JPEG encoder, AC Huffman table 0
address_offset : 0x5C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC0_49 HUFFENC_AC0_49 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC0_50

JPEG encoder, AC Huffman table 0
address_offset : 0x5C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC0_50 HUFFENC_AC0_50 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC0_51

JPEG encoder, AC Huffman table 0
address_offset : 0x5CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC0_51 HUFFENC_AC0_51 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC0_52

JPEG encoder, AC Huffman table 0
address_offset : 0x5D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC0_52 HUFFENC_AC0_52 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC0_53

JPEG encoder, AC Huffman table 0
address_offset : 0x5D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC0_53 HUFFENC_AC0_53 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC0_54

JPEG encoder, AC Huffman table 0
address_offset : 0x5D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC0_54 HUFFENC_AC0_54 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC0_55

JPEG encoder, AC Huffman table 0
address_offset : 0x5DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC0_55 HUFFENC_AC0_55 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC0_56

JPEG encoder, AC Huffman table 0
address_offset : 0x5E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC0_56 HUFFENC_AC0_56 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC0_57

JPEG encoder, AC Huffman table 0
address_offset : 0x5E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC0_57 HUFFENC_AC0_57 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC0_58

JPEG encoder, AC Huffman table 0
address_offset : 0x5E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC0_58 HUFFENC_AC0_58 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC0_59

JPEG encoder, AC Huffman table 0
address_offset : 0x5EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC0_59 HUFFENC_AC0_59 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC0_60

JPEG encoder, AC Huffman table 0
address_offset : 0x5F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC0_60 HUFFENC_AC0_60 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC0_61

JPEG encoder, AC Huffman table 0
address_offset : 0x5F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC0_61 HUFFENC_AC0_61 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC0_62

JPEG encoder, AC Huffman table 0
address_offset : 0x5F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC0_62 HUFFENC_AC0_62 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC0_63

JPEG encoder, AC Huffman table 0
address_offset : 0x5FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC0_63 HUFFENC_AC0_63 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


QMEM0_4

JPEG quantization tables
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QMEM0_4 QMEM0_4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QMem_RAM

QMem_RAM : QMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC0_64

JPEG encoder, AC Huffman table 0
address_offset : 0x600 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC0_64 HUFFENC_AC0_64 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC0_65

JPEG encoder, AC Huffman table 0
address_offset : 0x604 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC0_65 HUFFENC_AC0_65 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC0_66

JPEG encoder, AC Huffman table 0
address_offset : 0x608 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC0_66 HUFFENC_AC0_66 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC0_67

JPEG encoder, AC Huffman table 0
address_offset : 0x60C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC0_67 HUFFENC_AC0_67 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC0_68

JPEG encoder, AC Huffman table 0
address_offset : 0x610 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC0_68 HUFFENC_AC0_68 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC0_69

JPEG encoder, AC Huffman table 0
address_offset : 0x614 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC0_69 HUFFENC_AC0_69 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC0_70

JPEG encoder, AC Huffman table 0
address_offset : 0x618 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC0_70 HUFFENC_AC0_70 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC0_71

JPEG encoder, AC Huffman table 0
address_offset : 0x61C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC0_71 HUFFENC_AC0_71 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC0_72

JPEG encoder, AC Huffman table 0
address_offset : 0x620 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC0_72 HUFFENC_AC0_72 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC0_73

JPEG encoder, AC Huffman table 0
address_offset : 0x624 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC0_73 HUFFENC_AC0_73 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC0_74

JPEG encoder, AC Huffman table 0
address_offset : 0x628 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC0_74 HUFFENC_AC0_74 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC0_75

JPEG encoder, AC Huffman table 0
address_offset : 0x62C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC0_75 HUFFENC_AC0_75 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC0_76

JPEG encoder, AC Huffman table 0
address_offset : 0x630 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC0_76 HUFFENC_AC0_76 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC0_77

JPEG encoder, AC Huffman table 0
address_offset : 0x634 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC0_77 HUFFENC_AC0_77 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC0_78

JPEG encoder, AC Huffman table 0
address_offset : 0x638 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC0_78 HUFFENC_AC0_78 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC0_79

JPEG encoder, AC Huffman table 0
address_offset : 0x63C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC0_79 HUFFENC_AC0_79 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


QMEM0_5

JPEG quantization tables
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QMEM0_5 QMEM0_5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QMem_RAM

QMem_RAM : QMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC0_80

JPEG encoder, AC Huffman table 0
address_offset : 0x640 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC0_80 HUFFENC_AC0_80 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC0_81

JPEG encoder, AC Huffman table 0
address_offset : 0x644 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC0_81 HUFFENC_AC0_81 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC0_82

JPEG encoder, AC Huffman table 0
address_offset : 0x648 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC0_82 HUFFENC_AC0_82 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC0_83

JPEG encoder, AC Huffman table 0
address_offset : 0x64C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC0_83 HUFFENC_AC0_83 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC0_84

JPEG encoder, AC Huffman table 0
address_offset : 0x650 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC0_84 HUFFENC_AC0_84 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC0_85

JPEG encoder, AC Huffman table 0
address_offset : 0x654 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC0_85 HUFFENC_AC0_85 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC0_86

JPEG encoder, AC Huffman table 0
address_offset : 0x658 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC0_86 HUFFENC_AC0_86 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC0_87

JPEG encoder, AC Huffman table 0
address_offset : 0x65C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC0_87 HUFFENC_AC0_87 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC1_0

JPEG encoder, AC Huffman table 1
address_offset : 0x660 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC1_0 HUFFENC_AC1_0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC1_1

JPEG encoder, AC Huffman table 1
address_offset : 0x664 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC1_1 HUFFENC_AC1_1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC1_2

JPEG encoder, AC Huffman table 1
address_offset : 0x668 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC1_2 HUFFENC_AC1_2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC1_3

JPEG encoder, AC Huffman table 1
address_offset : 0x66C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC1_3 HUFFENC_AC1_3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC1_4

JPEG encoder, AC Huffman table 1
address_offset : 0x670 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC1_4 HUFFENC_AC1_4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC1_5

JPEG encoder, AC Huffman table 1
address_offset : 0x674 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC1_5 HUFFENC_AC1_5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC1_6

JPEG encoder, AC Huffman table 1
address_offset : 0x678 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC1_6 HUFFENC_AC1_6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC1_7

JPEG encoder, AC Huffman table 1
address_offset : 0x67C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC1_7 HUFFENC_AC1_7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


QMEM0_6

JPEG quantization tables
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QMEM0_6 QMEM0_6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QMem_RAM

QMem_RAM : QMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC1_8

JPEG encoder, AC Huffman table 1
address_offset : 0x680 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC1_8 HUFFENC_AC1_8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC1_9

JPEG encoder, AC Huffman table 1
address_offset : 0x684 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC1_9 HUFFENC_AC1_9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC1_10

JPEG encoder, AC Huffman table 1
address_offset : 0x688 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC1_10 HUFFENC_AC1_10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC1_11

JPEG encoder, AC Huffman table 1
address_offset : 0x68C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC1_11 HUFFENC_AC1_11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC1_12

JPEG encoder, AC Huffman table 1
address_offset : 0x690 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC1_12 HUFFENC_AC1_12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC1_13

JPEG encoder, AC Huffman table 1
address_offset : 0x694 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC1_13 HUFFENC_AC1_13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC1_14

JPEG encoder, AC Huffman table 1
address_offset : 0x698 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC1_14 HUFFENC_AC1_14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC1_15

JPEG encoder, AC Huffman table 1
address_offset : 0x69C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC1_15 HUFFENC_AC1_15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC1_16

JPEG encoder, AC Huffman table 1
address_offset : 0x6A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC1_16 HUFFENC_AC1_16 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC1_17

JPEG encoder, AC Huffman table 1
address_offset : 0x6A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC1_17 HUFFENC_AC1_17 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC1_18

JPEG encoder, AC Huffman table 1
address_offset : 0x6A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC1_18 HUFFENC_AC1_18 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC1_19

JPEG encoder, AC Huffman table 1
address_offset : 0x6AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC1_19 HUFFENC_AC1_19 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC1_20

JPEG encoder, AC Huffman table 1
address_offset : 0x6B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC1_20 HUFFENC_AC1_20 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC1_21

JPEG encoder, AC Huffman table 1
address_offset : 0x6B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC1_21 HUFFENC_AC1_21 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC1_22

JPEG encoder, AC Huffman table 1
address_offset : 0x6B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC1_22 HUFFENC_AC1_22 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC1_23

JPEG encoder, AC Huffman table 1
address_offset : 0x6BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC1_23 HUFFENC_AC1_23 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


QMEM0_7

JPEG quantization tables
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QMEM0_7 QMEM0_7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QMem_RAM

QMem_RAM : QMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC1_24

JPEG encoder, AC Huffman table 1
address_offset : 0x6C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC1_24 HUFFENC_AC1_24 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC1_25

JPEG encoder, AC Huffman table 1
address_offset : 0x6C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC1_25 HUFFENC_AC1_25 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC1_26

JPEG encoder, AC Huffman table 1
address_offset : 0x6C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC1_26 HUFFENC_AC1_26 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC1_27

JPEG encoder, AC Huffman table 1
address_offset : 0x6CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC1_27 HUFFENC_AC1_27 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC1_28

JPEG encoder, AC Huffman table 1
address_offset : 0x6D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC1_28 HUFFENC_AC1_28 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC1_29

JPEG encoder, AC Huffman table 1
address_offset : 0x6D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC1_29 HUFFENC_AC1_29 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC1_30

JPEG encoder, AC Huffman table 1
address_offset : 0x6D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC1_30 HUFFENC_AC1_30 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC1_31

JPEG encoder, AC Huffman table 1
address_offset : 0x6DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC1_31 HUFFENC_AC1_31 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC1_32

JPEG encoder, AC Huffman table 1
address_offset : 0x6E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC1_32 HUFFENC_AC1_32 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC1_33

JPEG encoder, AC Huffman table 1
address_offset : 0x6E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC1_33 HUFFENC_AC1_33 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC1_34

JPEG encoder, AC Huffman table 1
address_offset : 0x6E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC1_34 HUFFENC_AC1_34 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC1_35

JPEG encoder, AC Huffman table 1
address_offset : 0x6EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC1_35 HUFFENC_AC1_35 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC1_36

JPEG encoder, AC Huffman table 1
address_offset : 0x6F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC1_36 HUFFENC_AC1_36 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC1_37

JPEG encoder, AC Huffman table 1
address_offset : 0x6F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC1_37 HUFFENC_AC1_37 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC1_38

JPEG encoder, AC Huffman table 1
address_offset : 0x6F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC1_38 HUFFENC_AC1_38 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC1_39

JPEG encoder, AC Huffman table 1
address_offset : 0x6FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC1_39 HUFFENC_AC1_39 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


QMEM0_8

JPEG quantization tables
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QMEM0_8 QMEM0_8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QMem_RAM

QMem_RAM : QMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC1_40

JPEG encoder, AC Huffman table 1
address_offset : 0x700 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC1_40 HUFFENC_AC1_40 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC1_41

JPEG encoder, AC Huffman table 1
address_offset : 0x704 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC1_41 HUFFENC_AC1_41 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC1_42

JPEG encoder, AC Huffman table 1
address_offset : 0x708 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC1_42 HUFFENC_AC1_42 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC1_43

JPEG encoder, AC Huffman table 1
address_offset : 0x70C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC1_43 HUFFENC_AC1_43 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC1_44

JPEG encoder, AC Huffman table 1
address_offset : 0x710 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC1_44 HUFFENC_AC1_44 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC1_45

JPEG encoder, AC Huffman table 1
address_offset : 0x714 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC1_45 HUFFENC_AC1_45 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC1_46

JPEG encoder, AC Huffman table 1
address_offset : 0x718 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC1_46 HUFFENC_AC1_46 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC1_47

JPEG encoder, AC Huffman table 1
address_offset : 0x71C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC1_47 HUFFENC_AC1_47 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC1_48

JPEG encoder, AC Huffman table 1
address_offset : 0x720 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC1_48 HUFFENC_AC1_48 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC1_49

JPEG encoder, AC Huffman table 1
address_offset : 0x724 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC1_49 HUFFENC_AC1_49 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC1_50

JPEG encoder, AC Huffman table 1
address_offset : 0x728 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC1_50 HUFFENC_AC1_50 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC1_51

JPEG encoder, AC Huffman table 1
address_offset : 0x72C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC1_51 HUFFENC_AC1_51 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC1_52

JPEG encoder, AC Huffman table 1
address_offset : 0x730 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC1_52 HUFFENC_AC1_52 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC1_53

JPEG encoder, AC Huffman table 1
address_offset : 0x734 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC1_53 HUFFENC_AC1_53 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC1_54

JPEG encoder, AC Huffman table 1
address_offset : 0x738 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC1_54 HUFFENC_AC1_54 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC1_55

JPEG encoder, AC Huffman table 1
address_offset : 0x73C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC1_55 HUFFENC_AC1_55 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


QMEM0_9

JPEG quantization tables
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QMEM0_9 QMEM0_9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QMem_RAM

QMem_RAM : QMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC1_56

JPEG encoder, AC Huffman table 1
address_offset : 0x740 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC1_56 HUFFENC_AC1_56 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC1_57

JPEG encoder, AC Huffman table 1
address_offset : 0x744 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC1_57 HUFFENC_AC1_57 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC1_58

JPEG encoder, AC Huffman table 1
address_offset : 0x748 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC1_58 HUFFENC_AC1_58 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC1_59

JPEG encoder, AC Huffman table 1
address_offset : 0x74C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC1_59 HUFFENC_AC1_59 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC1_60

JPEG encoder, AC Huffman table 1
address_offset : 0x750 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC1_60 HUFFENC_AC1_60 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC1_61

JPEG encoder, AC Huffman table 1
address_offset : 0x754 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC1_61 HUFFENC_AC1_61 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC1_62

JPEG encoder, AC Huffman table 1
address_offset : 0x758 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC1_62 HUFFENC_AC1_62 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC1_63

JPEG encoder, AC Huffman table 1
address_offset : 0x75C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC1_63 HUFFENC_AC1_63 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC1_64

JPEG encoder, AC Huffman table 1
address_offset : 0x760 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC1_64 HUFFENC_AC1_64 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC1_65

JPEG encoder, AC Huffman table 1
address_offset : 0x764 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC1_65 HUFFENC_AC1_65 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC1_66

JPEG encoder, AC Huffman table 1
address_offset : 0x768 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC1_66 HUFFENC_AC1_66 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC1_67

JPEG encoder, AC Huffman table 1
address_offset : 0x76C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC1_67 HUFFENC_AC1_67 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC1_68

JPEG encoder, AC Huffman table 1
address_offset : 0x770 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC1_68 HUFFENC_AC1_68 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC1_69

JPEG encoder, AC Huffman table 1
address_offset : 0x774 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC1_69 HUFFENC_AC1_69 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC1_70

JPEG encoder, AC Huffman table 1
address_offset : 0x778 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC1_70 HUFFENC_AC1_70 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC1_71

JPEG encoder, AC Huffman table 1
address_offset : 0x77C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC1_71 HUFFENC_AC1_71 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


QMEM0_10

JPEG quantization tables
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QMEM0_10 QMEM0_10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QMem_RAM

QMem_RAM : QMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC1_72

JPEG encoder, AC Huffman table 1
address_offset : 0x780 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC1_72 HUFFENC_AC1_72 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC1_73

JPEG encoder, AC Huffman table 1
address_offset : 0x784 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC1_73 HUFFENC_AC1_73 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC1_74

JPEG encoder, AC Huffman table 1
address_offset : 0x788 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC1_74 HUFFENC_AC1_74 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC1_75

JPEG encoder, AC Huffman table 1
address_offset : 0x78C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC1_75 HUFFENC_AC1_75 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC1_76

JPEG encoder, AC Huffman table 1
address_offset : 0x790 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC1_76 HUFFENC_AC1_76 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC1_77

JPEG encoder, AC Huffman table 1
address_offset : 0x794 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC1_77 HUFFENC_AC1_77 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC1_78

JPEG encoder, AC Huffman table 1
address_offset : 0x798 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC1_78 HUFFENC_AC1_78 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC1_79

JPEG encoder, AC Huffman table 1
address_offset : 0x79C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC1_79 HUFFENC_AC1_79 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC1_80

JPEG encoder, AC Huffman table 1
address_offset : 0x7A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC1_80 HUFFENC_AC1_80 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC1_81

JPEG encoder, AC Huffman table 1
address_offset : 0x7A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC1_81 HUFFENC_AC1_81 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC1_82

JPEG encoder, AC Huffman table 1
address_offset : 0x7A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC1_82 HUFFENC_AC1_82 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC1_83

JPEG encoder, AC Huffman table 1
address_offset : 0x7AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC1_83 HUFFENC_AC1_83 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC1_84

JPEG encoder, AC Huffman table 1
address_offset : 0x7B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC1_84 HUFFENC_AC1_84 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC1_85

JPEG encoder, AC Huffman table 1
address_offset : 0x7B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC1_85 HUFFENC_AC1_85 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC1_86

JPEG encoder, AC Huffman table 1
address_offset : 0x7B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC1_86 HUFFENC_AC1_86 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_AC1_87

JPEG encoder, AC Huffman table 1
address_offset : 0x7BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_AC1_87 HUFFENC_AC1_87 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


QMEM0_11

JPEG quantization tables
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QMEM0_11 QMEM0_11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QMem_RAM

QMem_RAM : QMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_DC0_0

JPEG encoder, DC Huffman table 0
address_offset : 0x7C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_DC0_0 HUFFENC_DC0_0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_DC0_1

JPEG encoder, DC Huffman table 0
address_offset : 0x7C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_DC0_1 HUFFENC_DC0_1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_DC0_2

JPEG encoder, DC Huffman table 0
address_offset : 0x7C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_DC0_2 HUFFENC_DC0_2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_DC0_3

JPEG encoder, DC Huffman table 0
address_offset : 0x7CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_DC0_3 HUFFENC_DC0_3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_DC0_4

JPEG encoder, DC Huffman table 0
address_offset : 0x7D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_DC0_4 HUFFENC_DC0_4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_DC0_5

JPEG encoder, DC Huffman table 0
address_offset : 0x7D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_DC0_5 HUFFENC_DC0_5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_DC0_6

JPEG encoder, DC Huffman table 0
address_offset : 0x7D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_DC0_6 HUFFENC_DC0_6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_DC0_7

JPEG encoder, DC Huffman table 0
address_offset : 0x7DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_DC0_7 HUFFENC_DC0_7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_DC1_0

JPEG encoder, DC Huffman table 1
address_offset : 0x7E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_DC1_0 HUFFENC_DC1_0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_DC1_1

JPEG encoder, DC Huffman table 1
address_offset : 0x7E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_DC1_1 HUFFENC_DC1_1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_DC1_2

JPEG encoder, DC Huffman table 1
address_offset : 0x7E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_DC1_2 HUFFENC_DC1_2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_DC1_3

JPEG encoder, DC Huffman table 1
address_offset : 0x7EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_DC1_3 HUFFENC_DC1_3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_DC1_4

JPEG encoder, DC Huffman table 1
address_offset : 0x7F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_DC1_4 HUFFENC_DC1_4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_DC1_5

JPEG encoder, DC Huffman table 1
address_offset : 0x7F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_DC1_5 HUFFENC_DC1_5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_DC1_6

JPEG encoder, DC Huffman table 1
address_offset : 0x7F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_DC1_6 HUFFENC_DC1_6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


HUFFENC_DC1_7

JPEG encoder, DC Huffman table 1
address_offset : 0x7FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HUFFENC_DC1_7 HUFFENC_DC1_7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DHTMem_RAM

DHTMem_RAM : DHTMem RAM
bits : 0 - 31 (32 bit)


JPEG_CONFR2 (CONFR2)

JPEG codec configuration register 2
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

JPEG_CONFR2 JPEG_CONFR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NMCU

NMCU : Number of MCU
bits : 0 - 25 (26 bit)


QMEM0_12

JPEG quantization tables
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QMEM0_12 QMEM0_12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QMem_RAM

QMem_RAM : QMem RAM
bits : 0 - 31 (32 bit)


QMEM0_13

JPEG quantization tables
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QMEM0_13 QMEM0_13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QMem_RAM

QMem_RAM : QMem RAM
bits : 0 - 31 (32 bit)


QMEM0_14

JPEG quantization tables
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QMEM0_14 QMEM0_14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QMem_RAM

QMem_RAM : QMem RAM
bits : 0 - 31 (32 bit)


QMEM0_15

JPEG quantization tables
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QMEM0_15 QMEM0_15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QMem_RAM

QMem_RAM : QMem RAM
bits : 0 - 31 (32 bit)


QMEM1_0

JPEG quantization tables
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QMEM1_0 QMEM1_0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QMem_RAM

QMem_RAM : QMem RAM
bits : 0 - 31 (32 bit)


QMEM1_1

JPEG quantization tables
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QMEM1_1 QMEM1_1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QMem_RAM

QMem_RAM : QMem RAM
bits : 0 - 31 (32 bit)


QMEM1_2

JPEG quantization tables
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QMEM1_2 QMEM1_2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QMem_RAM

QMem_RAM : QMem RAM
bits : 0 - 31 (32 bit)


QMEM1_3

JPEG quantization tables
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QMEM1_3 QMEM1_3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QMem_RAM

QMem_RAM : QMem RAM
bits : 0 - 31 (32 bit)


QMEM1_4

JPEG quantization tables
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QMEM1_4 QMEM1_4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QMem_RAM

QMem_RAM : QMem RAM
bits : 0 - 31 (32 bit)


QMEM1_5

JPEG quantization tables
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QMEM1_5 QMEM1_5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QMem_RAM

QMem_RAM : QMem RAM
bits : 0 - 31 (32 bit)


QMEM1_6

JPEG quantization tables
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QMEM1_6 QMEM1_6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QMem_RAM

QMem_RAM : QMem RAM
bits : 0 - 31 (32 bit)


QMEM1_7

JPEG quantization tables
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QMEM1_7 QMEM1_7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QMem_RAM

QMem_RAM : QMem RAM
bits : 0 - 31 (32 bit)


QMEM1_8

JPEG quantization tables
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QMEM1_8 QMEM1_8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QMem_RAM

QMem_RAM : QMem RAM
bits : 0 - 31 (32 bit)


QMEM1_9

JPEG quantization tables
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QMEM1_9 QMEM1_9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QMem_RAM

QMem_RAM : QMem RAM
bits : 0 - 31 (32 bit)


QMEM1_10

JPEG quantization tables
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QMEM1_10 QMEM1_10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QMem_RAM

QMem_RAM : QMem RAM
bits : 0 - 31 (32 bit)


QMEM1_11

JPEG quantization tables
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QMEM1_11 QMEM1_11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QMem_RAM

QMem_RAM : QMem RAM
bits : 0 - 31 (32 bit)


JPEG_CONFR3 (CONFR3)

JPEG codec configuration register 3
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

JPEG_CONFR3 JPEG_CONFR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XSIZE

XSIZE : X size
bits : 16 - 31 (16 bit)


QMEM1_12

JPEG quantization tables
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QMEM1_12 QMEM1_12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QMem_RAM

QMem_RAM : QMem RAM
bits : 0 - 31 (32 bit)


QMEM1_13

JPEG quantization tables
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QMEM1_13 QMEM1_13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QMem_RAM

QMem_RAM : QMem RAM
bits : 0 - 31 (32 bit)


QMEM1_14

JPEG quantization tables
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QMEM1_14 QMEM1_14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QMem_RAM

QMem_RAM : QMem RAM
bits : 0 - 31 (32 bit)


QMEM1_15

JPEG quantization tables
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QMEM1_15 QMEM1_15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QMem_RAM

QMem_RAM : QMem RAM
bits : 0 - 31 (32 bit)


QMEM2_0

JPEG quantization tables
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QMEM2_0 QMEM2_0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QMem_RAM

QMem_RAM : QMem RAM
bits : 0 - 31 (32 bit)


QMEM2_1

JPEG quantization tables
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QMEM2_1 QMEM2_1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QMem_RAM

QMem_RAM : QMem RAM
bits : 0 - 31 (32 bit)


QMEM2_2

JPEG quantization tables
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QMEM2_2 QMEM2_2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QMem_RAM

QMem_RAM : QMem RAM
bits : 0 - 31 (32 bit)


QMEM2_3

JPEG quantization tables
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QMEM2_3 QMEM2_3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QMem_RAM

QMem_RAM : QMem RAM
bits : 0 - 31 (32 bit)


QMEM2_4

JPEG quantization tables
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QMEM2_4 QMEM2_4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QMem_RAM

QMem_RAM : QMem RAM
bits : 0 - 31 (32 bit)


QMEM2_5

JPEG quantization tables
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QMEM2_5 QMEM2_5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QMem_RAM

QMem_RAM : QMem RAM
bits : 0 - 31 (32 bit)


QMEM2_6

JPEG quantization tables
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QMEM2_6 QMEM2_6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QMem_RAM

QMem_RAM : QMem RAM
bits : 0 - 31 (32 bit)


QMEM2_7

JPEG quantization tables
address_offset : 0xEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QMEM2_7 QMEM2_7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QMem_RAM

QMem_RAM : QMem RAM
bits : 0 - 31 (32 bit)


QMEM2_8

JPEG quantization tables
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QMEM2_8 QMEM2_8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QMem_RAM

QMem_RAM : QMem RAM
bits : 0 - 31 (32 bit)


QMEM2_9

JPEG quantization tables
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QMEM2_9 QMEM2_9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QMem_RAM

QMem_RAM : QMem RAM
bits : 0 - 31 (32 bit)


QMEM2_10

JPEG quantization tables
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QMEM2_10 QMEM2_10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QMem_RAM

QMem_RAM : QMem RAM
bits : 0 - 31 (32 bit)


QMEM2_11

JPEG quantization tables
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QMEM2_11 QMEM2_11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QMem_RAM

QMem_RAM : QMem RAM
bits : 0 - 31 (32 bit)



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