\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIFF : Differential Mode
bits : 0 - 0 (1 bit)
access : read-write
SINEMODE : Sine Mode
bits : 1 - 1 (1 bit)
access : read-write
CONVMODE : Conversion Mode
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0x00000000 : CONTINUOUS
DAC is set in continuous mode
0x00000001 : SAMPLEHOLD
DAC is set in sample/hold mode
0x00000002 : SAMPLEOFF
DAC is set in sample/shut off mode
End of enumeration elements list.
OUTMODE : Output Mode
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x00000000 : DISABLE
DAC output to pin and ADC disabled
0x00000001 : PIN
DAC output to pin enabled. DAC output to ADC disabled
0x00000002 : ADC
DAC output to pin disabled. DAC output to ADC enabled
0x00000003 : PINADC
DAC output to pin and ADC enabled
End of enumeration elements list.
OUTENPRS : PRS Controlled Output Enable
bits : 6 - 6 (1 bit)
access : read-write
CH0PRESCRST : Channel 0 Start Reset Prescaler
bits : 7 - 7 (1 bit)
access : read-write
REFSEL : Reference Selection
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0x00000000 : 1V25
Internal 1.25 V bandgap reference
0x00000001 : 2V5
Internal 2.5 V bandgap reference
0x00000002 : VDD
VDD reference
End of enumeration elements list.
PRESC : Prescaler Setting
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
0x00000000 : NODIVISION
End of enumeration elements list.
REFRSEL : Refresh Interval Select
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
0x00000000 : 8CYCLES
All channels with enabled refresh are refreshed every 8 prescaled cycles
0x00000001 : 16CYCLES
All channels with enabled refresh are refreshed every 16 prescaled cycles
0x00000002 : 32CYCLES
All channels with enabled refresh are refreshed every 32 prescaled cycles
0x00000003 : 64CYCLES
All channels with enabled refresh are refreshed every 64 prescaled cycles
End of enumeration elements list.
Interrupt Enable Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0 : Channel 0 Conversion Complete Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write
CH1 : Channel 1 Conversion Complete Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write
CH0UF : Channel 0 Conversion Data Underflow Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write
CH1UF : Channel 1 Conversion Data Underflow Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write
Interrupt Flag Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CH0 : Channel 0 Conversion Complete Interrupt Flag
bits : 0 - 0 (1 bit)
access : read-only
CH1 : Channel 1 Conversion Complete Interrupt Flag
bits : 1 - 1 (1 bit)
access : read-only
CH0UF : Channel 0 Data Underflow Interrupt Flag
bits : 4 - 4 (1 bit)
access : read-only
CH1UF : Channel 1 Data Underflow Interrupt Flag
bits : 5 - 5 (1 bit)
access : read-only
Interrupt Flag Set Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CH0 : Channel 0 Conversion Complete Interrupt Flag Set
bits : 0 - 0 (1 bit)
access : write-only
CH1 : Channel 1 Conversion Complete Interrupt Flag Set
bits : 1 - 1 (1 bit)
access : write-only
CH0UF : Channel 0 Data Underflow Interrupt Flag Set
bits : 4 - 4 (1 bit)
access : write-only
CH1UF : Channel 1 Data Underflow Interrupt Flag Set
bits : 5 - 5 (1 bit)
access : write-only
Interrupt Flag Clear Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CH0 : Channel 0 Conversion Complete Interrupt Flag Clear
bits : 0 - 0 (1 bit)
access : write-only
CH1 : Channel 1 Conversion Complete Interrupt Flag Clear
bits : 1 - 1 (1 bit)
access : write-only
CH0UF : Channel 0 Data Underflow Interrupt Flag Clear
bits : 4 - 4 (1 bit)
access : write-only
CH1UF : Channel 1 Data Underflow Interrupt Flag Clear
bits : 5 - 5 (1 bit)
access : write-only
Channel 0 Data Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Channel 0 Data
bits : 0 - 11 (12 bit)
access : read-write
Channel 1 Data Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Channel 1 Data
bits : 0 - 11 (12 bit)
access : read-write
Combined Data Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CH0DATA : Channel 0 Data
bits : 0 - 11 (12 bit)
access : write-only
CH1DATA : Channel 1 Data
bits : 16 - 27 (12 bit)
access : write-only
Calibration Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0OFFSET : Channel 0 Offset Calibration Value
bits : 0 - 5 (6 bit)
access : read-write
CH1OFFSET : Channel 1 Offset Calibration Value
bits : 8 - 13 (6 bit)
access : read-write
GAIN : Gain Calibration Value
bits : 16 - 22 (7 bit)
access : read-write
Bias Programming Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BIASPROG : Bias Programming Value
bits : 0 - 3 (4 bit)
access : read-write
HALFBIAS : Half Bias Current
bits : 6 - 6 (1 bit)
access : read-write
Status Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CH0DV : Channel 0 Data Valid
bits : 0 - 0 (1 bit)
access : read-only
CH1DV : Channel 1 Data Valid
bits : 1 - 1 (1 bit)
access : read-only
Channel 0 Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Channel 0 Enable
bits : 0 - 0 (1 bit)
access : read-write
REFREN : Channel 0 Automatic Refresh Enable
bits : 1 - 1 (1 bit)
access : read-write
PRSEN : Channel 0 PRS Trigger Enable
bits : 2 - 2 (1 bit)
access : read-write
PRSSEL : Channel 0 PRS Trigger Select
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0x00000000 : PRSCH0
PRS ch 0 triggers channel 0 conversion.
0x00000001 : PRSCH1
PRS ch 1 triggers channel 0 conversion.
0x00000002 : PRSCH2
PRS ch 2 triggers channel 0 conversion.
0x00000003 : PRSCH3
PRS ch 3 triggers channel 0 conversion.
0x00000004 : PRSCH4
PRS ch 4 triggers channel 0 conversion.
0x00000005 : PRSCH5
PRS ch 5 triggers channel 0 conversion.
0x00000006 : PRSCH6
PRS ch 6 triggers channel 0 conversion.
0x00000007 : PRSCH7
PRS ch 7 triggers channel 0 conversion.
End of enumeration elements list.
Channel 1 Control Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Channel 1 Enable
bits : 0 - 0 (1 bit)
access : read-write
REFREN : Channel 1 Automatic Refresh Enable
bits : 1 - 1 (1 bit)
access : read-write
PRSEN : Channel 1 PRS Trigger Enable
bits : 2 - 2 (1 bit)
access : read-write
PRSSEL : Channel 1 PRS Trigger Select
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0x00000000 : PRSCH0
PRS ch 0 triggers channel 1 conversion.
0x00000001 : PRSCH1
PRS ch 1 triggers channel 1 conversion.
0x00000002 : PRSCH2
PRS ch 2 triggers channel 1 conversion.
0x00000003 : PRSCH3
PRS ch 3 triggers channel 1 conversion.
0x00000004 : PRSCH4
PRS ch 4 triggers channel 1 conversion.
0x00000005 : PRSCH5
PRS ch 5 triggers channel 1 conversion.
0x00000006 : PRSCH6
PRS ch 6 triggers channel 1 conversion.
0x00000007 : PRSCH7
PRS ch 7 triggers channel 1 conversion.
End of enumeration elements list.
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.