Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
DFSDM_FLT0CNVTIMR (FLT0CNVTIMR)
DFSDM_FLT1CNVTIMR (FLT1CNVTIMR)
DFSDM_FLT2CNVTIMR (FLT2CNVTIMR)
DFSDM_FLT3CNVTIMR (FLT3CNVTIMR)
channel configuration y register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SITP : SITP
bits : 0 - 1 (2 bit)
SPICKSEL : SPICKSEL
bits : 2 - 3 (2 bit)
SCDEN : SCDEN
bits : 5 - 5 (1 bit)
CKABEN : CKABEN
bits : 6 - 6 (1 bit)
CHEN : CHEN
bits : 7 - 7 (1 bit)
CHINSEL : CHINSEL
bits : 8 - 8 (1 bit)
DATMPX : DATMPX
bits : 12 - 13 (2 bit)
DATPACK : DATPACK
bits : 14 - 15 (2 bit)
CKOUTDIV : CKOUTDIV
bits : 16 - 23 (8 bit)
CKOUTSRC : CKOUTSRC
bits : 30 - 30 (1 bit)
DFSDMEN : DFSDMEN
bits : 31 - 31 (1 bit)
DFSDM channel configuration 0 register 1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SITP : Serial interface type for channel 0
bits : 0 - 1 (2 bit)
SPICKSEL : SPI clock select for channel 0
bits : 2 - 3 (2 bit)
SCDEN : Short-circuit detector enable on channel 0
bits : 5 - 5 (1 bit)
CKABEN : Clock absence detector enable on channel 0
bits : 6 - 6 (1 bit)
CHEN : Channel 0 enable
bits : 7 - 7 (1 bit)
CHINSEL : Channel inputs selection
bits : 8 - 8 (1 bit)
DATMPX : Input data multiplexer for channel 0
bits : 12 - 13 (2 bit)
DATPACK : Data packing mode in DFSDM_CHDATINyR register
bits : 14 - 15 (2 bit)
CKOUTDIV : Output serial clock divider
bits : 16 - 23 (8 bit)
CKOUTSRC : Output serial clock source selection
bits : 30 - 30 (1 bit)
DFSDMEN : Global enable for DFSDM interface
bits : 31 - 31 (1 bit)
channel data input register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INDAT0 : INDAT0
bits : 0 - 15 (16 bit)
INDAT1 : INDAT1
bits : 16 - 31 (16 bit)
DFSDM channel configuration 4 register 1
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SITP : Serial interface type for channel 4
bits : 0 - 1 (2 bit)
SPICKSEL : SPI clock select for channel 4
bits : 2 - 3 (2 bit)
SCDEN : Short-circuit detector enable on channel 4
bits : 5 - 5 (1 bit)
CKABEN : Clock absence detector enable on channel 4
bits : 6 - 6 (1 bit)
CHEN : Channel 4 enable
bits : 7 - 7 (1 bit)
CHINSEL : Channel inputs selection
bits : 8 - 8 (1 bit)
DATMPX : Input data multiplexer for channel 4
bits : 12 - 13 (2 bit)
DATPACK : Data packing mode in DFSDM_CHDATINyR register
bits : 14 - 15 (2 bit)
CKOUTDIV : Output serial clock divider
bits : 16 - 23 (8 bit)
CKOUTSRC : Output serial clock source selection
bits : 30 - 30 (1 bit)
DFSDMEN : Global enable for DFSDM interface
bits : 31 - 31 (1 bit)
control register 1
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DFEN : DFSDM enable
bits : 0 - 0 (1 bit)
JSWSTART : Start a conversion of the injected group of channels
bits : 1 - 1 (1 bit)
JSYNC : Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger
bits : 3 - 3 (1 bit)
JSCAN : Scanning conversion mode for injected conversions
bits : 4 - 4 (1 bit)
JDMAEN : DMA channel enabled to read data for the injected channel group
bits : 5 - 5 (1 bit)
JEXTSEL : Trigger signal selection for launching injected conversions
bits : 8 - 10 (3 bit)
JEXTEN : Trigger enable and trigger edge selection for injected conversions
bits : 13 - 14 (2 bit)
RSWSTART : Software start of a conversion on the regular channel
bits : 17 - 17 (1 bit)
RCONT : Continuous mode selection for regular conversions
bits : 18 - 18 (1 bit)
RSYNC : Launch regular conversion synchronously with DFSDM0
bits : 19 - 19 (1 bit)
RDMAEN : DMA channel enabled to read data for the regular conversion
bits : 21 - 21 (1 bit)
RCH : Regular channel selection
bits : 24 - 26 (3 bit)
FAST : Fast conversion mode selection for regular conversions
bits : 29 - 29 (1 bit)
AWFSEL : Analog watchdog fast mode select
bits : 30 - 30 (1 bit)
DFSDM data register for injected group
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
JDATACH : Injected channel most recently converted
bits : 0 - 2 (3 bit)
JDATA : Injected group conversion data
bits : 8 - 31 (24 bit)
control register 2
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
JEOCIE : Injected end of conversion interrupt enable
bits : 0 - 0 (1 bit)
REOCIE : Regular end of conversion interrupt enable
bits : 1 - 1 (1 bit)
JOVRIE : Injected data overrun interrupt enable
bits : 2 - 2 (1 bit)
ROVRIE : Regular data overrun interrupt enable
bits : 3 - 3 (1 bit)
AWDIE : Analog watchdog interrupt enable
bits : 4 - 4 (1 bit)
SCDIE : Short-circuit detector interrupt enable
bits : 5 - 5 (1 bit)
CKABIE : Clock absence interrupt enable
bits : 6 - 6 (1 bit)
EXCH : Extremes detector channel selection
bits : 8 - 15 (8 bit)
AWDCH : Analog watchdog channel selection
bits : 16 - 23 (8 bit)
DFSDM data register for injected group
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
JDATACH : Injected channel most recently converted
bits : 0 - 2 (3 bit)
JDATA : Injected group conversion data
bits : 8 - 31 (24 bit)
interrupt and status register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
JEOCF : End of injected conversion flag
bits : 0 - 0 (1 bit)
REOCF : End of regular conversion flag
bits : 1 - 1 (1 bit)
JOVRF : Injected conversion overrun flag
bits : 2 - 2 (1 bit)
ROVRF : Regular conversion overrun flag
bits : 3 - 3 (1 bit)
AWDF : Analog watchdog
bits : 4 - 4 (1 bit)
JCIP : Injected conversion in progress status
bits : 13 - 13 (1 bit)
RCIP : Regular conversion in progress status
bits : 14 - 14 (1 bit)
CKABF : Clock absence flag
bits : 16 - 23 (8 bit)
SCDF : short-circuit detector flag
bits : 24 - 31 (8 bit)
DFSDM data register for injected group
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
JDATACH : Injected channel most recently converted
bits : 0 - 2 (3 bit)
JDATA : Injected group conversion data
bits : 8 - 31 (24 bit)
interrupt flag clear register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRJOVRF : Clear the injected conversion overrun flag
bits : 2 - 2 (1 bit)
CLRROVRF : Clear the regular conversion overrun flag
bits : 3 - 3 (1 bit)
CLRCKABF : Clear the clock absence flag
bits : 16 - 23 (8 bit)
CLRSCDF : Clear the short-circuit detector flag
bits : 24 - 31 (8 bit)
DFSDM data register for injected group
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
JDATACH : Injected channel most recently converted
bits : 0 - 2 (3 bit)
JDATA : Injected group conversion data
bits : 8 - 31 (24 bit)
injected channel group selection register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
JCHG : Injected channel group selection
bits : 0 - 7 (8 bit)
DFSDM data register for the regular channel
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDATACH : Regular channel most recently converted
bits : 0 - 2 (3 bit)
RPEND : Regular channel pending data
bits : 4 - 4 (1 bit)
RDATA : Regular channel conversion data
bits : 8 - 31 (24 bit)
filter control register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IOSR : Integrator oversampling ratio (averaging length)
bits : 0 - 7 (8 bit)
FOSR : Sinc filter oversampling ratio (decimation rate)
bits : 16 - 25 (10 bit)
FORD : Sinc filter order
bits : 29 - 31 (3 bit)
DFSDM data register for the regular channel
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDATACH : Regular channel most recently converted
bits : 0 - 2 (3 bit)
RPEND : Regular channel pending data
bits : 4 - 4 (1 bit)
RDATA : Regular channel conversion data
bits : 8 - 31 (24 bit)
data register for injected group
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
JDATACH : Injected channel most recently converted
bits : 0 - 2 (3 bit)
JDATA : Injected group conversion data
bits : 8 - 31 (24 bit)
DFSDM data register for the regular channel
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDATACH : Regular channel most recently converted
bits : 0 - 2 (3 bit)
RPEND : Regular channel pending data
bits : 4 - 4 (1 bit)
RDATA : Regular channel conversion data
bits : 8 - 31 (24 bit)
data register for the regular channel
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDATACH : Regular channel most recently converted
bits : 0 - 2 (3 bit)
RPEND : Regular channel pending data
bits : 4 - 4 (1 bit)
RDATA : Regular channel conversion data
bits : 8 - 31 (24 bit)
DFSDM data register for the regular channel
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDATACH : Regular channel most recently converted
bits : 0 - 2 (3 bit)
RPEND : Regular channel pending data
bits : 4 - 4 (1 bit)
RDATA : Regular channel conversion data
bits : 8 - 31 (24 bit)
analog watchdog high threshold register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BKAWH : Break signal assignment to analog watchdog high threshold event
bits : 0 - 3 (4 bit)
AWHT : Analog watchdog high threshold
bits : 8 - 31 (24 bit)
DFSDM analog watchdog high threshold register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BKAWH : Break signal assignment to analog watchdog high threshold event
bits : 0 - 3 (4 bit)
AWHT : Analog watchdog high threshold
bits : 8 - 31 (24 bit)
analog watchdog low threshold register
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BKAWL : Break signal assignment to analog watchdog low threshold event
bits : 0 - 3 (4 bit)
AWLT : Analog watchdog low threshold
bits : 8 - 31 (24 bit)
DFSDM analog watchdog high threshold register
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BKAWH : Break signal assignment to analog watchdog high threshold event
bits : 0 - 3 (4 bit)
AWHT : Analog watchdog high threshold
bits : 8 - 31 (24 bit)
analog watchdog status register
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
AWLTF : Analog watchdog low threshold flag
bits : 0 - 7 (8 bit)
AWHTF : Analog watchdog high threshold flag
bits : 8 - 15 (8 bit)
DFSDM analog watchdog high threshold register
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BKAWH : Break signal assignment to analog watchdog high threshold event
bits : 0 - 3 (4 bit)
AWHT : Analog watchdog high threshold
bits : 8 - 31 (24 bit)
analog watchdog clear flag register
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRAWLTF : Clear the analog watchdog low threshold flag
bits : 0 - 7 (8 bit)
CLRAWHTF : Clear the analog watchdog high threshold flag
bits : 8 - 15 (8 bit)
DFSDM analog watchdog high threshold register
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BKAWH : Break signal assignment to analog watchdog high threshold event
bits : 0 - 3 (4 bit)
AWHT : Analog watchdog high threshold
bits : 8 - 31 (24 bit)
Extremes detector maximum register
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EXMAXCH : Extremes detector maximum data channel
bits : 0 - 2 (3 bit)
EXMAX : Extremes detector maximum value
bits : 8 - 31 (24 bit)
DFSDM analog watchdog low threshold register
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BKAWL : Break signal assignment to analog watchdog low threshold event
bits : 0 - 3 (4 bit)
AWLT : Analog watchdog low threshold
bits : 8 - 31 (24 bit)
Extremes detector minimum register
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EXMINCH : Extremes detector minimum data channel
bits : 0 - 2 (3 bit)
EXMIN : EXMIN
bits : 8 - 31 (24 bit)
DFSDM analog watchdog low threshold register
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BKAWL : Break signal assignment to analog watchdog low threshold event
bits : 0 - 3 (4 bit)
AWLT : Analog watchdog low threshold
bits : 8 - 31 (24 bit)
conversion timer register
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CNVCNT : 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN
bits : 4 - 31 (28 bit)
DFSDM analog watchdog low threshold register
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BKAWL : Break signal assignment to analog watchdog low threshold event
bits : 0 - 3 (4 bit)
AWLT : Analog watchdog low threshold
bits : 8 - 31 (24 bit)
DFSDM analog watchdog low threshold register
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BKAWL : Break signal assignment to analog watchdog low threshold event
bits : 0 - 3 (4 bit)
AWLT : Analog watchdog low threshold
bits : 8 - 31 (24 bit)
channel y delay register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLSSKP : PLSSKP
bits : 0 - 5 (6 bit)
DFSDM channel configuration 5 register 1
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SITP : Serial interface type for channel 5
bits : 0 - 1 (2 bit)
SPICKSEL : SPI clock select for channel 5
bits : 2 - 3 (2 bit)
SCDEN : Short-circuit detector enable on channel 5
bits : 5 - 5 (1 bit)
CKABEN : Clock absence detector enable on channel 5
bits : 6 - 6 (1 bit)
CHEN : Channel 5 enable
bits : 7 - 7 (1 bit)
CHINSEL : Channel inputs selection
bits : 8 - 8 (1 bit)
DATMPX : Input data multiplexer for channel 5
bits : 12 - 13 (2 bit)
DATPACK : Data packing mode in DFSDM_CHDATINyR register
bits : 14 - 15 (2 bit)
CKOUTDIV : Output serial clock divider
bits : 16 - 23 (8 bit)
CKOUTSRC : Output serial clock source selection
bits : 30 - 30 (1 bit)
DFSDMEN : Global enable for DFSDM interface
bits : 31 - 31 (1 bit)
DFSDM analog watchdog status register
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
AWLTF : Analog watchdog low threshold flag
bits : 0 - 7 (8 bit)
AWHTF : Analog watchdog high threshold flag
bits : 8 - 15 (8 bit)
DFSDM analog watchdog status register
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
AWLTF : Analog watchdog low threshold flag
bits : 0 - 7 (8 bit)
AWHTF : Analog watchdog high threshold flag
bits : 8 - 15 (8 bit)
DFSDM analog watchdog status register
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
AWLTF : Analog watchdog low threshold flag
bits : 0 - 7 (8 bit)
AWHTF : Analog watchdog high threshold flag
bits : 8 - 15 (8 bit)
DFSDM analog watchdog status register
address_offset : 0x14C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
AWLTF : Analog watchdog low threshold flag
bits : 0 - 7 (8 bit)
AWHTF : Analog watchdog high threshold flag
bits : 8 - 15 (8 bit)
DFSDM analog watchdog clear flag register
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRAWLTF : Clear the analog watchdog low threshold flag
bits : 0 - 7 (8 bit)
CLRAWHTF : Clear the analog watchdog high threshold flag
bits : 8 - 15 (8 bit)
DFSDM analog watchdog clear flag register
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRAWLTF : Clear the analog watchdog low threshold flag
bits : 0 - 7 (8 bit)
CLRAWHTF : Clear the analog watchdog high threshold flag
bits : 8 - 15 (8 bit)
DFSDM analog watchdog clear flag register
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRAWLTF : Clear the analog watchdog low threshold flag
bits : 0 - 7 (8 bit)
CLRAWHTF : Clear the analog watchdog high threshold flag
bits : 8 - 15 (8 bit)
DFSDM analog watchdog clear flag register
address_offset : 0x15C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRAWLTF : Clear the analog watchdog low threshold flag
bits : 0 - 7 (8 bit)
CLRAWHTF : Clear the analog watchdog high threshold flag
bits : 8 - 15 (8 bit)
DFSDM Extremes detector maximum register
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EXMAXCH : Extremes detector maximum data channel
bits : 0 - 2 (3 bit)
EXMAX : Extremes detector maximum value
bits : 8 - 31 (24 bit)
DFSDM Extremes detector maximum register
address_offset : 0x164 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EXMAXCH : Extremes detector maximum data channel
bits : 0 - 2 (3 bit)
EXMAX : Extremes detector maximum value
bits : 8 - 31 (24 bit)
DFSDM Extremes detector maximum register
address_offset : 0x168 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EXMAXCH : Extremes detector maximum data channel
bits : 0 - 2 (3 bit)
EXMAX : Extremes detector maximum value
bits : 8 - 31 (24 bit)
DFSDM Extremes detector maximum register
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EXMAXCH : Extremes detector maximum data channel
bits : 0 - 2 (3 bit)
EXMAX : Extremes detector maximum value
bits : 8 - 31 (24 bit)
DFSDM Extremes detector minimum register
address_offset : 0x170 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EXMINCH : Extremes detector minimum data channel
bits : 0 - 2 (3 bit)
EXMIN : Extremes detector minimum value
bits : 8 - 31 (24 bit)
DFSDM Extremes detector minimum register
address_offset : 0x174 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EXMINCH : Extremes detector minimum data channel
bits : 0 - 2 (3 bit)
EXMIN : Extremes detector minimum value
bits : 8 - 31 (24 bit)
DFSDM Extremes detector minimum register
address_offset : 0x178 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EXMINCH : Extremes detector minimum data channel
bits : 0 - 2 (3 bit)
EXMIN : Extremes detector minimum value
bits : 8 - 31 (24 bit)
DFSDM Extremes detector minimum register
address_offset : 0x17C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EXMINCH : Extremes detector minimum data channel
bits : 0 - 2 (3 bit)
EXMIN : Extremes detector minimum value
bits : 8 - 31 (24 bit)
DFSDM channel configuration 6 register 1
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SITP : Serial interface type for channel 6
bits : 0 - 1 (2 bit)
SPICKSEL : SPI clock select for channel 6
bits : 2 - 3 (2 bit)
SCDEN : Short-circuit detector enable on channel 6
bits : 5 - 5 (1 bit)
CKABEN : Clock absence detector enable on channel 6
bits : 6 - 6 (1 bit)
CHEN : Channel 6 enable
bits : 7 - 7 (1 bit)
CHINSEL : Channel inputs selection
bits : 8 - 8 (1 bit)
DATMPX : Input data multiplexer for channel 6
bits : 12 - 13 (2 bit)
DATPACK : Data packing mode in DFSDM_CHDATINyR register
bits : 14 - 15 (2 bit)
CKOUTDIV : Output serial clock divider
bits : 16 - 23 (8 bit)
CKOUTSRC : Output serial clock source selection
bits : 30 - 30 (1 bit)
DFSDMEN : Global enable for DFSDM interface
bits : 31 - 31 (1 bit)
control register 1
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DFEN : DFSDM enable
bits : 0 - 0 (1 bit)
JSWSTART : Start a conversion of the injected group of channels
bits : 1 - 1 (1 bit)
JSYNC : Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger
bits : 3 - 3 (1 bit)
JSCAN : Scanning conversion mode for injected conversions
bits : 4 - 4 (1 bit)
JDMAEN : DMA channel enabled to read data for the injected channel group
bits : 5 - 5 (1 bit)
JEXTSEL : Trigger signal selection for launching injected conversions
bits : 8 - 10 (3 bit)
JEXTEN : Trigger enable and trigger edge selection for injected conversions
bits : 13 - 14 (2 bit)
RSWSTART : Software start of a conversion on the regular channel
bits : 17 - 17 (1 bit)
RCONT : Continuous mode selection for regular conversions
bits : 18 - 18 (1 bit)
RSYNC : Launch regular conversion synchronously with DFSDM0
bits : 19 - 19 (1 bit)
RDMAEN : DMA channel enabled to read data for the regular conversion
bits : 21 - 21 (1 bit)
RCH : Regular channel selection
bits : 24 - 26 (3 bit)
FAST : Fast conversion mode selection for regular conversions
bits : 29 - 29 (1 bit)
AWFSEL : Analog watchdog fast mode select
bits : 30 - 30 (1 bit)
DFSDM conversion timer register
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CNVCNT : 28-bit timer counting conversion time
bits : 4 - 31 (28 bit)
control register 2
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
JEOCIE : Injected end of conversion interrupt enable
bits : 0 - 0 (1 bit)
REOCIE : Regular end of conversion interrupt enable
bits : 1 - 1 (1 bit)
JOVRIE : Injected data overrun interrupt enable
bits : 2 - 2 (1 bit)
ROVRIE : Regular data overrun interrupt enable
bits : 3 - 3 (1 bit)
AWDIE : Analog watchdog interrupt enable
bits : 4 - 4 (1 bit)
SCDIE : Short-circuit detector interrupt enable
bits : 5 - 5 (1 bit)
CKABIE : Clock absence interrupt enable
bits : 6 - 6 (1 bit)
EXCH : Extremes detector channel selection
bits : 8 - 15 (8 bit)
AWDCH : Analog watchdog channel selection
bits : 16 - 23 (8 bit)
DFSDM conversion timer register
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CNVCNT : 28-bit timer counting conversion time
bits : 4 - 31 (28 bit)
interrupt and status register
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
JEOCF : End of injected conversion flag
bits : 0 - 0 (1 bit)
REOCF : End of regular conversion flag
bits : 1 - 1 (1 bit)
JOVRF : Injected conversion overrun flag
bits : 2 - 2 (1 bit)
ROVRF : Regular conversion overrun flag
bits : 3 - 3 (1 bit)
AWDF : Analog watchdog
bits : 4 - 4 (1 bit)
JCIP : Injected conversion in progress status
bits : 13 - 13 (1 bit)
RCIP : Regular conversion in progress status
bits : 14 - 14 (1 bit)
CKABF : Clock absence flag
bits : 16 - 23 (8 bit)
SCDF : short-circuit detector flag
bits : 24 - 31 (8 bit)
DFSDM conversion timer register
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CNVCNT : 28-bit timer counting conversion time
bits : 4 - 31 (28 bit)
interrupt flag clear register
address_offset : 0x18C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRJOVRF : Clear the injected conversion overrun flag
bits : 2 - 2 (1 bit)
CLRROVRF : Clear the regular conversion overrun flag
bits : 3 - 3 (1 bit)
CLRCKABF : Clear the clock absence flag
bits : 16 - 23 (8 bit)
CLRSCDF : Clear the short-circuit detector flag
bits : 24 - 31 (8 bit)
DFSDM conversion timer register
address_offset : 0x18C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CNVCNT : 28-bit timer counting conversion time
bits : 4 - 31 (28 bit)
injected channel group selection register
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
JCHG : Injected channel group selection
bits : 0 - 7 (8 bit)
filter control register
address_offset : 0x194 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IOSR : Integrator oversampling ratio (averaging length)
bits : 0 - 7 (8 bit)
FOSR : Sinc filter oversampling ratio (decimation rate)
bits : 16 - 25 (10 bit)
FORD : Sinc filter order
bits : 29 - 31 (3 bit)
data register for injected group
address_offset : 0x198 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
JDATACH : Injected channel most recently converted
bits : 0 - 2 (3 bit)
JDATA : Injected group conversion data
bits : 8 - 31 (24 bit)
data register for the regular channel
address_offset : 0x19C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDATACH : Regular channel most recently converted
bits : 0 - 2 (3 bit)
RPEND : Regular channel pending data
bits : 4 - 4 (1 bit)
RDATA : Regular channel conversion data
bits : 8 - 31 (24 bit)
analog watchdog high threshold register
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BKAWH : Break signal assignment to analog watchdog high threshold event
bits : 0 - 3 (4 bit)
AWHT : Analog watchdog high threshold
bits : 8 - 31 (24 bit)
analog watchdog low threshold register
address_offset : 0x1A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BKAWL : Break signal assignment to analog watchdog low threshold event
bits : 0 - 3 (4 bit)
AWLT : Analog watchdog low threshold
bits : 8 - 31 (24 bit)
analog watchdog status register
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
AWLTF : Analog watchdog low threshold flag
bits : 0 - 7 (8 bit)
AWHTF : Analog watchdog high threshold flag
bits : 8 - 15 (8 bit)
analog watchdog clear flag register
address_offset : 0x1AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRAWLTF : Clear the analog watchdog low threshold flag
bits : 0 - 7 (8 bit)
CLRAWHTF : Clear the analog watchdog high threshold flag
bits : 8 - 15 (8 bit)
Extremes detector maximum register
address_offset : 0x1B0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EXMAXCH : Extremes detector maximum data channel
bits : 0 - 2 (3 bit)
EXMAX : Extremes detector maximum value
bits : 8 - 31 (24 bit)
Extremes detector minimum register
address_offset : 0x1B4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EXMINCH : Extremes detector minimum data channel
bits : 0 - 2 (3 bit)
EXMIN : EXMIN
bits : 8 - 31 (24 bit)
conversion timer register
address_offset : 0x1B8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CNVCNT : 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN
bits : 4 - 31 (28 bit)
DFSDM channel configuration 7 register 1
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SITP : Serial interface type for channel 7
bits : 0 - 1 (2 bit)
SPICKSEL : SPI clock select for channel 7
bits : 2 - 3 (2 bit)
SCDEN : Short-circuit detector enable on channel 7
bits : 5 - 5 (1 bit)
CKABEN : Clock absence detector enable on channel 7
bits : 6 - 6 (1 bit)
CHEN : Channel 7 enable
bits : 7 - 7 (1 bit)
CHINSEL : Channel inputs selection
bits : 8 - 8 (1 bit)
DATMPX : Input data multiplexer for channel 7
bits : 12 - 13 (2 bit)
DATPACK : Data packing mode in DFSDM_CHDATINyR register
bits : 14 - 15 (2 bit)
CKOUTDIV : Output serial clock divider
bits : 16 - 23 (8 bit)
CKOUTSRC : Output serial clock source selection
bits : 30 - 30 (1 bit)
DFSDMEN : Global enable for DFSDM interface
bits : 31 - 31 (1 bit)
CH1CFGR1
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SITP : SITP
bits : 0 - 1 (2 bit)
SPICKSEL : SPICKSEL
bits : 2 - 3 (2 bit)
SCDEN : SCDEN
bits : 5 - 5 (1 bit)
CKABEN : CKABEN
bits : 6 - 6 (1 bit)
CHEN : CHEN
bits : 7 - 7 (1 bit)
CHINSEL : CHINSEL
bits : 8 - 8 (1 bit)
DATMPX : DATMPX
bits : 12 - 13 (2 bit)
DATPACK : DATPACK
bits : 14 - 15 (2 bit)
DFSDM channel configuration 0 register 2
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTRBS : Data right bit-shift for channel 0
bits : 3 - 7 (5 bit)
OFFSET : 24-bit calibration offset for channel 0
bits : 8 - 31 (24 bit)
control register 1
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DFEN : DFSDM enable
bits : 0 - 0 (1 bit)
JSWSTART : Start a conversion of the injected group of channels
bits : 1 - 1 (1 bit)
JSYNC : Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger
bits : 3 - 3 (1 bit)
JSCAN : Scanning conversion mode for injected conversions
bits : 4 - 4 (1 bit)
JDMAEN : DMA channel enabled to read data for the injected channel group
bits : 5 - 5 (1 bit)
JEXTSEL : Trigger signal selection for launching injected conversions
bits : 8 - 10 (3 bit)
JEXTEN : Trigger enable and trigger edge selection for injected conversions
bits : 13 - 14 (2 bit)
RSWSTART : Software start of a conversion on the regular channel
bits : 17 - 17 (1 bit)
RCONT : Continuous mode selection for regular conversions
bits : 18 - 18 (1 bit)
RSYNC : Launch regular conversion synchronously with DFSDM0
bits : 19 - 19 (1 bit)
RDMAEN : DMA channel enabled to read data for the regular conversion
bits : 21 - 21 (1 bit)
RCH : Regular channel selection
bits : 24 - 26 (3 bit)
FAST : Fast conversion mode selection for regular conversions
bits : 29 - 29 (1 bit)
AWFSEL : Analog watchdog fast mode select
bits : 30 - 30 (1 bit)
control register 2
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
JEOCIE : Injected end of conversion interrupt enable
bits : 0 - 0 (1 bit)
REOCIE : Regular end of conversion interrupt enable
bits : 1 - 1 (1 bit)
JOVRIE : Injected data overrun interrupt enable
bits : 2 - 2 (1 bit)
ROVRIE : Regular data overrun interrupt enable
bits : 3 - 3 (1 bit)
AWDIE : Analog watchdog interrupt enable
bits : 4 - 4 (1 bit)
SCDIE : Short-circuit detector interrupt enable
bits : 5 - 5 (1 bit)
CKABIE : Clock absence interrupt enable
bits : 6 - 6 (1 bit)
EXCH : Extremes detector channel selection
bits : 8 - 15 (8 bit)
AWDCH : Analog watchdog channel selection
bits : 16 - 23 (8 bit)
interrupt and status register
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
JEOCF : End of injected conversion flag
bits : 0 - 0 (1 bit)
REOCF : End of regular conversion flag
bits : 1 - 1 (1 bit)
JOVRF : Injected conversion overrun flag
bits : 2 - 2 (1 bit)
ROVRF : Regular conversion overrun flag
bits : 3 - 3 (1 bit)
AWDF : Analog watchdog
bits : 4 - 4 (1 bit)
JCIP : Injected conversion in progress status
bits : 13 - 13 (1 bit)
RCIP : Regular conversion in progress status
bits : 14 - 14 (1 bit)
CKABF : Clock absence flag
bits : 16 - 23 (8 bit)
SCDF : short-circuit detector flag
bits : 24 - 31 (8 bit)
interrupt flag clear register
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRJOVRF : Clear the injected conversion overrun flag
bits : 2 - 2 (1 bit)
CLRROVRF : Clear the regular conversion overrun flag
bits : 3 - 3 (1 bit)
CLRCKABF : Clear the clock absence flag
bits : 16 - 23 (8 bit)
CLRSCDF : Clear the short-circuit detector flag
bits : 24 - 31 (8 bit)
injected channel group selection register
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
JCHG : Injected channel group selection
bits : 0 - 7 (8 bit)
filter control register
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IOSR : Integrator oversampling ratio (averaging length)
bits : 0 - 7 (8 bit)
FOSR : Sinc filter oversampling ratio (decimation rate)
bits : 16 - 25 (10 bit)
FORD : Sinc filter order
bits : 29 - 31 (3 bit)
data register for injected group
address_offset : 0x218 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
JDATACH : Injected channel most recently converted
bits : 0 - 2 (3 bit)
JDATA : Injected group conversion data
bits : 8 - 31 (24 bit)
data register for the regular channel
address_offset : 0x21C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDATACH : Regular channel most recently converted
bits : 0 - 2 (3 bit)
RPEND : Regular channel pending data
bits : 4 - 4 (1 bit)
RDATA : Regular channel conversion data
bits : 8 - 31 (24 bit)
analog watchdog high threshold register
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BKAWH : Break signal assignment to analog watchdog high threshold event
bits : 0 - 3 (4 bit)
AWHT : Analog watchdog high threshold
bits : 8 - 31 (24 bit)
analog watchdog low threshold register
address_offset : 0x224 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BKAWL : Break signal assignment to analog watchdog low threshold event
bits : 0 - 3 (4 bit)
AWLT : Analog watchdog low threshold
bits : 8 - 31 (24 bit)
analog watchdog status register
address_offset : 0x228 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
AWLTF : Analog watchdog low threshold flag
bits : 0 - 7 (8 bit)
AWHTF : Analog watchdog high threshold flag
bits : 8 - 15 (8 bit)
analog watchdog clear flag register
address_offset : 0x22C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRAWLTF : Clear the analog watchdog low threshold flag
bits : 0 - 7 (8 bit)
CLRAWHTF : Clear the analog watchdog high threshold flag
bits : 8 - 15 (8 bit)
Extremes detector maximum register
address_offset : 0x230 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EXMAXCH : Extremes detector maximum data channel
bits : 0 - 2 (3 bit)
EXMAX : Extremes detector maximum value
bits : 8 - 31 (24 bit)
Extremes detector minimum register
address_offset : 0x234 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EXMINCH : Extremes detector minimum data channel
bits : 0 - 2 (3 bit)
EXMIN : EXMIN
bits : 8 - 31 (24 bit)
conversion timer register
address_offset : 0x238 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CNVCNT : 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN
bits : 4 - 31 (28 bit)
CH1CFGR2
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTRBS : DTRBS
bits : 3 - 7 (5 bit)
OFFSET : OFFSET
bits : 8 - 31 (24 bit)
DFSDM channel configuration 1 register 2
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTRBS : Data right bit-shift for channel 1
bits : 3 - 7 (5 bit)
OFFSET : 24-bit calibration offset for channel 1
bits : 8 - 31 (24 bit)
CH1AWSCDR
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SCDT : SCDT
bits : 0 - 7 (8 bit)
BKSCD : BKSCD
bits : 12 - 15 (4 bit)
AWFOSR : AWFOSR
bits : 16 - 20 (5 bit)
AWFORD : AWFORD
bits : 22 - 23 (2 bit)
DFSDM channel configuration 2 register 2
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTRBS : Data right bit-shift for channel 2
bits : 3 - 7 (5 bit)
OFFSET : 24-bit calibration offset for channel 2
bits : 8 - 31 (24 bit)
control register 1
address_offset : 0x280 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DFEN : DFSDM enable
bits : 0 - 0 (1 bit)
JSWSTART : Start a conversion of the injected group of channels
bits : 1 - 1 (1 bit)
JSYNC : Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger
bits : 3 - 3 (1 bit)
JSCAN : Scanning conversion mode for injected conversions
bits : 4 - 4 (1 bit)
JDMAEN : DMA channel enabled to read data for the injected channel group
bits : 5 - 5 (1 bit)
JEXTSEL : Trigger signal selection for launching injected conversions
bits : 8 - 10 (3 bit)
JEXTEN : Trigger enable and trigger edge selection for injected conversions
bits : 13 - 14 (2 bit)
RSWSTART : Software start of a conversion on the regular channel
bits : 17 - 17 (1 bit)
RCONT : Continuous mode selection for regular conversions
bits : 18 - 18 (1 bit)
RSYNC : Launch regular conversion synchronously with DFSDM0
bits : 19 - 19 (1 bit)
RDMAEN : DMA channel enabled to read data for the regular conversion
bits : 21 - 21 (1 bit)
RCH : Regular channel selection
bits : 24 - 26 (3 bit)
FAST : Fast conversion mode selection for regular conversions
bits : 29 - 29 (1 bit)
AWFSEL : Analog watchdog fast mode select
bits : 30 - 30 (1 bit)
control register 2
address_offset : 0x284 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
JEOCIE : Injected end of conversion interrupt enable
bits : 0 - 0 (1 bit)
REOCIE : Regular end of conversion interrupt enable
bits : 1 - 1 (1 bit)
JOVRIE : Injected data overrun interrupt enable
bits : 2 - 2 (1 bit)
ROVRIE : Regular data overrun interrupt enable
bits : 3 - 3 (1 bit)
AWDIE : Analog watchdog interrupt enable
bits : 4 - 4 (1 bit)
SCDIE : Short-circuit detector interrupt enable
bits : 5 - 5 (1 bit)
CKABIE : Clock absence interrupt enable
bits : 6 - 6 (1 bit)
EXCH : Extremes detector channel selection
bits : 8 - 15 (8 bit)
AWDCH : Analog watchdog channel selection
bits : 16 - 23 (8 bit)
interrupt and status register
address_offset : 0x288 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
JEOCF : End of injected conversion flag
bits : 0 - 0 (1 bit)
REOCF : End of regular conversion flag
bits : 1 - 1 (1 bit)
JOVRF : Injected conversion overrun flag
bits : 2 - 2 (1 bit)
ROVRF : Regular conversion overrun flag
bits : 3 - 3 (1 bit)
AWDF : Analog watchdog
bits : 4 - 4 (1 bit)
JCIP : Injected conversion in progress status
bits : 13 - 13 (1 bit)
RCIP : Regular conversion in progress status
bits : 14 - 14 (1 bit)
CKABF : Clock absence flag
bits : 16 - 23 (8 bit)
SCDF : short-circuit detector flag
bits : 24 - 31 (8 bit)
interrupt flag clear register
address_offset : 0x28C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRJOVRF : Clear the injected conversion overrun flag
bits : 2 - 2 (1 bit)
CLRROVRF : Clear the regular conversion overrun flag
bits : 3 - 3 (1 bit)
CLRCKABF : Clear the clock absence flag
bits : 16 - 23 (8 bit)
CLRSCDF : Clear the short-circuit detector flag
bits : 24 - 31 (8 bit)
injected channel group selection register
address_offset : 0x290 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
JCHG : Injected channel group selection
bits : 0 - 7 (8 bit)
filter control register
address_offset : 0x294 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IOSR : Integrator oversampling ratio (averaging length)
bits : 0 - 7 (8 bit)
FOSR : Sinc filter oversampling ratio (decimation rate)
bits : 16 - 25 (10 bit)
FORD : Sinc filter order
bits : 29 - 31 (3 bit)
data register for injected group
address_offset : 0x298 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
JDATACH : Injected channel most recently converted
bits : 0 - 2 (3 bit)
JDATA : Injected group conversion data
bits : 8 - 31 (24 bit)
data register for the regular channel
address_offset : 0x29C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDATACH : Regular channel most recently converted
bits : 0 - 2 (3 bit)
RPEND : Regular channel pending data
bits : 4 - 4 (1 bit)
RDATA : Regular channel conversion data
bits : 8 - 31 (24 bit)
analog watchdog high threshold register
address_offset : 0x2A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BKAWH : Break signal assignment to analog watchdog high threshold event
bits : 0 - 3 (4 bit)
AWHT : Analog watchdog high threshold
bits : 8 - 31 (24 bit)
analog watchdog low threshold register
address_offset : 0x2A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BKAWL : Break signal assignment to analog watchdog low threshold event
bits : 0 - 3 (4 bit)
AWLT : Analog watchdog low threshold
bits : 8 - 31 (24 bit)
analog watchdog status register
address_offset : 0x2A8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
AWLTF : Analog watchdog low threshold flag
bits : 0 - 7 (8 bit)
AWHTF : Analog watchdog high threshold flag
bits : 8 - 15 (8 bit)
analog watchdog clear flag register
address_offset : 0x2AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRAWLTF : Clear the analog watchdog low threshold flag
bits : 0 - 7 (8 bit)
CLRAWHTF : Clear the analog watchdog high threshold flag
bits : 8 - 15 (8 bit)
Extremes detector maximum register
address_offset : 0x2B0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EXMAXCH : Extremes detector maximum data channel
bits : 0 - 2 (3 bit)
EXMAX : Extremes detector maximum value
bits : 8 - 31 (24 bit)
Extremes detector minimum register
address_offset : 0x2B4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EXMINCH : Extremes detector minimum data channel
bits : 0 - 2 (3 bit)
EXMIN : EXMIN
bits : 8 - 31 (24 bit)
conversion timer register
address_offset : 0x2B8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CNVCNT : 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN
bits : 4 - 31 (28 bit)
CH1WDATR
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDATA : WDATA
bits : 0 - 15 (16 bit)
DFSDM channel configuration 3 register 2
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTRBS : Data right bit-shift for channel 3
bits : 3 - 7 (5 bit)
OFFSET : 24-bit calibration offset for channel 3
bits : 8 - 31 (24 bit)
CH1DATINR
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INDAT0 : INDAT0
bits : 0 - 15 (16 bit)
INDAT1 : INDAT1
bits : 16 - 31 (16 bit)
DFSDM channel configuration 4 register 2
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTRBS : Data right bit-shift for channel 4
bits : 3 - 7 (5 bit)
OFFSET : 24-bit calibration offset for channel 4
bits : 8 - 31 (24 bit)
channel y delay register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLSSKP : PLSSKP
bits : 0 - 5 (6 bit)
DFSDM channel configuration 5 register 2
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTRBS : Data right bit-shift for channel 5
bits : 3 - 7 (5 bit)
OFFSET : 24-bit calibration offset for channel 5
bits : 8 - 31 (24 bit)
DFSDM channel configuration 6 register 2
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTRBS : Data right bit-shift for channel 6
bits : 3 - 7 (5 bit)
OFFSET : 24-bit calibration offset for channel 6
bits : 8 - 31 (24 bit)
DFSDM channel configuration 7 register 2
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTRBS : Data right bit-shift for channel 7
bits : 3 - 7 (5 bit)
OFFSET : 24-bit calibration offset for channel 7
bits : 8 - 31 (24 bit)
channel configuration y register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTRBS : DTRBS
bits : 3 - 7 (5 bit)
OFFSET : OFFSET
bits : 8 - 31 (24 bit)
DFSDM channel configuration 1 register 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SITP : Serial interface type for channel 1
bits : 0 - 1 (2 bit)
SPICKSEL : SPI clock select for channel 1
bits : 2 - 3 (2 bit)
SCDEN : Short-circuit detector enable on channel 1
bits : 5 - 5 (1 bit)
CKABEN : Clock absence detector enable on channel 1
bits : 6 - 6 (1 bit)
CHEN : Channel 1 enable
bits : 7 - 7 (1 bit)
CHINSEL : Channel inputs selection
bits : 8 - 8 (1 bit)
DATMPX : Input data multiplexer for channel 1
bits : 12 - 13 (2 bit)
DATPACK : Data packing mode in DFSDM_CHDATINyR register
bits : 14 - 15 (2 bit)
CKOUTDIV : Output serial clock divider
bits : 16 - 23 (8 bit)
CKOUTSRC : Output serial clock source selection
bits : 30 - 30 (1 bit)
DFSDMEN : Global enable for DFSDM interface
bits : 31 - 31 (1 bit)
CH2CFGR1
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SITP : SITP
bits : 0 - 1 (2 bit)
SPICKSEL : SPICKSEL
bits : 2 - 3 (2 bit)
SCDEN : SCDEN
bits : 5 - 5 (1 bit)
CKABEN : CKABEN
bits : 6 - 6 (1 bit)
CHEN : CHEN
bits : 7 - 7 (1 bit)
CHINSEL : CHINSEL
bits : 8 - 8 (1 bit)
DATMPX : DATMPX
bits : 12 - 13 (2 bit)
DATPACK : DATPACK
bits : 14 - 15 (2 bit)
DFSDM analog watchdog and short-circuit detector register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SCDT : short-circuit detector threshold for channel 0
bits : 0 - 7 (8 bit)
BKSCD : Break signal assignment for short-circuit detector on channel 0
bits : 12 - 15 (4 bit)
AWFOSR : Analog watchdog filter oversampling ratio (decimation rate) on channel 0
bits : 16 - 20 (5 bit)
AWFORD : Analog watchdog Sinc filter order on channel 0
bits : 22 - 23 (2 bit)
CH2CFGR2
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTRBS : DTRBS
bits : 3 - 7 (5 bit)
OFFSET : OFFSET
bits : 8 - 31 (24 bit)
DFSDM analog watchdog and short-circuit detector register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SCDT : short-circuit detector threshold for channel 1
bits : 0 - 7 (8 bit)
BKSCD : Break signal assignment for short-circuit detector on channel 1
bits : 12 - 15 (4 bit)
AWFOSR : Analog watchdog filter oversampling ratio (decimation rate) on channel 1
bits : 16 - 20 (5 bit)
AWFORD : Analog watchdog Sinc filter order on channel 1
bits : 22 - 23 (2 bit)
CH2AWSCDR
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SCDT : SCDT
bits : 0 - 7 (8 bit)
BKSCD : BKSCD
bits : 12 - 15 (4 bit)
AWFOSR : AWFOSR
bits : 16 - 20 (5 bit)
AWFORD : AWFORD
bits : 22 - 23 (2 bit)
DFSDM analog watchdog and short-circuit detector register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SCDT : short-circuit detector threshold for channel 2
bits : 0 - 7 (8 bit)
BKSCD : Break signal assignment for short-circuit detector on channel 2
bits : 12 - 15 (4 bit)
AWFOSR : Analog watchdog filter oversampling ratio (decimation rate) on channel 2
bits : 16 - 20 (5 bit)
AWFORD : Analog watchdog Sinc filter order on channel 2
bits : 22 - 23 (2 bit)
CH2WDATR
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDATA : WDATA
bits : 0 - 15 (16 bit)
DFSDM analog watchdog and short-circuit detector register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SCDT : short-circuit detector threshold for channel 3
bits : 0 - 7 (8 bit)
BKSCD : Break signal assignment for short-circuit detector on channel 3
bits : 12 - 15 (4 bit)
AWFOSR : Analog watchdog filter oversampling ratio (decimation rate) on channel 3
bits : 16 - 20 (5 bit)
AWFORD : Analog watchdog Sinc filter order on channel 3
bits : 22 - 23 (2 bit)
CH2DATINR
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INDAT0 : INDAT0
bits : 0 - 15 (16 bit)
INDAT1 : INDAT1
bits : 16 - 31 (16 bit)
DFSDM analog watchdog and short-circuit detector register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SCDT : short-circuit detector threshold for channel 4
bits : 0 - 7 (8 bit)
BKSCD : Break signal assignment for short-circuit detector on channel 4
bits : 12 - 15 (4 bit)
AWFOSR : Analog watchdog filter oversampling ratio (decimation rate) on channel 4
bits : 16 - 20 (5 bit)
AWFORD : Analog watchdog Sinc filter order on channel 4
bits : 22 - 23 (2 bit)
channel y delay register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLSSKP : PLSSKP
bits : 0 - 5 (6 bit)
DFSDM analog watchdog and short-circuit detector register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SCDT : short-circuit detector threshold for channel 5
bits : 0 - 7 (8 bit)
BKSCD : Break signal assignment for short-circuit detector on channel 5
bits : 12 - 15 (4 bit)
AWFOSR : Analog watchdog filter oversampling ratio (decimation rate) on channel 5
bits : 16 - 20 (5 bit)
AWFORD : Analog watchdog Sinc filter order on channel 5
bits : 22 - 23 (2 bit)
DFSDM analog watchdog and short-circuit detector register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SCDT : short-circuit detector threshold for channel 6
bits : 0 - 7 (8 bit)
BKSCD : Break signal assignment for short-circuit detector on channel 6
bits : 12 - 15 (4 bit)
AWFOSR : Analog watchdog filter oversampling ratio (decimation rate) on channel 6
bits : 16 - 20 (5 bit)
AWFORD : Analog watchdog Sinc filter order on channel 6
bits : 22 - 23 (2 bit)
DFSDM analog watchdog and short-circuit detector register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SCDT : short-circuit detector threshold for channel 7
bits : 0 - 7 (8 bit)
BKSCD : Break signal assignment for short-circuit detector on channel 7
bits : 12 - 15 (4 bit)
AWFOSR : Analog watchdog filter oversampling ratio (decimation rate) on channel 7
bits : 16 - 20 (5 bit)
AWFORD : Analog watchdog Sinc filter order on channel 7
bits : 22 - 23 (2 bit)
CH3CFGR1
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SITP : SITP
bits : 0 - 1 (2 bit)
SPICKSEL : SPICKSEL
bits : 2 - 3 (2 bit)
SCDEN : SCDEN
bits : 5 - 5 (1 bit)
CKABEN : CKABEN
bits : 6 - 6 (1 bit)
CHEN : CHEN
bits : 7 - 7 (1 bit)
CHINSEL : CHINSEL
bits : 8 - 8 (1 bit)
DATMPX : DATMPX
bits : 12 - 13 (2 bit)
DATPACK : DATPACK
bits : 14 - 15 (2 bit)
DFSDM channel watchdog filter data register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WDATA : Input channel y watchdog data
bits : 0 - 15 (16 bit)
CH3CFGR2
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTRBS : DTRBS
bits : 3 - 7 (5 bit)
OFFSET : OFFSET
bits : 8 - 31 (24 bit)
DFSDM channel watchdog filter data register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WDATA : Input channel y watchdog data
bits : 0 - 15 (16 bit)
CH3AWSCDR
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SCDT : SCDT
bits : 0 - 7 (8 bit)
BKSCD : BKSCD
bits : 12 - 15 (4 bit)
AWFOSR : AWFOSR
bits : 16 - 20 (5 bit)
AWFORD : AWFORD
bits : 22 - 23 (2 bit)
DFSDM channel watchdog filter data register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WDATA : Input channel y watchdog data
bits : 0 - 15 (16 bit)
CH3WDATR
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDATA : WDATA
bits : 0 - 15 (16 bit)
DFSDM channel watchdog filter data register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WDATA : Input channel y watchdog data
bits : 0 - 15 (16 bit)
CH3DATINR
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INDAT0 : INDAT0
bits : 0 - 15 (16 bit)
INDAT1 : INDAT1
bits : 16 - 31 (16 bit)
DFSDM channel watchdog filter data register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WDATA : Input channel y watchdog data
bits : 0 - 15 (16 bit)
channel y delay register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLSSKP : PLSSKP
bits : 0 - 5 (6 bit)
DFSDM channel watchdog filter data register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WDATA : Input channel y watchdog data
bits : 0 - 15 (16 bit)
DFSDM channel watchdog filter data register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WDATA : Input channel y watchdog data
bits : 0 - 15 (16 bit)
DFSDM channel watchdog filter data register
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WDATA : Input channel y watchdog data
bits : 0 - 15 (16 bit)
analog watchdog and short-circuit detector register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SCDT : SCDT
bits : 0 - 7 (8 bit)
BKSCD : BKSCD
bits : 12 - 15 (4 bit)
AWFOSR : AWFOSR
bits : 16 - 20 (5 bit)
AWFORD : AWFORD
bits : 22 - 23 (2 bit)
DFSDM channel configuration 2 register 1
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SITP : Serial interface type for channel 2
bits : 0 - 1 (2 bit)
SPICKSEL : SPI clock select for channel 2
bits : 2 - 3 (2 bit)
SCDEN : Short-circuit detector enable on channel 2
bits : 5 - 5 (1 bit)
CKABEN : Clock absence detector enable on channel 2
bits : 6 - 6 (1 bit)
CHEN : Channel 2 enable
bits : 7 - 7 (1 bit)
CHINSEL : Channel inputs selection
bits : 8 - 8 (1 bit)
DATMPX : Input data multiplexer for channel 2
bits : 12 - 13 (2 bit)
DATPACK : Data packing mode in DFSDM_CHDATINyR register
bits : 14 - 15 (2 bit)
CKOUTDIV : Output serial clock divider
bits : 16 - 23 (8 bit)
CKOUTSRC : Output serial clock source selection
bits : 30 - 30 (1 bit)
DFSDMEN : Global enable for DFSDM interface
bits : 31 - 31 (1 bit)
CH4CFGR1
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SITP : SITP
bits : 0 - 1 (2 bit)
SPICKSEL : SPICKSEL
bits : 2 - 3 (2 bit)
SCDEN : SCDEN
bits : 5 - 5 (1 bit)
CKABEN : CKABEN
bits : 6 - 6 (1 bit)
CHEN : CHEN
bits : 7 - 7 (1 bit)
CHINSEL : CHINSEL
bits : 8 - 8 (1 bit)
DATMPX : DATMPX
bits : 12 - 13 (2 bit)
DATPACK : DATPACK
bits : 14 - 15 (2 bit)
DFSDM channel data input register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INDAT0 : Input data for channel 0
bits : 0 - 15 (16 bit)
INDAT1 : Input data for channel 1
bits : 16 - 31 (16 bit)
CH4CFGR2
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTRBS : DTRBS
bits : 3 - 7 (5 bit)
OFFSET : OFFSET
bits : 8 - 31 (24 bit)
DFSDM channel data input register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INDAT0 : Input data for channel 1
bits : 0 - 15 (16 bit)
INDAT1 : Input data for channel 2
bits : 16 - 31 (16 bit)
CH4AWSCDR
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SCDT : SCDT
bits : 0 - 7 (8 bit)
BKSCD : BKSCD
bits : 12 - 15 (4 bit)
AWFOSR : AWFOSR
bits : 16 - 20 (5 bit)
AWFORD : AWFORD
bits : 22 - 23 (2 bit)
DFSDM channel data input register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INDAT0 : Input data for channel 2
bits : 0 - 15 (16 bit)
INDAT1 : Input data for channel 3
bits : 16 - 31 (16 bit)
CH4WDATR
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDATA : WDATA
bits : 0 - 15 (16 bit)
DFSDM channel data input register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INDAT0 : Input data for channel 3
bits : 0 - 15 (16 bit)
INDAT1 : Input data for channel 4
bits : 16 - 31 (16 bit)
CH4DATINR
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INDAT0 : INDAT0
bits : 0 - 15 (16 bit)
INDAT1 : INDAT1
bits : 16 - 31 (16 bit)
DFSDM channel data input register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INDAT0 : Input data for channel 4
bits : 0 - 15 (16 bit)
INDAT1 : Input data for channel 5
bits : 16 - 31 (16 bit)
channel y delay register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLSSKP : PLSSKP
bits : 0 - 5 (6 bit)
DFSDM channel data input register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INDAT0 : Input data for channel 5
bits : 0 - 15 (16 bit)
INDAT1 : Input data for channel 6
bits : 16 - 31 (16 bit)
DFSDM channel data input register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INDAT0 : Input data for channel 6
bits : 0 - 15 (16 bit)
INDAT1 : Input data for channel 7
bits : 16 - 31 (16 bit)
DFSDM channel data input register
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INDAT0 : Input data for channel 7
bits : 0 - 15 (16 bit)
INDAT1 : Input data for channel 8
bits : 16 - 31 (16 bit)
CH5CFGR1
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SITP : SITP
bits : 0 - 1 (2 bit)
SPICKSEL : SPICKSEL
bits : 2 - 3 (2 bit)
SCDEN : SCDEN
bits : 5 - 5 (1 bit)
CKABEN : CKABEN
bits : 6 - 6 (1 bit)
CHEN : CHEN
bits : 7 - 7 (1 bit)
CHINSEL : CHINSEL
bits : 8 - 8 (1 bit)
DATMPX : DATMPX
bits : 12 - 13 (2 bit)
DATPACK : DATPACK
bits : 14 - 15 (2 bit)
DFSDM control register 1
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DFEN : DFSDM enable
bits : 0 - 0 (1 bit)
JSWSTART : Start a conversion of the injected group of channels
bits : 1 - 1 (1 bit)
JSYNC : Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger
bits : 3 - 3 (1 bit)
JSCAN : Scanning conversion mode for injected conversions
bits : 4 - 4 (1 bit)
JDMAEN : DMA channel enabled to read data for the injected channel group
bits : 5 - 5 (1 bit)
JEXTSEL : Trigger signal selection for launching injected conversions
bits : 8 - 12 (5 bit)
JEXTEN : Trigger enable and trigger edge selection for injected conversions
bits : 13 - 14 (2 bit)
RSWSTART : Software start of a conversion on the regular channel
bits : 17 - 17 (1 bit)
RCONT : Continuous mode selection for regular conversions
bits : 18 - 18 (1 bit)
RSYNC : Launch regular conversion synchronously with DFSDM0
bits : 19 - 19 (1 bit)
RDMAEN : DMA channel enabled to read data for the regular conversion
bits : 21 - 21 (1 bit)
RCH : Regular channel selection
bits : 24 - 26 (3 bit)
FAST : Fast conversion mode selection for regular conversions
bits : 29 - 29 (1 bit)
AWFSEL : Analog watchdog fast mode select
bits : 30 - 30 (1 bit)
CH5CFGR2
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTRBS : DTRBS
bits : 3 - 7 (5 bit)
OFFSET : OFFSET
bits : 8 - 31 (24 bit)
DFSDM control register 1
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DFEN : DFSDM enable
bits : 0 - 0 (1 bit)
JSWSTART : Start a conversion of the injected group of channels
bits : 1 - 1 (1 bit)
JSYNC : Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger
bits : 3 - 3 (1 bit)
JSCAN : Scanning conversion mode for injected conversions
bits : 4 - 4 (1 bit)
JDMAEN : DMA channel enabled to read data for the injected channel group
bits : 5 - 5 (1 bit)
JEXTSEL : Trigger signal selection for launching injected conversions
bits : 8 - 12 (5 bit)
JEXTEN : Trigger enable and trigger edge selection for injected conversions
bits : 13 - 14 (2 bit)
RSWSTART : Software start of a conversion on the regular channel
bits : 17 - 17 (1 bit)
RCONT : Continuous mode selection for regular conversions
bits : 18 - 18 (1 bit)
RSYNC : Launch regular conversion synchronously with DFSDM0
bits : 19 - 19 (1 bit)
RDMAEN : DMA channel enabled to read data for the regular conversion
bits : 21 - 21 (1 bit)
RCH : Regular channel selection
bits : 24 - 26 (3 bit)
FAST : Fast conversion mode selection for regular conversions
bits : 29 - 29 (1 bit)
AWFSEL : Analog watchdog fast mode select
bits : 30 - 30 (1 bit)
CH5AWSCDR
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SCDT : SCDT
bits : 0 - 7 (8 bit)
BKSCD : BKSCD
bits : 12 - 15 (4 bit)
AWFOSR : AWFOSR
bits : 16 - 20 (5 bit)
AWFORD : AWFORD
bits : 22 - 23 (2 bit)
DFSDM control register 1
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DFEN : DFSDM enable
bits : 0 - 0 (1 bit)
JSWSTART : Start a conversion of the injected group of channels
bits : 1 - 1 (1 bit)
JSYNC : Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger
bits : 3 - 3 (1 bit)
JSCAN : Scanning conversion mode for injected conversions
bits : 4 - 4 (1 bit)
JDMAEN : DMA channel enabled to read data for the injected channel group
bits : 5 - 5 (1 bit)
JEXTSEL : Trigger signal selection for launching injected conversions
bits : 8 - 12 (5 bit)
JEXTEN : Trigger enable and trigger edge selection for injected conversions
bits : 13 - 14 (2 bit)
RSWSTART : Software start of a conversion on the regular channel
bits : 17 - 17 (1 bit)
RCONT : Continuous mode selection for regular conversions
bits : 18 - 18 (1 bit)
RSYNC : Launch regular conversion synchronously with DFSDM0
bits : 19 - 19 (1 bit)
RDMAEN : DMA channel enabled to read data for the regular conversion
bits : 21 - 21 (1 bit)
RCH : Regular channel selection
bits : 24 - 26 (3 bit)
FAST : Fast conversion mode selection for regular conversions
bits : 29 - 29 (1 bit)
AWFSEL : Analog watchdog fast mode select
bits : 30 - 30 (1 bit)
CH5WDATR
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDATA : WDATA
bits : 0 - 15 (16 bit)
DFSDM control register 1
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DFEN : DFSDM enable
bits : 0 - 0 (1 bit)
JSWSTART : Start a conversion of the injected group of channels
bits : 1 - 1 (1 bit)
JSYNC : Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger
bits : 3 - 3 (1 bit)
JSCAN : Scanning conversion mode for injected conversions
bits : 4 - 4 (1 bit)
JDMAEN : DMA channel enabled to read data for the injected channel group
bits : 5 - 5 (1 bit)
JEXTSEL : Trigger signal selection for launching injected conversions
bits : 8 - 12 (5 bit)
JEXTEN : Trigger enable and trigger edge selection for injected conversions
bits : 13 - 14 (2 bit)
RSWSTART : Software start of a conversion on the regular channel
bits : 17 - 17 (1 bit)
RCONT : Continuous mode selection for regular conversions
bits : 18 - 18 (1 bit)
RSYNC : Launch regular conversion synchronously with DFSDM0
bits : 19 - 19 (1 bit)
RDMAEN : DMA channel enabled to read data for the regular conversion
bits : 21 - 21 (1 bit)
RCH : Regular channel selection
bits : 24 - 26 (3 bit)
FAST : Fast conversion mode selection for regular conversions
bits : 29 - 29 (1 bit)
AWFSEL : Analog watchdog fast mode select
bits : 30 - 30 (1 bit)
CH5DATINR
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INDAT0 : INDAT0
bits : 0 - 15 (16 bit)
INDAT1 : INDAT1
bits : 16 - 31 (16 bit)
DFSDM control register 2
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
JEOCIE : Injected end of conversion interrupt enable
bits : 0 - 0 (1 bit)
REOCIE : Regular end of conversion interrupt enable
bits : 1 - 1 (1 bit)
JOVRIE : Injected data overrun interrupt enable
bits : 2 - 2 (1 bit)
ROVRIE : Regular data overrun interrupt enable
bits : 3 - 3 (1 bit)
AWDIE : Analog watchdog interrupt enable
bits : 4 - 4 (1 bit)
SCDIE : Short-circuit detector interrupt enable
bits : 5 - 5 (1 bit)
CKABIE : Clock absence interrupt enable
bits : 6 - 6 (1 bit)
EXCH : Extremes detector channel selection
bits : 8 - 15 (8 bit)
AWDCH : Analog watchdog channel selection
bits : 16 - 23 (8 bit)
channel y delay register
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLSSKP : PLSSKP
bits : 0 - 5 (6 bit)
DFSDM control register 2
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
JEOCIE : Injected end of conversion interrupt enable
bits : 0 - 0 (1 bit)
REOCIE : Regular end of conversion interrupt enable
bits : 1 - 1 (1 bit)
JOVRIE : Injected data overrun interrupt enable
bits : 2 - 2 (1 bit)
ROVRIE : Regular data overrun interrupt enable
bits : 3 - 3 (1 bit)
AWDIE : Analog watchdog interrupt enable
bits : 4 - 4 (1 bit)
SCDIE : Short-circuit detector interrupt enable
bits : 5 - 5 (1 bit)
CKABIE : Clock absence interrupt enable
bits : 6 - 6 (1 bit)
EXCH : Extremes detector channel selection
bits : 8 - 15 (8 bit)
AWDCH : Analog watchdog channel selection
bits : 16 - 23 (8 bit)
DFSDM control register 2
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
JEOCIE : Injected end of conversion interrupt enable
bits : 0 - 0 (1 bit)
REOCIE : Regular end of conversion interrupt enable
bits : 1 - 1 (1 bit)
JOVRIE : Injected data overrun interrupt enable
bits : 2 - 2 (1 bit)
ROVRIE : Regular data overrun interrupt enable
bits : 3 - 3 (1 bit)
AWDIE : Analog watchdog interrupt enable
bits : 4 - 4 (1 bit)
SCDIE : Short-circuit detector interrupt enable
bits : 5 - 5 (1 bit)
CKABIE : Clock absence interrupt enable
bits : 6 - 6 (1 bit)
EXCH : Extremes detector channel selection
bits : 8 - 15 (8 bit)
AWDCH : Analog watchdog channel selection
bits : 16 - 23 (8 bit)
DFSDM control register 2
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
JEOCIE : Injected end of conversion interrupt enable
bits : 0 - 0 (1 bit)
REOCIE : Regular end of conversion interrupt enable
bits : 1 - 1 (1 bit)
JOVRIE : Injected data overrun interrupt enable
bits : 2 - 2 (1 bit)
ROVRIE : Regular data overrun interrupt enable
bits : 3 - 3 (1 bit)
AWDIE : Analog watchdog interrupt enable
bits : 4 - 4 (1 bit)
SCDIE : Short-circuit detector interrupt enable
bits : 5 - 5 (1 bit)
CKABIE : Clock absence interrupt enable
bits : 6 - 6 (1 bit)
EXCH : Extremes detector channel selection
bits : 8 - 15 (8 bit)
AWDCH : Analog watchdog channel selection
bits : 16 - 23 (8 bit)
channel watchdog filter data register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDATA : WDATA
bits : 0 - 15 (16 bit)
DFSDM channel configuration 3 register 1
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SITP : Serial interface type for channel 3
bits : 0 - 1 (2 bit)
SPICKSEL : SPI clock select for channel 3
bits : 2 - 3 (2 bit)
SCDEN : Short-circuit detector enable on channel 3
bits : 5 - 5 (1 bit)
CKABEN : Clock absence detector enable on channel 3
bits : 6 - 6 (1 bit)
CHEN : Channel 3 enable
bits : 7 - 7 (1 bit)
CHINSEL : Channel inputs selection
bits : 8 - 8 (1 bit)
DATMPX : Input data multiplexer for channel 3
bits : 12 - 13 (2 bit)
DATPACK : Data packing mode in DFSDM_CHDATINyR register
bits : 14 - 15 (2 bit)
CKOUTDIV : Output serial clock divider
bits : 16 - 23 (8 bit)
CKOUTSRC : Output serial clock source selection
bits : 30 - 30 (1 bit)
DFSDMEN : Global enable for DFSDM interface
bits : 31 - 31 (1 bit)
CH6CFGR1
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SITP : SITP
bits : 0 - 1 (2 bit)
SPICKSEL : SPICKSEL
bits : 2 - 3 (2 bit)
SCDEN : SCDEN
bits : 5 - 5 (1 bit)
CKABEN : CKABEN
bits : 6 - 6 (1 bit)
CHEN : CHEN
bits : 7 - 7 (1 bit)
CHINSEL : CHINSEL
bits : 8 - 8 (1 bit)
DATMPX : DATMPX
bits : 12 - 13 (2 bit)
DATPACK : DATPACK
bits : 14 - 15 (2 bit)
DFSDM interrupt and status register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
JEOCF : End of injected conversion flag
bits : 0 - 0 (1 bit)
REOCF : End of regular conversion flag
bits : 1 - 1 (1 bit)
JOVRF : Injected conversion overrun flag
bits : 2 - 2 (1 bit)
ROVRF : Regular conversion overrun flag
bits : 3 - 3 (1 bit)
AWDF : Analog watchdog
bits : 4 - 4 (1 bit)
JCIP : Injected conversion in progress status
bits : 13 - 13 (1 bit)
RCIP : Regular conversion in progress status
bits : 14 - 14 (1 bit)
CKABF : Clock absence flag
bits : 16 - 23 (8 bit)
SCDF : short-circuit detector flag
bits : 24 - 31 (8 bit)
CH6CFGR2
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTRBS : DTRBS
bits : 3 - 7 (5 bit)
OFFSET : OFFSET
bits : 8 - 31 (24 bit)
DFSDM interrupt and status register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
JEOCF : End of injected conversion flag
bits : 0 - 0 (1 bit)
REOCF : End of regular conversion flag
bits : 1 - 1 (1 bit)
JOVRF : Injected conversion overrun flag
bits : 2 - 2 (1 bit)
ROVRF : Regular conversion overrun flag
bits : 3 - 3 (1 bit)
AWDF : Analog watchdog
bits : 4 - 4 (1 bit)
JCIP : Injected conversion in progress status
bits : 13 - 13 (1 bit)
RCIP : Regular conversion in progress status
bits : 14 - 14 (1 bit)
CKABF : Clock absence flag
bits : 16 - 23 (8 bit)
SCDF : short-circuit detector flag
bits : 24 - 31 (8 bit)
CH6AWSCDR
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SCDT : SCDT
bits : 0 - 7 (8 bit)
BKSCD : BKSCD
bits : 12 - 15 (4 bit)
AWFOSR : AWFOSR
bits : 16 - 20 (5 bit)
AWFORD : AWFORD
bits : 22 - 23 (2 bit)
DFSDM interrupt and status register
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
JEOCF : End of injected conversion flag
bits : 0 - 0 (1 bit)
REOCF : End of regular conversion flag
bits : 1 - 1 (1 bit)
JOVRF : Injected conversion overrun flag
bits : 2 - 2 (1 bit)
ROVRF : Regular conversion overrun flag
bits : 3 - 3 (1 bit)
AWDF : Analog watchdog
bits : 4 - 4 (1 bit)
JCIP : Injected conversion in progress status
bits : 13 - 13 (1 bit)
RCIP : Regular conversion in progress status
bits : 14 - 14 (1 bit)
CKABF : Clock absence flag
bits : 16 - 23 (8 bit)
SCDF : short-circuit detector flag
bits : 24 - 31 (8 bit)
CH6WDATR
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDATA : WDATA
bits : 0 - 15 (16 bit)
DFSDM interrupt and status register
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
JEOCF : End of injected conversion flag
bits : 0 - 0 (1 bit)
REOCF : End of regular conversion flag
bits : 1 - 1 (1 bit)
JOVRF : Injected conversion overrun flag
bits : 2 - 2 (1 bit)
ROVRF : Regular conversion overrun flag
bits : 3 - 3 (1 bit)
AWDF : Analog watchdog
bits : 4 - 4 (1 bit)
JCIP : Injected conversion in progress status
bits : 13 - 13 (1 bit)
RCIP : Regular conversion in progress status
bits : 14 - 14 (1 bit)
CKABF : Clock absence flag
bits : 16 - 23 (8 bit)
SCDF : short-circuit detector flag
bits : 24 - 31 (8 bit)
CH6DATINR
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INDAT0 : INDAT0
bits : 0 - 15 (16 bit)
INDAT1 : INDAT1
bits : 16 - 31 (16 bit)
DFSDM interrupt flag clear register
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRJOVRF : Clear the injected conversion overrun flag
bits : 2 - 2 (1 bit)
CLRROVRF : Clear the regular conversion overrun flag
bits : 3 - 3 (1 bit)
CLRCKABF : Clear the clock absence flag
bits : 16 - 23 (8 bit)
CLRSCDF : Clear the short-circuit detector flag
bits : 24 - 31 (8 bit)
channel y delay register
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLSSKP : PLSSKP
bits : 0 - 5 (6 bit)
DFSDM interrupt flag clear register
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRJOVRF : Clear the injected conversion overrun flag
bits : 2 - 2 (1 bit)
CLRROVRF : Clear the regular conversion overrun flag
bits : 3 - 3 (1 bit)
CLRCKABF : Clear the clock absence flag
bits : 16 - 23 (8 bit)
CLRSCDF : Clear the short-circuit detector flag
bits : 24 - 31 (8 bit)
DFSDM interrupt flag clear register
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRJOVRF : Clear the injected conversion overrun flag
bits : 2 - 2 (1 bit)
CLRROVRF : Clear the regular conversion overrun flag
bits : 3 - 3 (1 bit)
CLRCKABF : Clear the clock absence flag
bits : 16 - 23 (8 bit)
CLRSCDF : Clear the short-circuit detector flag
bits : 24 - 31 (8 bit)
DFSDM interrupt flag clear register
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRJOVRF : Clear the injected conversion overrun flag
bits : 2 - 2 (1 bit)
CLRROVRF : Clear the regular conversion overrun flag
bits : 3 - 3 (1 bit)
CLRCKABF : Clear the clock absence flag
bits : 16 - 23 (8 bit)
CLRSCDF : Clear the short-circuit detector flag
bits : 24 - 31 (8 bit)
CH7CFGR1
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SITP : SITP
bits : 0 - 1 (2 bit)
SPICKSEL : SPICKSEL
bits : 2 - 3 (2 bit)
SCDEN : SCDEN
bits : 5 - 5 (1 bit)
CKABEN : CKABEN
bits : 6 - 6 (1 bit)
CHEN : CHEN
bits : 7 - 7 (1 bit)
CHINSEL : CHINSEL
bits : 8 - 8 (1 bit)
DATMPX : DATMPX
bits : 12 - 13 (2 bit)
DATPACK : DATPACK
bits : 14 - 15 (2 bit)
DFSDM injected channel group selection register
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
JCHG : Injected channel group selection
bits : 0 - 7 (8 bit)
CH7CFGR2
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTRBS : DTRBS
bits : 3 - 7 (5 bit)
OFFSET : OFFSET
bits : 8 - 31 (24 bit)
DFSDM injected channel group selection register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
JCHG : Injected channel group selection
bits : 0 - 7 (8 bit)
CH7AWSCDR
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SCDT : SCDT
bits : 0 - 7 (8 bit)
BKSCD : BKSCD
bits : 12 - 15 (4 bit)
AWFOSR : AWFOSR
bits : 16 - 20 (5 bit)
AWFORD : AWFORD
bits : 22 - 23 (2 bit)
DFSDM injected channel group selection register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
JCHG : Injected channel group selection
bits : 0 - 7 (8 bit)
CH7WDATR
address_offset : 0xEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDATA : WDATA
bits : 0 - 15 (16 bit)
DFSDM injected channel group selection register
address_offset : 0xEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
JCHG : Injected channel group selection
bits : 0 - 7 (8 bit)
CH7DATINR
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INDAT0 : INDAT0
bits : 0 - 15 (16 bit)
INDAT1 : INDAT1
bits : 16 - 31 (16 bit)
DFSDM filter control register
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IOSR : Integrator oversampling ratio (averaging length)
bits : 0 - 7 (8 bit)
FOSR : Sinc filter oversampling ratio (decimation rate)
bits : 16 - 25 (10 bit)
FORD : Sinc filter order
bits : 29 - 31 (3 bit)
channel y delay register
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLSSKP : PLSSKP
bits : 0 - 5 (6 bit)
DFSDM filter control register
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IOSR : Integrator oversampling ratio (averaging length)
bits : 0 - 7 (8 bit)
FOSR : Sinc filter oversampling ratio (decimation rate)
bits : 16 - 25 (10 bit)
FORD : Sinc filter order
bits : 29 - 31 (3 bit)
DFSDM filter control register
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IOSR : Integrator oversampling ratio (averaging length)
bits : 0 - 7 (8 bit)
FOSR : Sinc filter oversampling ratio (decimation rate)
bits : 16 - 25 (10 bit)
FORD : Sinc filter order
bits : 29 - 31 (3 bit)
DFSDM filter control register
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IOSR : Integrator oversampling ratio (averaging length)
bits : 0 - 7 (8 bit)
FOSR : Sinc filter oversampling ratio (decimation rate)
bits : 16 - 25 (10 bit)
FORD : Sinc filter order
bits : 29 - 31 (3 bit)
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