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address_offset : 0x0 Bytes (0x0)
size : 0x41 byte (0x0)
mem_usage : registers
protection : not protected
CPUID base register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Revision : Revision number
bits : 0 - 3 (4 bit)
PartNo : Part number of the processor
bits : 4 - 15 (12 bit)
Constant : Reads as 0xF
bits : 16 - 19 (4 bit)
Variant : Variant number
bits : 20 - 23 (4 bit)
Implementer : Implementer code
bits : 24 - 31 (8 bit)
System control register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLEEPONEXIT : SLEEPONEXIT
bits : 1 - 1 (1 bit)
SLEEPDEEP : SLEEPDEEP
bits : 2 - 2 (1 bit)
SEVEONPEND : Send Event on Pending bit
bits : 4 - 4 (1 bit)
Configuration and control register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NONBASETHRDENA : Configures how the processor enters Thread mode
bits : 0 - 0 (1 bit)
USERSETMPEND : USERSETMPEND
bits : 1 - 1 (1 bit)
UNALIGN__TRP : UNALIGN_ TRP
bits : 3 - 3 (1 bit)
DIV_0_TRP : DIV_0_TRP
bits : 4 - 4 (1 bit)
BFHFNMIGN : BFHFNMIGN
bits : 8 - 8 (1 bit)
STKALIGN : STKALIGN
bits : 9 - 9 (1 bit)
DC : DC
bits : 16 - 16 (1 bit)
IC : IC
bits : 17 - 17 (1 bit)
BP : BP
bits : 18 - 18 (1 bit)
System handler priority registers
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_4 : Priority of system handler 4
bits : 0 - 7 (8 bit)
PRI_5 : Priority of system handler 5
bits : 8 - 15 (8 bit)
PRI_6 : Priority of system handler 6
bits : 16 - 23 (8 bit)
System handler priority registers
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_11 : Priority of system handler 11
bits : 24 - 31 (8 bit)
System handler priority registers
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_14 : Priority of system handler 14
bits : 16 - 23 (8 bit)
PRI_15 : Priority of system handler 15
bits : 24 - 31 (8 bit)
System handler control and state register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MEMFAULTACT : Memory management fault exception active bit
bits : 0 - 0 (1 bit)
BUSFAULTACT : Bus fault exception active bit
bits : 1 - 1 (1 bit)
USGFAULTACT : Usage fault exception active bit
bits : 3 - 3 (1 bit)
SVCALLACT : SVC call active bit
bits : 7 - 7 (1 bit)
MONITORACT : Debug monitor active bit
bits : 8 - 8 (1 bit)
PENDSVACT : PendSV exception active bit
bits : 10 - 10 (1 bit)
SYSTICKACT : SysTick exception active bit
bits : 11 - 11 (1 bit)
USGFAULTPENDED : Usage fault exception pending bit
bits : 12 - 12 (1 bit)
MEMFAULTPENDED : Memory management fault exception pending bit
bits : 13 - 13 (1 bit)
BUSFAULTPENDED : Bus fault exception pending bit
bits : 14 - 14 (1 bit)
SVCALLPENDED : SVC call pending bit
bits : 15 - 15 (1 bit)
MEMFAULTENA : Memory management fault enable bit
bits : 16 - 16 (1 bit)
BUSFAULTENA : Bus fault enable bit
bits : 17 - 17 (1 bit)
USGFAULTENA : Usage fault enable bit
bits : 18 - 18 (1 bit)
System handler control and state register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MEMFAULTACT : Memory management fault exception active bit
bits : 0 - 0 (1 bit)
BUSFAULTACT : Bus fault exception active bit
bits : 1 - 1 (1 bit)
USGFAULTACT : Usage fault exception active bit
bits : 3 - 3 (1 bit)
SVCALLACT : SVC call active bit
bits : 7 - 7 (1 bit)
MONITORACT : Debug monitor active bit
bits : 8 - 8 (1 bit)
PENDSVACT : PendSV exception active bit
bits : 10 - 10 (1 bit)
SYSTICKACT : SysTick exception active bit
bits : 11 - 11 (1 bit)
USGFAULTPENDED : Usage fault exception pending bit
bits : 12 - 12 (1 bit)
MEMFAULTPENDED : Memory management fault exception pending bit
bits : 13 - 13 (1 bit)
BUSFAULTPENDED : Bus fault exception pending bit
bits : 14 - 14 (1 bit)
SVCALLPENDED : SVC call pending bit
bits : 15 - 15 (1 bit)
MEMFAULTENA : Memory management fault enable bit
bits : 16 - 16 (1 bit)
BUSFAULTENA : Bus fault enable bit
bits : 17 - 17 (1 bit)
USGFAULTENA : Usage fault enable bit
bits : 18 - 18 (1 bit)
Configurable fault status register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IACCVIOL : IACCVIOL
bits : 0 - 0 (1 bit)
DACCVIOL : DACCVIOL
bits : 1 - 1 (1 bit)
MUNSTKERR : MUNSTKERR
bits : 3 - 3 (1 bit)
MSTKERR : MSTKERR
bits : 4 - 4 (1 bit)
MLSPERR : MLSPERR
bits : 5 - 5 (1 bit)
MMARVALID : MMARVALID
bits : 7 - 7 (1 bit)
IBUSERR : Instruction bus error
bits : 8 - 8 (1 bit)
PRECISERR : Precise data bus error
bits : 9 - 9 (1 bit)
IMPRECISERR : Imprecise data bus error
bits : 10 - 10 (1 bit)
UNSTKERR : Bus fault on unstacking for a return from exception
bits : 11 - 11 (1 bit)
STKERR : Bus fault on stacking for exception entry
bits : 12 - 12 (1 bit)
LSPERR : Bus fault on floating-point lazy state preservation
bits : 13 - 13 (1 bit)
BFARVALID : Bus Fault Address Register (BFAR) valid flag
bits : 15 - 15 (1 bit)
UNDEFINSTR : Undefined instruction usage fault
bits : 16 - 16 (1 bit)
INVSTATE : Invalid state usage fault
bits : 17 - 17 (1 bit)
INVPC : Invalid PC load usage fault
bits : 18 - 18 (1 bit)
NOCP : No coprocessor usage fault.
bits : 19 - 19 (1 bit)
UNALIGNED : Unaligned access usage fault
bits : 24 - 24 (1 bit)
DIVBYZERO : Divide by zero usage fault
bits : 25 - 25 (1 bit)
Hard fault status register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VECTTBL : Vector table hard fault
bits : 1 - 1 (1 bit)
FORCED : Forced hard fault
bits : 30 - 30 (1 bit)
DEBUG_VT : Reserved for Debug use
bits : 31 - 31 (1 bit)
Memory management fault address register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDRESS : Memory management fault address
bits : 0 - 31 (32 bit)
Bus fault address register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDRESS : Bus fault address
bits : 0 - 31 (32 bit)
Interrupt control and state register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VECTACTIVE : Active vector
bits : 0 - 8 (9 bit)
RETTOBASE : Return to base level
bits : 11 - 11 (1 bit)
VECTPENDING : Pending vector
bits : 12 - 18 (7 bit)
ISRPENDING : Interrupt pending flag
bits : 22 - 22 (1 bit)
PENDSTCLR : SysTick exception clear-pending bit
bits : 25 - 25 (1 bit)
PENDSTSET : SysTick exception set-pending bit
bits : 26 - 26 (1 bit)
PENDSVCLR : PendSV clear-pending bit
bits : 27 - 27 (1 bit)
PENDSVSET : PendSV set-pending bit
bits : 28 - 28 (1 bit)
NMIPENDSET : NMI set-pending bit.
bits : 31 - 31 (1 bit)
Vector table offset register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TBLOFF : Vector table base offset field
bits : 9 - 29 (21 bit)
Application interrupt and reset control register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VECTRESET : VECTRESET
bits : 0 - 0 (1 bit)
VECTCLRACTIVE : VECTCLRACTIVE
bits : 1 - 1 (1 bit)
SYSRESETREQ : SYSRESETREQ
bits : 2 - 2 (1 bit)
PRIGROUP : PRIGROUP
bits : 8 - 10 (3 bit)
ENDIANESS : ENDIANESS
bits : 15 - 15 (1 bit)
VECTKEYSTAT : Register key
bits : 16 - 31 (16 bit)
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