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address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
ADC interrupt and status register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADRDY : ADC ready
bits : 0 - 0 (1 bit)
EOSMP : End of sampling flag
bits : 1 - 1 (1 bit)
EOC : End of conversion flag
bits : 2 - 2 (1 bit)
EOS : End of regular sequence flag
bits : 3 - 3 (1 bit)
OVR : ADC overrun
bits : 4 - 4 (1 bit)
JEOC : Injected channel end of conversion flag
bits : 5 - 5 (1 bit)
JEOS : Injected channel end of sequence flag
bits : 6 - 6 (1 bit)
AWD1 : Analog watchdog 1 flag
bits : 7 - 7 (1 bit)
AWD2 : Analog watchdog 2 flag
bits : 8 - 8 (1 bit)
AWD3 : Analog watchdog 3 flag
bits : 9 - 9 (1 bit)
JQOVF : Injected context queue overflow
bits : 10 - 10 (1 bit)
ADC Common status register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : ISR
reset_Mask : 0x0
ADRDY_MST : Master ADC ready
bits : 0 - 0 (1 bit)
EOSMP_MST : End of Sampling phase flag of the master ADC
bits : 1 - 1 (1 bit)
EOC_MST : End of regular conversion of the master ADC
bits : 2 - 2 (1 bit)
EOS_MST : End of regular sequence flag of the master ADC
bits : 3 - 3 (1 bit)
OVR_MST : Overrun flag of the master ADC
bits : 4 - 4 (1 bit)
JEOC_MST : End of injected conversion flag of the master ADC
bits : 5 - 5 (1 bit)
JEOS_MST : End of injected sequence flag of the master ADC
bits : 6 - 6 (1 bit)
AWD1_MST : Analog watchdog 1 flag of the master ADC
bits : 7 - 7 (1 bit)
AWD2_MST : Analog watchdog 2 flag of the master ADC
bits : 8 - 8 (1 bit)
AWD3_MST : Analog watchdog 3 flag of the master ADC
bits : 9 - 9 (1 bit)
JQOVF_MST : Injected Context Queue Overflow flag of the master ADC
bits : 10 - 10 (1 bit)
ADRDY_SLV : Slave ADC ready
bits : 16 - 16 (1 bit)
EOSMP_SLV : End of Sampling phase flag of the slave ADC
bits : 17 - 17 (1 bit)
EOC_SLV : End of regular conversion of the slave ADC
bits : 18 - 18 (1 bit)
EOS_SLV : End of regular sequence flag of the slave ADC
bits : 19 - 19 (1 bit)
OVR_SLV : Overrun flag of the slave ADC
bits : 20 - 20 (1 bit)
JEOC_SLV : End of injected conversion flag of the slave ADC
bits : 21 - 21 (1 bit)
JEOS_SLV : End of injected sequence flag of the slave ADC
bits : 22 - 22 (1 bit)
AWD1_SLV : Analog watchdog 1 flag of the slave ADC
bits : 23 - 23 (1 bit)
AWD2_SLV : Analog watchdog 2 flag of the slave ADC
bits : 24 - 24 (1 bit)
AWD3_SLV : Analog watchdog 3 flag of the slave ADC
bits : 25 - 25 (1 bit)
JQOVF_SLV : Injected Context Queue Overflow flag of the slave ADC
bits : 26 - 26 (1 bit)
ADC sample time register 1
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SMP1 : Channel 1 sampling time selection
bits : 3 - 5 (3 bit)
SMP2 : Channel 2 sampling time selection
bits : 6 - 8 (3 bit)
SMP3 : Channel 3 sampling time selection
bits : 9 - 11 (3 bit)
SMP4 : Channel 4 sampling time selection
bits : 12 - 14 (3 bit)
SMP5 : Channel 5 sampling time selection
bits : 15 - 17 (3 bit)
SMP6 : Channel 6 sampling time selection
bits : 18 - 20 (3 bit)
SMP7 : Channel 7 sampling time selection
bits : 21 - 23 (3 bit)
SMP8 : Channel 8 sampling time selection
bits : 24 - 26 (3 bit)
SMP9 : Channel 9 sampling time selection
bits : 27 - 29 (3 bit)
ADC sample time register 2
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SMP10 : Channel 10 sampling time selection
bits : 0 - 2 (3 bit)
SMP11 : Channel 11 sampling time selection
bits : 3 - 5 (3 bit)
SMP12 : Channel 12 sampling time selection
bits : 6 - 8 (3 bit)
SMP13 : Channel 13 sampling time selection
bits : 9 - 11 (3 bit)
SMP14 : Channel 14 sampling time selection
bits : 12 - 14 (3 bit)
SMP15 : Channel 15 sampling time selection
bits : 15 - 17 (3 bit)
SMP16 : Channel 16 sampling time selection
bits : 18 - 20 (3 bit)
SMP17 : Channel 17 sampling time selection
bits : 21 - 23 (3 bit)
SMP18 : Channel 18 sampling time selection
bits : 24 - 26 (3 bit)
ADC watchdog threshold register 1
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LT1 : Analog watchdog 1 lower threshold
bits : 0 - 11 (12 bit)
HT1 : Analog watchdog 1 higher threshold
bits : 16 - 27 (12 bit)
ADC watchdog threshold register 2
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LT2 : Analog watchdog 2 lower threshold
bits : 0 - 7 (8 bit)
HT2 : Analog watchdog 2 higher threshold
bits : 16 - 23 (8 bit)
read-write
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LT3 : Analog watchdog 3 lower threshold
bits : 0 - 7 (8 bit)
HT3 : Analog watchdog 3 higher threshold
bits : 16 - 23 (8 bit)
ADC regular sequence register 1
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
L : Regular channel sequence length
bits : 0 - 3 (4 bit)
SQ1 : 1st conversion in regular sequence
bits : 6 - 10 (5 bit)
SQ2 : 2nd conversion in regular sequence
bits : 12 - 16 (5 bit)
SQ3 : 3rd conversion in regular sequence
bits : 18 - 22 (5 bit)
SQ4 : 4th conversion in regular sequence
bits : 24 - 28 (5 bit)
ADC regular sequence register 2
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SQ5 : 5th conversion in regular sequence
bits : 0 - 4 (5 bit)
SQ6 : 6th conversion in regular sequence
bits : 6 - 10 (5 bit)
SQ7 : 7th conversion in regular sequence
bits : 12 - 16 (5 bit)
SQ8 : 8th conversion in regular sequence
bits : 18 - 22 (5 bit)
SQ9 : 9th conversion in regular sequence
bits : 24 - 28 (5 bit)
ADC regular sequence register 3
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SQ10 : 10th conversion in regular sequence
bits : 0 - 4 (5 bit)
SQ11 : 11th conversion in regular sequence
bits : 6 - 10 (5 bit)
SQ12 : 13th conversion in regular sequence
bits : 12 - 16 (5 bit)
SQ13 : 13th conversion in regular sequence
bits : 18 - 22 (5 bit)
SQ14 : 14th conversion in regular sequence
bits : 24 - 28 (5 bit)
ADC regular sequence register 4
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SQ15 : 15th conversion in regular sequence
bits : 0 - 4 (5 bit)
SQ16 : 16th conversion in regular sequence
bits : 6 - 10 (5 bit)
ADC interrupt enable register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADRDYIE : ADC ready interrupt enable
bits : 0 - 0 (1 bit)
EOSMPIE : End of sampling flag interrupt enable for regular conversions
bits : 1 - 1 (1 bit)
EOCIE : End of regular conversion interrupt enable
bits : 2 - 2 (1 bit)
EOSIE : End of regular sequence of conversions interrupt enable
bits : 3 - 3 (1 bit)
OVRIE : Overrun interrupt enable
bits : 4 - 4 (1 bit)
JEOCIE : End of injected conversion interrupt enable
bits : 5 - 5 (1 bit)
JEOSIE : End of injected sequence of conversions interrupt enable
bits : 6 - 6 (1 bit)
AWD1IE : Analog watchdog 1 interrupt enable
bits : 7 - 7 (1 bit)
AWD2IE : Analog watchdog 2 interrupt enable
bits : 8 - 8 (1 bit)
AWD3IE : Analog watchdog 3 interrupt enable
bits : 9 - 9 (1 bit)
JQOVFIE : Injected context queue overflow interrupt enable
bits : 10 - 10 (1 bit)
ADC regular Data Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDATA : Regular Data converted
bits : 0 - 15 (16 bit)
ADC injected sequence register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
JL : Injected channel sequence length
bits : 0 - 1 (2 bit)
JEXTSEL : External Trigger Selection for injected group
bits : 2 - 5 (4 bit)
JEXTEN : External Trigger Enable and Polarity Selection for injected channels
bits : 6 - 7 (2 bit)
JSQ1 : 1st conversion in the injected sequence
bits : 8 - 12 (5 bit)
JSQ2 : 2nd conversion in the injected sequence
bits : 14 - 18 (5 bit)
JSQ3 : 3rd conversion in the injected sequence
bits : 20 - 24 (5 bit)
JSQ4 : 4th conversion in the injected sequence
bits : 26 - 30 (5 bit)
ADC offset register1
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OFFSET1 : Data offset 1 for the channel programmed into bits OFFSET1_CH
bits : 0 - 11 (12 bit)
OFFSET1_CH : Channel selection for the Data offset 1
bits : 26 - 30 (5 bit)
OFFSET1_EN : Offset1 Enable
bits : 31 - 31 (1 bit)
ADC offset register2
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OFFSET2 : Data offset 2 for the channel programmed into bits OFFSET2_CH
bits : 0 - 11 (12 bit)
OFFSET2_CH : Channel selection for the Data offset 2
bits : 26 - 30 (5 bit)
OFFSET2_EN : Offset 2 Enable
bits : 31 - 31 (1 bit)
ADC offset register3
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OFFSET3 : Data offset 3 for the channel programmed into bits OFFSET3_CH
bits : 0 - 11 (12 bit)
OFFSET3_CH : Channel selection for the Data offset 3
bits : 26 - 30 (5 bit)
OFFSET3_EN : Offset y Enable
bits : 31 - 31 (1 bit)
ADC offset register4
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OFFSET4 : Data offset 4 for the channel programmed into bits OFFSET4_CH
bits : 0 - 11 (12 bit)
OFFSET4_CH : Channel selection for the Data offset 4
bits : 26 - 30 (5 bit)
OFFSET4_EN : Offset 4 Enable
bits : 31 - 31 (1 bit)
ADC control register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADEN : ADC enable control
bits : 0 - 0 (1 bit)
access : read-only
ADDIS : ADC disable command
bits : 1 - 1 (1 bit)
access : read-only
ADSTART : ADC start of regular conversion
bits : 2 - 2 (1 bit)
access : read-only
JADSTART : ADC start of injected conversion
bits : 3 - 3 (1 bit)
access : read-only
ADSTP : ADC stop of regular conversion command
bits : 4 - 4 (1 bit)
access : read-only
JADST : ADC stop of injected conversion command
bits : 5 - 5 (1 bit)
access : read-only
ADVREGEN : ADC voltage regulator enable
bits : 28 - 29 (2 bit)
access : read-write
ADCALDIF : Differential mode for calibration
bits : 30 - 30 (1 bit)
access : read-write
ADCAL : ADC calibration
bits : 31 - 31 (1 bit)
access : read-only
ADC common control register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CR
reset_Mask : 0x0
CKMODE : ADC clock mode
bits : 16 - 17 (2 bit)
VREFEN : VREFINT enable
bits : 22 - 22 (1 bit)
TSEN : Temperature sensor enable
bits : 23 - 23 (1 bit)
VBATEN : VBATEN
bits : 24 - 24 (1 bit)
ADC offset register1
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
JDATA : Injected data
bits : 0 - 15 (16 bit)
ADC offset register2
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
JDATA : Injected data
bits : 0 - 15 (16 bit)
ADC offset register3
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
JDATA : Injected data
bits : 0 - 15 (16 bit)
ADC offset register4
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
JDATA : Injected data
bits : 0 - 15 (16 bit)
ADC Analog Watchdog 2 Configuration Register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AWD2CH : Analog watchdog 2 channel selection
bits : 1 - 18 (18 bit)
ADC Analog Watchdog 3 Configuration Register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AWD3CH : Analog watchdog 3 channel selection
bits : 1 - 18 (18 bit)
ADC Differential Mode Selection Register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIFSEL : Differential mode for channels 15 to 1
bits : 1 - 18 (18 bit)
ADC Calibration Factors
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CALFACT_S : Calibration Factors In Single-Ended mode
bits : 0 - 6 (7 bit)
CALFACT_D : Calibration Factors in differential mode
bits : 16 - 22 (7 bit)
ADC configuration register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAEN : Direct memory access enable
bits : 0 - 0 (1 bit)
DMACFG : Direct memory access configuration
bits : 1 - 1 (1 bit)
RES : Data resolution
bits : 3 - 4 (2 bit)
ALIGN : Data alignment
bits : 5 - 5 (1 bit)
EXTSEL : External trigger selection for regular group
bits : 6 - 9 (4 bit)
EXTEN : External trigger enable and polarity selection for regular channels
bits : 10 - 11 (2 bit)
OVRMOD : Overrun Mode
bits : 12 - 12 (1 bit)
CONT : Single / continuous conversion mode for regular conversions
bits : 13 - 13 (1 bit)
AUTDLY : Delayed conversion mode
bits : 14 - 14 (1 bit)
DISCEN : Discontinuous mode for regular channels
bits : 16 - 16 (1 bit)
DISCNUM : Discontinuous mode channel count
bits : 17 - 19 (3 bit)
JDISCEN : Discontinuous mode on injected channels
bits : 20 - 20 (1 bit)
JQM : JSQR queue mode
bits : 21 - 21 (1 bit)
AWD1SGL : Enable the watchdog 1 on a single channel or on all channels
bits : 22 - 22 (1 bit)
AWD1EN : Analog watchdog 1 enable on regular channels
bits : 23 - 23 (1 bit)
JAWD1EN : Analog watchdog 1 enable on injected channels
bits : 24 - 24 (1 bit)
JAUTO : Automatic injected group conversion
bits : 25 - 25 (1 bit)
AWD1CH : Analog watchdog 1 channel selection
bits : 26 - 30 (5 bit)
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