\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
DMA mode register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWR : Software Reset
bits : 0 - 0 (1 bit)
access : read-write
DA : DMA Tx or Rx Arbitration Scheme
bits : 1 - 1 (1 bit)
access : read-only
TXPR : Transmit priority
bits : 11 - 11 (1 bit)
access : read-only
PR : Priority ratio
bits : 12 - 14 (3 bit)
access : read-only
INTM : Interrupt Mode
bits : 16 - 16 (1 bit)
access : read-write
Channel control register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MSS : Maximum Segment Size
bits : 0 - 13 (14 bit)
PBLX8 : 8xPBL mode
bits : 16 - 16 (1 bit)
DSL : Descriptor Skip Length
bits : 18 - 20 (3 bit)
Channel transmit control register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ST : Start or Stop Transmission Command
bits : 0 - 0 (1 bit)
OSF : Operate on Second Packet
bits : 4 - 4 (1 bit)
TSE : TCP Segmentation Enabled
bits : 12 - 12 (1 bit)
TXPBL : Transmit Programmable Burst Length
bits : 16 - 21 (6 bit)
Channel receive control register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SR : Start or Stop Receive Command
bits : 0 - 0 (1 bit)
RBSZ : Receive Buffer size
bits : 1 - 14 (14 bit)
RXPBL : RXPBL
bits : 16 - 21 (6 bit)
RPF : DMA Rx Channel Packet Flush
bits : 31 - 31 (1 bit)
Channel Tx descriptor list address register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDESLA : Start of Transmit List
bits : 2 - 31 (30 bit)
Channel Rx descriptor list address register
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDESLA : Start of Receive List
bits : 2 - 31 (30 bit)
Channel Tx descriptor tail pointer register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDT : Transmit Descriptor Tail Pointer
bits : 2 - 31 (30 bit)
Channel Rx descriptor tail pointer register
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDT : Receive Descriptor Tail Pointer
bits : 2 - 31 (30 bit)
Channel Tx descriptor ring length register
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDRL : Transmit Descriptor Ring Length
bits : 0 - 9 (10 bit)
Channel Rx descriptor ring length register
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDRL : Receive Descriptor Ring Length
bits : 0 - 9 (10 bit)
Channel interrupt enable register
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIE : Transmit Interrupt Enable
bits : 0 - 0 (1 bit)
TXSE : Transmit Stopped Enable
bits : 1 - 1 (1 bit)
TBUE : Transmit Buffer Unavailable Enable
bits : 2 - 2 (1 bit)
RIE : Receive Interrupt Enable
bits : 6 - 6 (1 bit)
RBUE : Receive Buffer Unavailable Enable
bits : 7 - 7 (1 bit)
RSE : Receive Stopped Enable
bits : 8 - 8 (1 bit)
RWTE : Receive Watchdog Timeout Enable
bits : 9 - 9 (1 bit)
ETIE : Early Transmit Interrupt Enable
bits : 10 - 10 (1 bit)
ERIE : Early Receive Interrupt Enable
bits : 11 - 11 (1 bit)
FBEE : Fatal Bus Error Enable
bits : 12 - 12 (1 bit)
CDEE : Context Descriptor Error Enable
bits : 13 - 13 (1 bit)
AIE : Abnormal Interrupt Summary Enable
bits : 14 - 14 (1 bit)
NIE : Normal Interrupt Summary Enable
bits : 15 - 15 (1 bit)
Channel Rx interrupt watchdog timer register
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RWT : Receive Interrupt Watchdog Timer Count
bits : 0 - 7 (8 bit)
Channel current application transmit descriptor register
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CURTDESAPTR : Application Transmit Descriptor Address Pointer
bits : 0 - 31 (32 bit)
Channel current application receive descriptor register
address_offset : 0x14C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CURRDESAPTR : Application Receive Descriptor Address Pointer
bits : 0 - 31 (32 bit)
Channel current application transmit buffer register
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CURTBUFAPTR : Application Transmit Buffer Address Pointer
bits : 0 - 31 (32 bit)
Channel current application receive buffer register
address_offset : 0x15C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CURRBUFAPTR : Application Receive Buffer Address Pointer
bits : 0 - 31 (32 bit)
Channel status register
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TI : Transmit Interrupt
bits : 0 - 0 (1 bit)
access : read-write
TPS : Transmit Process Stopped
bits : 1 - 1 (1 bit)
access : read-write
TBU : Transmit Buffer Unavailable
bits : 2 - 2 (1 bit)
access : read-write
RI : Receive Interrupt
bits : 6 - 6 (1 bit)
access : read-write
RBU : Receive Buffer Unavailable
bits : 7 - 7 (1 bit)
access : read-write
RPS : Receive Process Stopped
bits : 8 - 8 (1 bit)
access : read-write
RWT : Receive Watchdog Timeout
bits : 9 - 9 (1 bit)
access : read-write
ET : Early Transmit Interrupt
bits : 10 - 10 (1 bit)
access : read-write
ER : Early Receive Interrupt
bits : 11 - 11 (1 bit)
access : read-write
FBE : Fatal Bus Error
bits : 12 - 12 (1 bit)
access : read-write
CDE : Context Descriptor Error
bits : 13 - 13 (1 bit)
access : read-write
AIS : Abnormal Interrupt Summary
bits : 14 - 14 (1 bit)
access : read-write
NIS : Normal Interrupt Summary
bits : 15 - 15 (1 bit)
access : read-write
TEB : Tx DMA Error Bits
bits : 16 - 18 (3 bit)
access : read-only
REB : Rx DMA Error Bits
bits : 19 - 21 (3 bit)
access : read-only
Channel missed frame count register
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MFC : Dropped Packet Counters
bits : 0 - 10 (11 bit)
MFCO : Overflow status of the MFC Counter
bits : 15 - 15 (1 bit)
System bus mode register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FB : Fixed Burst Length
bits : 0 - 0 (1 bit)
access : read-write
AAL : Address-Aligned Beats
bits : 12 - 12 (1 bit)
access : read-write
MB : Mixed Burst
bits : 14 - 14 (1 bit)
access : read-only
RB : Rebuild INCRx Burst
bits : 15 - 15 (1 bit)
access : read-only
Interrupt status register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DC0IS : DMA Channel Interrupt Status
bits : 0 - 0 (1 bit)
MTLIS : MTL Interrupt Status
bits : 16 - 16 (1 bit)
MACIS : MAC Interrupt Status
bits : 17 - 17 (1 bit)
Debug status register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
AXWHSTS : AHB Master Write Channel
bits : 0 - 0 (1 bit)
RPS0 : DMA Channel Receive Process State
bits : 8 - 11 (4 bit)
TPS0 : DMA Channel Transmit Process State
bits : 12 - 15 (4 bit)
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