\n
address_offset : 0x0 Bytes (0x0)
size : 0xBDF byte (0x0)
mem_usage : registers
protection : not protected
TX_SINGLE_COLLISION_GOOD_PACKETS (TX_SINGLE_COLLISION_GOOD_PACKETS)
TX_MULTIPLE_COLLISION_GOOD_PACKETS (TX_MULTIPLE_COLLISION_GOOD_PACKETS)
Operating mode configuration register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RE : Receiver Enable
bits : 0 - 0 (1 bit)
TE : TE
bits : 1 - 1 (1 bit)
PRELEN : PRELEN
bits : 2 - 3 (2 bit)
DC : DC
bits : 4 - 4 (1 bit)
BL : BL
bits : 5 - 6 (2 bit)
DR : DR
bits : 8 - 8 (1 bit)
DCRS : DCRS
bits : 9 - 9 (1 bit)
DO : DO
bits : 10 - 10 (1 bit)
ECRSFD : ECRSFD
bits : 11 - 11 (1 bit)
LM : LM
bits : 12 - 12 (1 bit)
DM : DM
bits : 13 - 13 (1 bit)
FES : FES
bits : 14 - 14 (1 bit)
JE : JE
bits : 16 - 16 (1 bit)
JD : JD
bits : 17 - 17 (1 bit)
WD : WD
bits : 19 - 19 (1 bit)
ACS : ACS
bits : 20 - 20 (1 bit)
CST : CST
bits : 21 - 21 (1 bit)
S2KP : S2KP
bits : 22 - 22 (1 bit)
GPSLCE : GPSLCE
bits : 23 - 23 (1 bit)
IPG : IPG
bits : 24 - 26 (3 bit)
IPC : IPC
bits : 27 - 27 (1 bit)
SARC : SARC
bits : 28 - 30 (3 bit)
ARPEN : ARPEN
bits : 31 - 31 (1 bit)
Hash Table 0 register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HT31T0 : HT31T0
bits : 0 - 31 (32 bit)
Version register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SNPSVER : SNPSVER
bits : 0 - 7 (8 bit)
USERVER : USERVER
bits : 8 - 15 (8 bit)
Debug register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RPESTS : RPESTS
bits : 0 - 0 (1 bit)
RFCFCSTS : RFCFCSTS
bits : 1 - 2 (2 bit)
TPESTS : TPESTS
bits : 16 - 16 (1 bit)
TFCSTS : TFCSTS
bits : 17 - 18 (2 bit)
HW feature 1 register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXFIFOSIZE : RXFIFOSIZE
bits : 0 - 4 (5 bit)
TXFIFOSIZE : TXFIFOSIZE
bits : 6 - 10 (5 bit)
OSTEN : OSTEN
bits : 11 - 11 (1 bit)
PTOEN : PTOEN
bits : 12 - 12 (1 bit)
ADVTHWORD : ADVTHWORD
bits : 13 - 13 (1 bit)
ADDR64 : ADDR64
bits : 14 - 15 (2 bit)
DCBEN : DCBEN
bits : 16 - 16 (1 bit)
SPHEN : SPHEN
bits : 17 - 17 (1 bit)
TSOEN : TSOEN
bits : 18 - 18 (1 bit)
DBGMEMA : DBGMEMA
bits : 19 - 19 (1 bit)
AVSEL : AVSEL
bits : 20 - 20 (1 bit)
HASHTBLSZ : HASHTBLSZ
bits : 24 - 25 (2 bit)
L3L4FNUM : L3L4FNUM
bits : 27 - 30 (4 bit)
HW feature 2 register
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXQCNT : RXQCNT
bits : 0 - 3 (4 bit)
TXQCNT : TXQCNT
bits : 6 - 9 (4 bit)
RXCHCNT : RXCHCNT
bits : 12 - 15 (4 bit)
TXCHCNT : TXCHCNT
bits : 18 - 21 (4 bit)
PPSOUTNUM : PPSOUTNUM
bits : 24 - 26 (3 bit)
AUXSNAPNUM : AUXSNAPNUM
bits : 28 - 30 (3 bit)
Hash Table 1 register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HT63T32 : HT63T32
bits : 0 - 31 (32 bit)
MDIO address register
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MB : MB
bits : 0 - 0 (1 bit)
C45E : C45E
bits : 1 - 1 (1 bit)
GOC : GOC
bits : 2 - 3 (2 bit)
SKAP : SKAP
bits : 4 - 4 (1 bit)
CR : CR
bits : 8 - 11 (4 bit)
NTC : NTC
bits : 12 - 14 (3 bit)
RDA : RDA
bits : 16 - 20 (5 bit)
PA : PA
bits : 21 - 25 (5 bit)
BTB : BTB
bits : 26 - 26 (1 bit)
PSE : PSE
bits : 27 - 27 (1 bit)
MDIO data register
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MD : MD
bits : 0 - 15 (16 bit)
RA : RA
bits : 16 - 31 (16 bit)
Address 0 high register
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDRHI : ADDRHI
bits : 0 - 15 (16 bit)
access : read-write
AE : AE
bits : 31 - 31 (1 bit)
access : read-only
Address 0 low register
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDRLO : ADDRLO
bits : 0 - 31 (32 bit)
Address 1 high register
address_offset : 0x308 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDRHI : ADDRHI
bits : 0 - 15 (16 bit)
MBC : MBC
bits : 24 - 29 (6 bit)
SA : SA
bits : 30 - 30 (1 bit)
AE : AE
bits : 31 - 31 (1 bit)
Address 1 low register
address_offset : 0x30C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDRLO : ADDRLO
bits : 0 - 31 (32 bit)
Address 2 high register
address_offset : 0x310 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDRHI : ADDRHI
bits : 0 - 15 (16 bit)
MBC : MBC
bits : 24 - 29 (6 bit)
SA : SA
bits : 30 - 30 (1 bit)
AE : AE
bits : 31 - 31 (1 bit)
Address 2 low register
address_offset : 0x314 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDRLO : ADDRLO
bits : 0 - 31 (32 bit)
Address 3 high register
address_offset : 0x318 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDRHI : ADDRHI
bits : 0 - 15 (16 bit)
MBC : MBC
bits : 24 - 29 (6 bit)
SA : SA
bits : 30 - 30 (1 bit)
AE : AE
bits : 31 - 31 (1 bit)
Address 3 low register
address_offset : 0x31C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDRLO : ADDRLO
bits : 0 - 31 (32 bit)
Extended operating mode configuration register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPSL : GPSL
bits : 0 - 13 (14 bit)
DCRCC : DCRCC
bits : 16 - 16 (1 bit)
SPEN : SPEN
bits : 17 - 17 (1 bit)
USP : USP
bits : 18 - 18 (1 bit)
EIPGEN : EIPGEN
bits : 24 - 24 (1 bit)
EIPG : EIPG
bits : 25 - 29 (5 bit)
VLAN tag register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VL : VL
bits : 0 - 15 (16 bit)
ETV : ETV
bits : 16 - 16 (1 bit)
VTIM : VTIM
bits : 17 - 17 (1 bit)
ESVL : ESVL
bits : 18 - 18 (1 bit)
ERSVLM : ERSVLM
bits : 19 - 19 (1 bit)
DOVLTC : DOVLTC
bits : 20 - 20 (1 bit)
EVLS : EVLS
bits : 21 - 22 (2 bit)
EVLRXS : EVLRXS
bits : 24 - 24 (1 bit)
VTHM : VTHM
bits : 25 - 25 (1 bit)
EDVLP : EDVLP
bits : 26 - 26 (1 bit)
ERIVLT : ERIVLT
bits : 27 - 27 (1 bit)
EIVLS : EIVLS
bits : 28 - 29 (2 bit)
EIVLRXS : EIVLRXS
bits : 31 - 31 (1 bit)
VLAN Hash table register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VLHT : VLHT
bits : 0 - 15 (16 bit)
VLAN inclusion register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VLT : VLT
bits : 0 - 15 (16 bit)
VLC : VLC
bits : 16 - 17 (2 bit)
VLP : VLP
bits : 18 - 18 (1 bit)
CSVL : CSVL
bits : 19 - 19 (1 bit)
VLTI : VLTI
bits : 20 - 20 (1 bit)
Inner VLAN inclusion register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VLT : VLT
bits : 0 - 15 (16 bit)
VLC : VLC
bits : 16 - 17 (2 bit)
VLP : VLP
bits : 18 - 18 (1 bit)
CSVL : CSVL
bits : 19 - 19 (1 bit)
VLTI : VLTI
bits : 20 - 20 (1 bit)
Tx Queue flow control register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FCB_BPA : FCB_BPA
bits : 0 - 0 (1 bit)
TFE : TFE
bits : 1 - 1 (1 bit)
PLT : PLT
bits : 4 - 6 (3 bit)
DZPQ : DZPQ
bits : 7 - 7 (1 bit)
PT : PT
bits : 16 - 31 (16 bit)
MMC control register
address_offset : 0x700 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNTRST : CNTRST
bits : 0 - 0 (1 bit)
CNTSTOPRO : CNTSTOPRO
bits : 1 - 1 (1 bit)
RSTONRD : RSTONRD
bits : 2 - 2 (1 bit)
CNTFREEZ : CNTFREEZ
bits : 3 - 3 (1 bit)
CNTPRST : CNTPRST
bits : 4 - 4 (1 bit)
CNTPRSTLVL : CNTPRSTLVL
bits : 5 - 5 (1 bit)
UCDBC : UCDBC
bits : 8 - 8 (1 bit)
MMC Rx interrupt register
address_offset : 0x704 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXCRCERPIS : RXCRCERPIS
bits : 5 - 5 (1 bit)
RXALGNERPIS : RXALGNERPIS
bits : 6 - 6 (1 bit)
RXUCGPIS : RXUCGPIS
bits : 17 - 17 (1 bit)
RXLPIUSCIS : RXLPIUSCIS
bits : 26 - 26 (1 bit)
RXLPITRCIS : RXLPITRCIS
bits : 27 - 27 (1 bit)
MMC Tx interrupt register
address_offset : 0x708 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXSCOLGPIS : TXSCOLGPIS
bits : 14 - 14 (1 bit)
TXMCOLGPIS : TXMCOLGPIS
bits : 15 - 15 (1 bit)
TXGPKTIS : TXGPKTIS
bits : 21 - 21 (1 bit)
TXLPIUSCIS : TXLPIUSCIS
bits : 26 - 26 (1 bit)
TXLPITRCIS : TXLPITRCIS
bits : 27 - 27 (1 bit)
MMC Rx interrupt mask register
address_offset : 0x70C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXCRCERPIM : RXCRCERPIM
bits : 5 - 5 (1 bit)
access : read-write
RXALGNERPIM : RXALGNERPIM
bits : 6 - 6 (1 bit)
access : read-write
RXUCGPIM : RXUCGPIM
bits : 17 - 17 (1 bit)
access : read-write
RXLPIUSCIM : RXLPIUSCIM
bits : 26 - 26 (1 bit)
access : read-write
RXLPITRCIM : RXLPITRCIM
bits : 27 - 27 (1 bit)
access : read-only
MMC Tx interrupt mask register
address_offset : 0x710 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXSCOLGPIM : TXSCOLGPIM
bits : 14 - 14 (1 bit)
access : read-write
TXMCOLGPIM : TXMCOLGPIM
bits : 15 - 15 (1 bit)
access : read-write
TXGPKTIM : TXGPKTIM
bits : 21 - 21 (1 bit)
access : read-write
TXLPIUSCIM : TXLPIUSCIM
bits : 26 - 26 (1 bit)
access : read-write
TXLPITRCIM : TXLPITRCIM
bits : 27 - 27 (1 bit)
access : read-only
Tx single collision good packets register
address_offset : 0x74C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXSNGLCOLG : TXSNGLCOLG
bits : 0 - 31 (32 bit)
Tx multiple collision good packets register
address_offset : 0x750 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXMULTCOLG : TXMULTCOLG
bits : 0 - 31 (32 bit)
Tx packet count good register
address_offset : 0x768 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXPKTG : TXPKTG
bits : 0 - 31 (32 bit)
Rx CRC error packets register
address_offset : 0x794 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXCRCERR : RXCRCERR
bits : 0 - 31 (32 bit)
Rx alignment error packets register
address_offset : 0x798 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXALGNERR : RXALGNERR
bits : 0 - 31 (32 bit)
Rx unicast packets good register
address_offset : 0x7C4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXUCASTG : RXUCASTG
bits : 0 - 31 (32 bit)
Tx LPI microsecond timer register
address_offset : 0x7EC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXLPIUSC : TXLPIUSC
bits : 0 - 31 (32 bit)
Tx LPI transition counter register
address_offset : 0x7F0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXLPITRC : TXLPITRC
bits : 0 - 31 (32 bit)
Rx LPI microsecond counter register
address_offset : 0x7F4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXLPIUSC : RXLPIUSC
bits : 0 - 31 (32 bit)
Rx LPI transition counter register
address_offset : 0x7F8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXLPITRC : RXLPITRC
bits : 0 - 31 (32 bit)
Packet filtering control register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PR : PR
bits : 0 - 0 (1 bit)
HUC : HUC
bits : 1 - 1 (1 bit)
HMC : HMC
bits : 2 - 2 (1 bit)
DAIF : DAIF
bits : 3 - 3 (1 bit)
PM : PM
bits : 4 - 4 (1 bit)
DBF : DBF
bits : 5 - 5 (1 bit)
PCF : PCF
bits : 6 - 7 (2 bit)
SAIF : SAIF
bits : 8 - 8 (1 bit)
SAF : SAF
bits : 9 - 9 (1 bit)
HPF : HPF
bits : 10 - 10 (1 bit)
VTFE : VTFE
bits : 16 - 16 (1 bit)
IPFE : IPFE
bits : 20 - 20 (1 bit)
DNTU : DNTU
bits : 21 - 21 (1 bit)
RA : RA
bits : 31 - 31 (1 bit)
Rx flow control register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RFE : RFE
bits : 0 - 0 (1 bit)
UP : UP
bits : 1 - 1 (1 bit)
L3 and L4 control 0 register
address_offset : 0x900 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
L3PEN0 : L3PEN0
bits : 0 - 0 (1 bit)
L3SAM0 : L3SAM0
bits : 2 - 2 (1 bit)
L3SAIM0 : L3SAIM0
bits : 3 - 3 (1 bit)
L3DAM0 : L3DAM0
bits : 4 - 4 (1 bit)
L3DAIM0 : L3DAIM0
bits : 5 - 5 (1 bit)
L3HSBM0 : L3HSBM0
bits : 6 - 10 (5 bit)
L3HDBM0 : L3HDBM0
bits : 11 - 15 (5 bit)
L4PEN0 : L4PEN0
bits : 16 - 16 (1 bit)
L4SPM0 : L4SPM0
bits : 18 - 18 (1 bit)
L4SPIM0 : L4SPIM0
bits : 19 - 19 (1 bit)
L4DPM0 : L4DPM0
bits : 20 - 20 (1 bit)
L4DPIM0 : L4DPIM0
bits : 21 - 21 (1 bit)
Layer4 address filter 0 register
address_offset : 0x904 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
L4SP0 : L4SP0
bits : 0 - 15 (16 bit)
L4DP0 : L4DP0
bits : 16 - 31 (16 bit)
MACL3A00R
address_offset : 0x910 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
L3A00 : L3A00
bits : 0 - 31 (32 bit)
Layer3 address 1 filter 0 register
address_offset : 0x914 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
L3A10 : L3A10
bits : 0 - 31 (32 bit)
Layer3 Address 2 filter 0 register
address_offset : 0x918 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
L3A20 : L3A20
bits : 0 - 31 (32 bit)
Layer3 Address 3 filter 0 register
address_offset : 0x91C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
L3A30 : L3A30
bits : 0 - 31 (32 bit)
L3 and L4 control 1 register
address_offset : 0x930 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
L3PEN1 : L3PEN1
bits : 0 - 0 (1 bit)
L3SAM1 : L3SAM1
bits : 2 - 2 (1 bit)
L3SAIM1 : L3SAIM1
bits : 3 - 3 (1 bit)
L3DAM1 : L3DAM1
bits : 4 - 4 (1 bit)
L3DAIM1 : L3DAIM1
bits : 5 - 5 (1 bit)
L3HSBM1 : L3HSBM1
bits : 6 - 10 (5 bit)
L3HDBM1 : L3HDBM1
bits : 11 - 15 (5 bit)
L4PEN1 : L4PEN1
bits : 16 - 16 (1 bit)
L4SPM1 : L4SPM1
bits : 18 - 18 (1 bit)
L4SPIM1 : L4SPIM1
bits : 19 - 19 (1 bit)
L4DPM1 : L4DPM1
bits : 20 - 20 (1 bit)
L4DPIM1 : L4DPIM1
bits : 21 - 21 (1 bit)
Layer 4 address filter 1 register
address_offset : 0x934 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
L4SP1 : L4SP1
bits : 0 - 15 (16 bit)
L4DP1 : L4DP1
bits : 16 - 31 (16 bit)
Layer3 address 0 filter 1 Register
address_offset : 0x940 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
L3A01 : L3A01
bits : 0 - 31 (32 bit)
Layer3 address 1 filter 1 register
address_offset : 0x944 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
L3A11 : L3A11
bits : 0 - 31 (32 bit)
Layer3 address 2 filter 1 Register
address_offset : 0x948 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
L3A21 : L3A21
bits : 0 - 31 (32 bit)
Layer3 address 3 filter 1 register
address_offset : 0x94C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
L3A31 : L3A31
bits : 0 - 31 (32 bit)
ARP address register
address_offset : 0xAE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARPPA : ARPPA
bits : 0 - 31 (32 bit)
Interrupt status register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PHYIS : PHYIS
bits : 3 - 3 (1 bit)
PMTIS : PMTIS
bits : 4 - 4 (1 bit)
LPIIS : LPIIS
bits : 5 - 5 (1 bit)
MMCIS : MMCIS
bits : 8 - 8 (1 bit)
MMCRXIS : MMCRXIS
bits : 9 - 9 (1 bit)
MMCTXIS : MMCTXIS
bits : 10 - 10 (1 bit)
TSIS : TSIS
bits : 12 - 12 (1 bit)
TXSTSIS : TXSTSIS
bits : 13 - 13 (1 bit)
RXSTSIS : RXSTSIS
bits : 14 - 14 (1 bit)
Timestamp control Register
address_offset : 0xB00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSENA : TSENA
bits : 0 - 0 (1 bit)
access : read-write
TSCFUPDT : TSCFUPDT
bits : 1 - 1 (1 bit)
access : read-write
TSINIT : TSINIT
bits : 2 - 2 (1 bit)
access : read-write
TSUPDT : TSUPDT
bits : 3 - 3 (1 bit)
access : read-write
TSADDREG : TSADDREG
bits : 5 - 5 (1 bit)
access : read-write
TSENALL : TSENALL
bits : 8 - 8 (1 bit)
access : read-write
TSCTRLSSR : TSCTRLSSR
bits : 9 - 9 (1 bit)
access : read-write
TSVER2ENA : TSVER2ENA
bits : 10 - 10 (1 bit)
access : read-write
TSIPENA : TSIPENA
bits : 11 - 11 (1 bit)
access : read-write
TSIPV6ENA : TSIPV6ENA
bits : 12 - 12 (1 bit)
access : read-write
TSIPV4ENA : TSIPV4ENA
bits : 13 - 13 (1 bit)
access : read-write
TSEVNTENA : TSEVNTENA
bits : 14 - 14 (1 bit)
access : read-write
TSMSTRENA : TSMSTRENA
bits : 15 - 15 (1 bit)
access : read-write
SNAPTYPSEL : SNAPTYPSEL
bits : 16 - 17 (2 bit)
access : read-write
TSENMACADDR : TSENMACADDR
bits : 18 - 18 (1 bit)
access : read-write
CSC : CSC
bits : 19 - 19 (1 bit)
access : read-only
TXTSSTSM : TXTSSTSM
bits : 24 - 24 (1 bit)
access : read-write
Sub-second increment register
address_offset : 0xB04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SNSINC : SNSINC
bits : 8 - 15 (8 bit)
SSINC : SSINC
bits : 16 - 23 (8 bit)
System time seconds register
address_offset : 0xB08 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TSS : TSS
bits : 0 - 31 (32 bit)
System time nanoseconds register
address_offset : 0xB0C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TSSS : TSSS
bits : 0 - 30 (31 bit)
System time seconds update register
address_offset : 0xB10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSS : TSS
bits : 0 - 31 (32 bit)
System time nanoseconds update register
address_offset : 0xB14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSSS : TSSS
bits : 0 - 30 (31 bit)
ADDSUB : ADDSUB
bits : 31 - 31 (1 bit)
Timestamp addend register
address_offset : 0xB18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSAR : TSAR
bits : 0 - 31 (32 bit)
Timestamp status register
address_offset : 0xB20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TSSOVF : TSSOVF
bits : 0 - 0 (1 bit)
TSTARGT0 : TSTARGT0
bits : 1 - 1 (1 bit)
AUXTSTRIG : AUXTSTRIG
bits : 2 - 2 (1 bit)
TSTRGTERR0 : TSTRGTERR0
bits : 3 - 3 (1 bit)
TXTSSIS : TXTSSIS
bits : 15 - 15 (1 bit)
ATSSTN : ATSSTN
bits : 16 - 19 (4 bit)
ATSSTM : ATSSTM
bits : 24 - 24 (1 bit)
ATSNS : ATSNS
bits : 25 - 29 (5 bit)
Tx timestamp status nanoseconds register
address_offset : 0xB30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXTSSLO : TXTSSLO
bits : 0 - 30 (31 bit)
TXTSSMIS : TXTSSMIS
bits : 31 - 31 (1 bit)
Tx timestamp status seconds register
address_offset : 0xB34 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXTSSHI : TXTSSHI
bits : 0 - 31 (32 bit)
Interrupt enable register
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PHYIE : PHYIE
bits : 3 - 3 (1 bit)
PMTIE : PMTIE
bits : 4 - 4 (1 bit)
LPIIE : LPIIE
bits : 5 - 5 (1 bit)
TSIE : TSIE
bits : 12 - 12 (1 bit)
TXSTSIE : TXSTSIE
bits : 13 - 13 (1 bit)
RXSTSIE : RXSTSIE
bits : 14 - 14 (1 bit)
Auxiliary control register
address_offset : 0xB40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ATSFC : ATSFC
bits : 0 - 0 (1 bit)
ATSEN0 : ATSEN0
bits : 4 - 4 (1 bit)
ATSEN1 : ATSEN1
bits : 5 - 5 (1 bit)
ATSEN2 : ATSEN2
bits : 6 - 6 (1 bit)
ATSEN3 : ATSEN3
bits : 7 - 7 (1 bit)
Auxiliary timestamp nanoseconds register
address_offset : 0xB48 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
AUXTSLO : AUXTSLO
bits : 0 - 30 (31 bit)
Auxiliary timestamp seconds register
address_offset : 0xB4C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
AUXTSHI : AUXTSHI
bits : 0 - 31 (32 bit)
Timestamp Ingress asymmetric correction register
address_offset : 0xB50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OSTIAC : OSTIAC
bits : 0 - 31 (32 bit)
Timestamp Egress asymmetric correction register
address_offset : 0xB54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OSTEAC : OSTEAC
bits : 0 - 31 (32 bit)
Timestamp Ingress correction nanosecond register
address_offset : 0xB58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSIC : TSIC
bits : 0 - 31 (32 bit)
Timestamp Egress correction nanosecond register
address_offset : 0xB5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSEC : TSEC
bits : 0 - 31 (32 bit)
PPS control register
address_offset : 0xB70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PPSCTRL : PPSCTRL
bits : 0 - 3 (4 bit)
PPSEN0 : PPSEN0
bits : 4 - 4 (1 bit)
TRGTMODSEL0 : TRGTMODSEL0
bits : 5 - 6 (2 bit)
Rx Tx status register
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TJT : TJT
bits : 0 - 0 (1 bit)
NCARR : NCARR
bits : 1 - 1 (1 bit)
LCARR : LCARR
bits : 2 - 2 (1 bit)
EXDEF : EXDEF
bits : 3 - 3 (1 bit)
LCOL : LCOL
bits : 4 - 4 (1 bit)
EXCOL : LCOL
bits : 5 - 5 (1 bit)
RWT : RWT
bits : 8 - 8 (1 bit)
PPS target time seconds register
address_offset : 0xB80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSTRH0 : TSTRH0
bits : 0 - 30 (31 bit)
PPS target time nanoseconds register
address_offset : 0xB84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TTSL0 : TTSL0
bits : 0 - 30 (31 bit)
TRGTBUSY0 : TRGTBUSY0
bits : 31 - 31 (1 bit)
PPS interval register
address_offset : 0xB88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PPSINT0 : PPSINT0
bits : 0 - 31 (32 bit)
PPS width register
address_offset : 0xB8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PPSWIDTH0 : PPSWIDTH0
bits : 0 - 31 (32 bit)
PTP Offload control register
address_offset : 0xBC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PTOEN : PTOEN
bits : 0 - 0 (1 bit)
ASYNCEN : ASYNCEN
bits : 1 - 1 (1 bit)
APDREQEN : APDREQEN
bits : 2 - 2 (1 bit)
ASYNCTRIG : ASYNCTRIG
bits : 4 - 4 (1 bit)
APDREQTRIG : APDREQTRIG
bits : 5 - 5 (1 bit)
DRRDIS : DRRDIS
bits : 6 - 6 (1 bit)
DN : DN
bits : 8 - 15 (8 bit)
PTP Source Port Identity 0 Register
address_offset : 0xBC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPI0 : SPI0
bits : 0 - 31 (32 bit)
PTP Source port identity 1 register
address_offset : 0xBC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPI1 : SPI1
bits : 0 - 31 (32 bit)
PTP Source port identity 2 register
address_offset : 0xBCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPI2 : SPI2
bits : 0 - 15 (16 bit)
Log message interval register
address_offset : 0xBD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LSI : LSI
bits : 0 - 7 (8 bit)
DRSYNCR : DRSYNCR
bits : 8 - 10 (3 bit)
LMPDRI : LMPDRI
bits : 24 - 31 (8 bit)
Watchdog timeout register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WTO : WTO
bits : 0 - 3 (4 bit)
PWE : PWE
bits : 8 - 8 (1 bit)
PMT control status register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWRDWN : PWRDWN
bits : 0 - 0 (1 bit)
access : read-write
MGKPKTEN : MGKPKTEN
bits : 1 - 1 (1 bit)
access : read-write
RWKPKTEN : RWKPKTEN
bits : 2 - 2 (1 bit)
access : read-write
MGKPRCVD : MGKPRCVD
bits : 5 - 5 (1 bit)
access : read-only
RWKPRCVD : RWKPRCVD
bits : 6 - 6 (1 bit)
access : read-only
GLBLUCAST : GLBLUCAST
bits : 9 - 9 (1 bit)
access : read-write
RWKPFE : RWKPFE
bits : 10 - 10 (1 bit)
access : read-write
RWKPTR : RWKPTR
bits : 24 - 28 (5 bit)
access : read-write
RWKFILTRST : RWKFILTRST
bits : 31 - 31 (1 bit)
access : read-write
Remove wakeup packet filter register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MACRWKPFR : MACRWKPFR
bits : 0 - 31 (32 bit)
LPI control status register
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TLPIEN : TLPIEN
bits : 0 - 0 (1 bit)
access : read-only
TLPIEX : TLPIEX
bits : 1 - 1 (1 bit)
access : read-only
RLPIEN : RLPIEN
bits : 2 - 2 (1 bit)
access : read-only
RLPIEX : RLPIEX
bits : 3 - 3 (1 bit)
access : read-only
TLPIST : TLPIST
bits : 8 - 8 (1 bit)
access : read-only
RLPIST : RLPIST
bits : 9 - 9 (1 bit)
access : read-only
LPIEN : LPIEN
bits : 16 - 16 (1 bit)
access : read-write
PLS : PLS
bits : 17 - 17 (1 bit)
access : read-write
PLSEN : PLSEN
bits : 18 - 18 (1 bit)
access : read-write
LPITXA : LPITXA
bits : 19 - 19 (1 bit)
access : read-write
LPITE : LPITE
bits : 20 - 20 (1 bit)
access : read-write
LPI timers control register
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TWT : TWT
bits : 0 - 15 (16 bit)
LST : LST
bits : 16 - 25 (10 bit)
LPI entry timer register
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPIET : LPIET
bits : 0 - 16 (17 bit)
1-microsecond-tick counter register
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIC_1US_CNTR : TIC_1US_CNTR
bits : 0 - 11 (12 bit)
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