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DBGMCU

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

IDCODE

CR

APB1FZ

APB2FZ


IDCODE

MCU Device ID Code Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IDCODE IDCODE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DEV_ID REV_ID

DEV_ID : Device Identifier
bits : 0 - 11 (12 bit)

REV_ID : Revision Identifier
bits : 16 - 31 (16 bit)


CR

Debug MCU Configuration Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DBG_SLEEP DBG_STOP DBG_STANDBY TRACE_IOEN TRACE_MODE

DBG_SLEEP : Debug Sleep mode
bits : 0 - 0 (1 bit)

DBG_STOP : Debug Stop Mode
bits : 1 - 1 (1 bit)

DBG_STANDBY : Debug Standby Mode
bits : 2 - 2 (1 bit)

TRACE_IOEN : Trace pin assignment control
bits : 5 - 5 (1 bit)

TRACE_MODE : Trace pin assignment control
bits : 6 - 7 (2 bit)


APB1FZ

APB Low Freeze Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB1FZ APB1FZ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DBG_TIM2_STOP DBG_TIM3_STOP DBG_TIM4_STOP DBG_TIM5_STOP DBG_TIM6_STOP DBG_TIM7_STOP DBG_TIM12_STOP DBG_TIM13_STOP DBG_TIMER14_STOP DBG_TIM18_STOP DBG_RTC_STOP DBG_WWDG_STOP DBG_IWDG_STOP I2C1_SMBUS_TIMEOUT I2C2_SMBUS_TIMEOUT DBG_CAN_STOP

DBG_TIM2_STOP : Debug Timer 2 stopped when Core is halted
bits : 0 - 0 (1 bit)

DBG_TIM3_STOP : Debug Timer 3 stopped when Core is halted
bits : 1 - 1 (1 bit)

DBG_TIM4_STOP : Debug Timer 4 stopped when Core is halted
bits : 2 - 2 (1 bit)

DBG_TIM5_STOP : Debug Timer 5 stopped when Core is halted
bits : 3 - 3 (1 bit)

DBG_TIM6_STOP : Debug Timer 6 stopped when Core is halted
bits : 4 - 4 (1 bit)

DBG_TIM7_STOP : Debug Timer 7 stopped when Core is halted
bits : 5 - 5 (1 bit)

DBG_TIM12_STOP : Debug Timer 12 stopped when Core is halted
bits : 6 - 6 (1 bit)

DBG_TIM13_STOP : Debug Timer 13 stopped when Core is halted
bits : 7 - 7 (1 bit)

DBG_TIMER14_STOP : Debug Timer 14 stopped when Core is halted
bits : 8 - 8 (1 bit)

DBG_TIM18_STOP : Debug Timer 18 stopped when Core is halted
bits : 9 - 9 (1 bit)

DBG_RTC_STOP : Debug RTC stopped when Core is halted
bits : 10 - 10 (1 bit)

DBG_WWDG_STOP : Debug Window Wachdog stopped when Core is halted
bits : 11 - 11 (1 bit)

DBG_IWDG_STOP : Debug Independent Wachdog stopped when Core is halted
bits : 12 - 12 (1 bit)

I2C1_SMBUS_TIMEOUT : SMBUS timeout mode stopped when Core is halted
bits : 21 - 21 (1 bit)

I2C2_SMBUS_TIMEOUT : SMBUS timeout mode stopped when Core is halted
bits : 22 - 22 (1 bit)

DBG_CAN_STOP : Debug CAN stopped when core is halted
bits : 25 - 25 (1 bit)


APB2FZ

APB High Freeze Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB2FZ APB2FZ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DBG_TIM15_STOP DBG_TIM16_STOP DBG_TIM17_STO DBG_TIM19_STOP

DBG_TIM15_STOP : Debug Timer 15 stopped when Core is halted
bits : 2 - 2 (1 bit)

DBG_TIM16_STOP : Debug Timer 16 stopped when Core is halted
bits : 3 - 3 (1 bit)

DBG_TIM17_STO : Debug Timer 17 stopped when Core is halted
bits : 4 - 4 (1 bit)

DBG_TIM19_STOP : Debug Timer 19 stopped when Core is halted
bits : 5 - 5 (1 bit)



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