\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
FDCAN Core Release Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DAY : Timestamp Day
bits : 0 - 7 (8 bit)
MON : Timestamp Month
bits : 8 - 15 (8 bit)
YEAR : Timestamp Year
bits : 16 - 19 (4 bit)
SUBSTEP : Sub-step of Core release
bits : 20 - 23 (4 bit)
STEP : Step of Core release
bits : 24 - 27 (4 bit)
REL : Core release
bits : 28 - 31 (4 bit)
FDCAN Test Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LBCK : Loop Back mode
bits : 4 - 4 (1 bit)
TX : Loop Back mode
bits : 5 - 6 (2 bit)
RX : Control of Transmit Pin
bits : 7 - 7 (1 bit)
FDCAN TT Trigger Memory Configuration Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMSA : Trigger Memory Start Address
bits : 2 - 15 (14 bit)
TME : Trigger Memory Elements
bits : 16 - 22 (7 bit)
FDCAN TT Reference Message Configuration Register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RID : Reference Identifier.
bits : 0 - 28 (29 bit)
XTD : Extended Identifier
bits : 30 - 30 (1 bit)
RMPS : Reference Message Payload Select
bits : 31 - 31 (1 bit)
FDCAN TT Operation Configuration Register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OM : Operation Mode
bits : 0 - 1 (2 bit)
GEN : Gap Enable
bits : 3 - 3 (1 bit)
TM : Time Master
bits : 4 - 4 (1 bit)
LDSDL : LD of Synchronization Deviation Limit
bits : 5 - 7 (3 bit)
IRTO : Initial Reference Trigger Offset
bits : 8 - 14 (7 bit)
EECS : Enable External Clock Synchronization
bits : 15 - 15 (1 bit)
AWL : Application Watchdog Limit
bits : 16 - 23 (8 bit)
EGTF : Enable Global Time Filtering
bits : 24 - 24 (1 bit)
ECC : Enable Clock Calibration
bits : 25 - 25 (1 bit)
EVTP : Event Trigger Polarity
bits : 26 - 26 (1 bit)
FDCAN TT Matrix Limits Register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCM : Cycle Count Max
bits : 0 - 5 (6 bit)
CSS : Cycle Start Synchronization
bits : 6 - 7 (2 bit)
TXEW : Tx Enable Window
bits : 8 - 11 (4 bit)
ENTT : Expected Number of Tx Triggers
bits : 16 - 27 (12 bit)
FDCAN TUR Configuration Register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NCL : Numerator Configuration Low.
bits : 0 - 15 (16 bit)
DC : Denominator Configuration.
bits : 16 - 29 (14 bit)
ELT : Enable Local Time
bits : 31 - 31 (1 bit)
FDCAN TT Operation Control Register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SGT : Set Global time
bits : 0 - 0 (1 bit)
ECS : External Clock Synchronization
bits : 1 - 1 (1 bit)
SWP : Stop Watch Polarity
bits : 2 - 2 (1 bit)
SWS : Stop Watch Source.
bits : 3 - 4 (2 bit)
RTIE : Register Time Mark Interrupt Pulse Enable
bits : 5 - 5 (1 bit)
TMC : Register Time Mark Compare
bits : 6 - 7 (2 bit)
TTIE : Trigger Time Mark Interrupt Pulse Enable
bits : 8 - 8 (1 bit)
GCS : Gap Control Select
bits : 9 - 9 (1 bit)
FGP : Finish Gap.
bits : 10 - 10 (1 bit)
TMG : Time Mark Gap
bits : 11 - 11 (1 bit)
NIG : Next is Gap
bits : 12 - 12 (1 bit)
ESCN : External Synchronization Control
bits : 13 - 13 (1 bit)
LCKC : TT Operation Control Register Locked
bits : 15 - 15 (1 bit)
FDCAN TT Global Time Preset Register
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NCL : Time Preset
bits : 0 - 15 (16 bit)
CTP : Cycle Time Target Phase
bits : 16 - 31 (16 bit)
FDCAN TT Time Mark Register
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TM : Time Mark
bits : 0 - 15 (16 bit)
TICC : Time Mark Cycle Code
bits : 16 - 22 (7 bit)
LCKM : TT Time Mark Register Locked
bits : 31 - 31 (1 bit)
FDCAN TT Interrupt Register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SBC : Start of Basic Cycle
bits : 0 - 0 (1 bit)
SMC : Start of Matrix Cycle
bits : 1 - 1 (1 bit)
CSM : Change of Synchronization Mode
bits : 2 - 2 (1 bit)
SOG : Start of Gap
bits : 3 - 3 (1 bit)
RTMI : Register Time Mark Interrupt.
bits : 4 - 4 (1 bit)
TTMI : Trigger Time Mark Event Internal
bits : 5 - 5 (1 bit)
SWE : Stop Watch Event
bits : 6 - 6 (1 bit)
GTW : Global Time Wrap
bits : 7 - 7 (1 bit)
GTD : Global Time Discontinuity
bits : 8 - 8 (1 bit)
GTE : Global Time Error
bits : 9 - 9 (1 bit)
TXU : Tx Count Underflow
bits : 10 - 10 (1 bit)
TXO : Tx Count Overflow
bits : 11 - 11 (1 bit)
SE1 : Scheduling Error 1
bits : 12 - 12 (1 bit)
SE2 : Scheduling Error 2
bits : 13 - 13 (1 bit)
ELC : Error Level Changed.
bits : 14 - 14 (1 bit)
IWTG : Initialization Watch Trigger
bits : 15 - 15 (1 bit)
WT : Watch Trigger
bits : 16 - 16 (1 bit)
AW : Application Watchdog
bits : 17 - 17 (1 bit)
CER : Configuration Error
bits : 18 - 18 (1 bit)
FDCAN TT Interrupt Enable Register
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SBCE : Start of Basic Cycle Interrupt Enable
bits : 0 - 0 (1 bit)
SMCE : Start of Matrix Cycle Interrupt Enable
bits : 1 - 1 (1 bit)
CSME : Change of Synchronization Mode Interrupt Enable
bits : 2 - 2 (1 bit)
SOGE : Start of Gap Interrupt Enable
bits : 3 - 3 (1 bit)
RTMIE : Register Time Mark Interrupt Enable
bits : 4 - 4 (1 bit)
TTMIE : Trigger Time Mark Event Internal Interrupt Enable
bits : 5 - 5 (1 bit)
SWEE : Stop Watch Event Interrupt Enable
bits : 6 - 6 (1 bit)
GTWE : Global Time Wrap Interrupt Enable
bits : 7 - 7 (1 bit)
GTDE : Global Time Discontinuity Interrupt Enable
bits : 8 - 8 (1 bit)
GTEE : Global Time Error Interrupt Enable
bits : 9 - 9 (1 bit)
TXUE : Tx Count Underflow Interrupt Enable
bits : 10 - 10 (1 bit)
TXOE : Tx Count Overflow Interrupt Enable
bits : 11 - 11 (1 bit)
SE1E : Scheduling Error 1 Interrupt Enable
bits : 12 - 12 (1 bit)
SE2E : Scheduling Error 2 Interrupt Enable
bits : 13 - 13 (1 bit)
ELCE : Change Error Level Interrupt Enable
bits : 14 - 14 (1 bit)
IWTGE : Initialization Watch Trigger Interrupt Enable
bits : 15 - 15 (1 bit)
WTE : Watch Trigger Interrupt Enable
bits : 16 - 16 (1 bit)
AWE : Application Watchdog Interrupt Enable
bits : 17 - 17 (1 bit)
CERE : Configuration Error Interrupt Enable
bits : 18 - 18 (1 bit)
FDCAN TT Interrupt Line Select Register
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SBCL : Start of Basic Cycle Interrupt Line
bits : 0 - 0 (1 bit)
SMCL : Start of Matrix Cycle Interrupt Line
bits : 1 - 1 (1 bit)
CSML : Change of Synchronization Mode Interrupt Line
bits : 2 - 2 (1 bit)
SOGL : Start of Gap Interrupt Line
bits : 3 - 3 (1 bit)
RTMIL : Register Time Mark Interrupt Line
bits : 4 - 4 (1 bit)
TTMIL : Trigger Time Mark Event Internal Interrupt Line
bits : 5 - 5 (1 bit)
SWEL : Stop Watch Event Interrupt Line
bits : 6 - 6 (1 bit)
GTWL : Global Time Wrap Interrupt Line
bits : 7 - 7 (1 bit)
GTDL : Global Time Discontinuity Interrupt Line
bits : 8 - 8 (1 bit)
GTEL : Global Time Error Interrupt Line
bits : 9 - 9 (1 bit)
TXUL : Tx Count Underflow Interrupt Line
bits : 10 - 10 (1 bit)
TXOL : Tx Count Overflow Interrupt Line
bits : 11 - 11 (1 bit)
SE1L : Scheduling Error 1 Interrupt Line
bits : 12 - 12 (1 bit)
SE2L : Scheduling Error 2 Interrupt Line
bits : 13 - 13 (1 bit)
ELCL : Change Error Level Interrupt Line
bits : 14 - 14 (1 bit)
IWTGL : Initialization Watch Trigger Interrupt Line
bits : 15 - 15 (1 bit)
WTL : Watch Trigger Interrupt Line
bits : 16 - 16 (1 bit)
AWL : Application Watchdog Interrupt Line
bits : 17 - 17 (1 bit)
CERL : Configuration Error Interrupt Line
bits : 18 - 18 (1 bit)
FDCAN TT Operation Status Register
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EL : Error Level
bits : 0 - 1 (2 bit)
MS : Master State.
bits : 2 - 3 (2 bit)
SYS : Synchronization State
bits : 4 - 5 (2 bit)
GTP : Quality of Global Time Phase
bits : 6 - 6 (1 bit)
QCS : Quality of Clock Speed
bits : 7 - 7 (1 bit)
RTO : Reference Trigger Offset
bits : 8 - 15 (8 bit)
WGTD : Wait for Global Time Discontinuity
bits : 22 - 22 (1 bit)
GFI : Gap Finished Indicator.
bits : 23 - 23 (1 bit)
TMP : Time Master Priority
bits : 24 - 26 (3 bit)
GSI : Gap Started Indicator.
bits : 27 - 27 (1 bit)
WFE : Wait for Event
bits : 28 - 28 (1 bit)
AWE : Application Watchdog Event
bits : 29 - 29 (1 bit)
WECS : Wait for External Clock Synchronization
bits : 30 - 30 (1 bit)
SPL : Schedule Phase Lock
bits : 31 - 31 (1 bit)
FDCAN TUR Numerator Actual Register
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NAV : Numerator Actual Value
bits : 0 - 17 (18 bit)
FDCAN TT Local and Global Time Register
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LT : Local Time
bits : 0 - 15 (16 bit)
GT : Global Time
bits : 16 - 31 (16 bit)
FDCAN TT Cycle Time and Count Register
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CT : Cycle Time
bits : 0 - 15 (16 bit)
CC : Cycle Count
bits : 16 - 21 (6 bit)
FDCAN TT Capture Time Register
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CT : Cycle Count Value
bits : 0 - 5 (6 bit)
SWV : Stop Watch Value
bits : 16 - 31 (16 bit)
FDCAN RAM Watchdog Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WDC : Watchdog configuration
bits : 0 - 7 (8 bit)
WDV : Watchdog value
bits : 8 - 15 (8 bit)
FDCAN TT Cycle Sync Mark Register
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CSM : Cycle Sync Mark
bits : 0 - 15 (16 bit)
FDCAN CC Control Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INIT : Initialization
bits : 0 - 0 (1 bit)
CCE : Configuration Change Enable
bits : 1 - 1 (1 bit)
ASM : ASM Restricted Operation Mode
bits : 2 - 2 (1 bit)
CSA : Clock Stop Acknowledge
bits : 3 - 3 (1 bit)
CSR : Clock Stop Request
bits : 4 - 4 (1 bit)
MON : Bus Monitoring Mode
bits : 5 - 5 (1 bit)
DAR : Disable Automatic Retransmission
bits : 6 - 6 (1 bit)
TEST : Test Mode Enable
bits : 7 - 7 (1 bit)
FDOE : FD Operation Enable
bits : 8 - 8 (1 bit)
BSE : FDCAN Bit Rate Switching
bits : 9 - 9 (1 bit)
PXHD : Protocol Exception Handling Disable
bits : 12 - 12 (1 bit)
EFBI : Edge Filtering during Bus Integration
bits : 13 - 13 (1 bit)
TXP : TXP
bits : 14 - 14 (1 bit)
NISO : Non ISO Operation
bits : 15 - 15 (1 bit)
FDCAN Nominal Bit Timing and Prescaler Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSEG2 : Nominal Time segment after sample point
bits : 0 - 6 (7 bit)
NTSEG1 : Nominal Time segment before sample point
bits : 8 - 15 (8 bit)
NBRP : Bit Rate Prescaler
bits : 16 - 24 (9 bit)
NSJW : NSJW: Nominal (Re)Synchronization Jump Width
bits : 25 - 31 (7 bit)
FDCAN Timestamp Counter Configuration Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSS : Timestamp Select
bits : 0 - 1 (2 bit)
TCP : Timestamp Counter Prescaler
bits : 16 - 19 (4 bit)
FDCAN Timestamp Counter Value Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSC : Timestamp Counter
bits : 0 - 15 (16 bit)
FDCAN Timeout Counter Configuration Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ETOC : Enable Timeout Counter
bits : 0 - 0 (1 bit)
TOS : Timeout Select
bits : 1 - 2 (2 bit)
TOP : Timeout Period
bits : 16 - 31 (16 bit)
FDCAN Timeout Counter Value Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOC : Timeout Counter
bits : 0 - 15 (16 bit)
FDCAN TT Trigger Select Register
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWTDEL : Stop watch trigger input selection
bits : 0 - 1 (2 bit)
EVTSEL : Event trigger input selection
bits : 4 - 5 (2 bit)
FDCAN Core Release Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ETV : Endiannes Test Value
bits : 0 - 31 (32 bit)
FDCAN Error Counter Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TEC : Transmit Error Counter
bits : 0 - 7 (8 bit)
TREC : Receive Error Counter
bits : 8 - 14 (7 bit)
RP : Receive Error Passive
bits : 15 - 15 (1 bit)
CEL : AN Error Logging
bits : 16 - 23 (8 bit)
FDCAN Protocol Status Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LEC : Last Error Code
bits : 0 - 2 (3 bit)
ACT : Activity
bits : 3 - 4 (2 bit)
EP : Error Passive
bits : 5 - 5 (1 bit)
EW : Warning Status
bits : 6 - 6 (1 bit)
BO : Bus_Off Status
bits : 7 - 7 (1 bit)
DLEC : Data Last Error Code
bits : 8 - 10 (3 bit)
RESI : ESI flag of last received FDCAN Message
bits : 11 - 11 (1 bit)
RBRS : BRS flag of last received FDCAN Message
bits : 12 - 12 (1 bit)
REDL : Received FDCAN Message
bits : 13 - 13 (1 bit)
PXE : Protocol Exception Event
bits : 14 - 14 (1 bit)
TDCV : Transmitter Delay Compensation Value
bits : 16 - 22 (7 bit)
FDCAN Transmitter Delay Compensation Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TDCF : Transmitter Delay Compensation Filter Window Length
bits : 0 - 6 (7 bit)
TDCO : Transmitter Delay Compensation Offset
bits : 8 - 14 (7 bit)
FDCAN Interrupt Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RF0N : Rx FIFO 0 New Message
bits : 0 - 0 (1 bit)
RF0W : Rx FIFO 0 Full
bits : 1 - 1 (1 bit)
RF0F : Rx FIFO 0 Full
bits : 2 - 2 (1 bit)
RF0L : Rx FIFO 0 Message Lost
bits : 3 - 3 (1 bit)
RF1N : Rx FIFO 1 New Message
bits : 4 - 4 (1 bit)
RF1W : Rx FIFO 1 Watermark Reached
bits : 5 - 5 (1 bit)
RF1F : Rx FIFO 1 Watermark Reached
bits : 6 - 6 (1 bit)
RF1L : Rx FIFO 1 Message Lost
bits : 7 - 7 (1 bit)
HPM : High Priority Message
bits : 8 - 8 (1 bit)
TC : Transmission Completed
bits : 9 - 9 (1 bit)
TCF : Transmission Cancellation Finished
bits : 10 - 10 (1 bit)
TEF : Tx FIFO Empty
bits : 11 - 11 (1 bit)
TEFN : Tx Event FIFO New Entry
bits : 12 - 12 (1 bit)
TEFW : Tx Event FIFO Watermark Reached
bits : 13 - 13 (1 bit)
TEFF : Tx Event FIFO Full
bits : 14 - 14 (1 bit)
TEFL : Tx Event FIFO Element Lost
bits : 15 - 15 (1 bit)
TSW : Timestamp Wraparound
bits : 16 - 16 (1 bit)
MRAF : Message RAM Access Failure
bits : 17 - 17 (1 bit)
TOO : Timeout Occurred
bits : 18 - 18 (1 bit)
DRX : Message stored to Dedicated Rx Buffer
bits : 19 - 19 (1 bit)
ELO : Error Logging Overflow
bits : 22 - 22 (1 bit)
EP : Error Passive
bits : 23 - 23 (1 bit)
EW : Warning Status
bits : 24 - 24 (1 bit)
BO : Bus_Off Status
bits : 25 - 25 (1 bit)
WDI : Watchdog Interrupt
bits : 26 - 26 (1 bit)
PEA : Protocol Error in Arbitration Phase (Nominal Bit Time is used)
bits : 27 - 27 (1 bit)
PED : Protocol Error in Data Phase (Data Bit Time is used)
bits : 28 - 28 (1 bit)
ARA : Access to Reserved Address
bits : 29 - 29 (1 bit)
FDCAN Interrupt Enable Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RF0NE : Rx FIFO 0 New Message Enable
bits : 0 - 0 (1 bit)
RF0WE : Rx FIFO 0 Full Enable
bits : 1 - 1 (1 bit)
RF0FE : Rx FIFO 0 Full Enable
bits : 2 - 2 (1 bit)
RF0LE : Rx FIFO 0 Message Lost Enable
bits : 3 - 3 (1 bit)
RF1NE : Rx FIFO 1 New Message Enable
bits : 4 - 4 (1 bit)
RF1WE : Rx FIFO 1 Watermark Reached Enable
bits : 5 - 5 (1 bit)
RF1FE : Rx FIFO 1 Watermark Reached Enable
bits : 6 - 6 (1 bit)
RF1LE : Rx FIFO 1 Message Lost Enable
bits : 7 - 7 (1 bit)
HPME : High Priority Message Enable
bits : 8 - 8 (1 bit)
TCE : Transmission Completed Enable
bits : 9 - 9 (1 bit)
TCFE : Transmission Cancellation Finished Enable
bits : 10 - 10 (1 bit)
TEFE : Tx FIFO Empty Enable
bits : 11 - 11 (1 bit)
TEFNE : Tx Event FIFO New Entry Enable
bits : 12 - 12 (1 bit)
TEFWE : Tx Event FIFO Watermark Reached Enable
bits : 13 - 13 (1 bit)
TEFFE : Tx Event FIFO Full Enable
bits : 14 - 14 (1 bit)
TEFLE : Tx Event FIFO Element Lost Enable
bits : 15 - 15 (1 bit)
TSWE : Timestamp Wraparound Enable
bits : 16 - 16 (1 bit)
MRAFE : Message RAM Access Failure Enable
bits : 17 - 17 (1 bit)
TOOE : Timeout Occurred Enable
bits : 18 - 18 (1 bit)
DRXE : Message stored to Dedicated Rx Buffer Enable
bits : 19 - 19 (1 bit)
BECE : Bit Error Corrected Interrupt Enable
bits : 20 - 20 (1 bit)
BEUE : Bit Error Uncorrected Interrupt Enable
bits : 21 - 21 (1 bit)
ELOE : Error Logging Overflow Enable
bits : 22 - 22 (1 bit)
EPE : Error Passive Enable
bits : 23 - 23 (1 bit)
EWE : Warning Status Enable
bits : 24 - 24 (1 bit)
BOE : Bus_Off Status Enable
bits : 25 - 25 (1 bit)
WDIE : Watchdog Interrupt Enable
bits : 26 - 26 (1 bit)
PEAE : Protocol Error in Arbitration Phase Enable
bits : 27 - 27 (1 bit)
PEDE : Protocol Error in Data Phase Enable
bits : 28 - 28 (1 bit)
ARAE : Access to Reserved Address Enable
bits : 29 - 29 (1 bit)
FDCAN Interrupt Line Select Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RF0NL : Rx FIFO 0 New Message Interrupt Line
bits : 0 - 0 (1 bit)
RF0WL : Rx FIFO 0 Watermark Reached Interrupt Line
bits : 1 - 1 (1 bit)
RF0FL : Rx FIFO 0 Full Interrupt Line
bits : 2 - 2 (1 bit)
RF0LL : Rx FIFO 0 Message Lost Interrupt Line
bits : 3 - 3 (1 bit)
RF1NL : Rx FIFO 1 New Message Interrupt Line
bits : 4 - 4 (1 bit)
RF1WL : Rx FIFO 1 Watermark Reached Interrupt Line
bits : 5 - 5 (1 bit)
RF1FL : Rx FIFO 1 Full Interrupt Line
bits : 6 - 6 (1 bit)
RF1LL : Rx FIFO 1 Message Lost Interrupt Line
bits : 7 - 7 (1 bit)
HPML : High Priority Message Interrupt Line
bits : 8 - 8 (1 bit)
TCL : Transmission Completed Interrupt Line
bits : 9 - 9 (1 bit)
TCFL : Transmission Cancellation Finished Interrupt Line
bits : 10 - 10 (1 bit)
TEFL : Tx FIFO Empty Interrupt Line
bits : 11 - 11 (1 bit)
TEFNL : Tx Event FIFO New Entry Interrupt Line
bits : 12 - 12 (1 bit)
TEFWL : Tx Event FIFO Watermark Reached Interrupt Line
bits : 13 - 13 (1 bit)
TEFFL : Tx Event FIFO Full Interrupt Line
bits : 14 - 14 (1 bit)
TEFLL : Tx Event FIFO Element Lost Interrupt Line
bits : 15 - 15 (1 bit)
TSWL : Timestamp Wraparound Interrupt Line
bits : 16 - 16 (1 bit)
MRAFL : Message RAM Access Failure Interrupt Line
bits : 17 - 17 (1 bit)
TOOL : Timeout Occurred Interrupt Line
bits : 18 - 18 (1 bit)
DRXL : Message stored to Dedicated Rx Buffer Interrupt Line
bits : 19 - 19 (1 bit)
BECL : Bit Error Corrected Interrupt Line
bits : 20 - 20 (1 bit)
BEUL : Bit Error Uncorrected Interrupt Line
bits : 21 - 21 (1 bit)
ELOL : Error Logging Overflow Interrupt Line
bits : 22 - 22 (1 bit)
EPL : Error Passive Interrupt Line
bits : 23 - 23 (1 bit)
EWL : Warning Status Interrupt Line
bits : 24 - 24 (1 bit)
BOL : Bus_Off Status
bits : 25 - 25 (1 bit)
WDIL : Watchdog Interrupt Line
bits : 26 - 26 (1 bit)
PEAL : Protocol Error in Arbitration Phase Line
bits : 27 - 27 (1 bit)
PEDL : Protocol Error in Data Phase Line
bits : 28 - 28 (1 bit)
ARAL : Access to Reserved Address Line
bits : 29 - 29 (1 bit)
FDCAN Interrupt Line Enable Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EINT0 : Enable Interrupt Line 0
bits : 0 - 0 (1 bit)
EINT1 : Enable Interrupt Line 1
bits : 1 - 1 (1 bit)
FDCAN Global Filter Configuration Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RRFE : Reject Remote Frames Extended
bits : 0 - 0 (1 bit)
RRFS : Reject Remote Frames Standard
bits : 1 - 1 (1 bit)
ANFE : Accept Non-matching Frames Extended
bits : 2 - 3 (2 bit)
ANFS : Accept Non-matching Frames Standard
bits : 4 - 5 (2 bit)
FDCAN Standard ID Filter Configuration Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLSSA : Filter List Standard Start Address
bits : 2 - 15 (14 bit)
LSS : List Size Standard
bits : 16 - 23 (8 bit)
FDCAN Extended ID Filter Configuration Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLESA : Filter List Standard Start Address
bits : 2 - 15 (14 bit)
LSE : List Size Extended
bits : 16 - 23 (8 bit)
FDCAN Extended ID and Mask Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EIDM : Extended ID Mask
bits : 0 - 28 (29 bit)
FDCAN High Priority Message Status Register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BIDX : Buffer Index
bits : 0 - 5 (6 bit)
MSI : Message Storage Indicator
bits : 6 - 7 (2 bit)
FIDX : Filter Index
bits : 8 - 14 (7 bit)
FLST : Filter List
bits : 15 - 15 (1 bit)
FDCAN New Data 1 Register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ND0 : New data
bits : 0 - 0 (1 bit)
ND1 : New data
bits : 1 - 1 (1 bit)
ND2 : New data
bits : 2 - 2 (1 bit)
ND3 : New data
bits : 3 - 3 (1 bit)
ND4 : New data
bits : 4 - 4 (1 bit)
ND5 : New data
bits : 5 - 5 (1 bit)
ND6 : New data
bits : 6 - 6 (1 bit)
ND7 : New data
bits : 7 - 7 (1 bit)
ND8 : New data
bits : 8 - 8 (1 bit)
ND9 : New data
bits : 9 - 9 (1 bit)
ND10 : New data
bits : 10 - 10 (1 bit)
ND11 : New data
bits : 11 - 11 (1 bit)
ND12 : New data
bits : 12 - 12 (1 bit)
ND13 : New data
bits : 13 - 13 (1 bit)
ND14 : New data
bits : 14 - 14 (1 bit)
ND15 : New data
bits : 15 - 15 (1 bit)
ND16 : New data
bits : 16 - 16 (1 bit)
ND17 : New data
bits : 17 - 17 (1 bit)
ND18 : New data
bits : 18 - 18 (1 bit)
ND19 : New data
bits : 19 - 19 (1 bit)
ND20 : New data
bits : 20 - 20 (1 bit)
ND21 : New data
bits : 21 - 21 (1 bit)
ND22 : New data
bits : 22 - 22 (1 bit)
ND23 : New data
bits : 23 - 23 (1 bit)
ND24 : New data
bits : 24 - 24 (1 bit)
ND25 : New data
bits : 25 - 25 (1 bit)
ND26 : New data
bits : 26 - 26 (1 bit)
ND27 : New data
bits : 27 - 27 (1 bit)
ND28 : New data
bits : 28 - 28 (1 bit)
ND29 : New data
bits : 29 - 29 (1 bit)
ND30 : New data
bits : 30 - 30 (1 bit)
ND31 : New data
bits : 31 - 31 (1 bit)
FDCAN New Data 2 Register
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ND32 : New data
bits : 0 - 0 (1 bit)
ND33 : New data
bits : 1 - 1 (1 bit)
ND34 : New data
bits : 2 - 2 (1 bit)
ND35 : New data
bits : 3 - 3 (1 bit)
ND36 : New data
bits : 4 - 4 (1 bit)
ND37 : New data
bits : 5 - 5 (1 bit)
ND38 : New data
bits : 6 - 6 (1 bit)
ND39 : New data
bits : 7 - 7 (1 bit)
ND40 : New data
bits : 8 - 8 (1 bit)
ND41 : New data
bits : 9 - 9 (1 bit)
ND42 : New data
bits : 10 - 10 (1 bit)
ND43 : New data
bits : 11 - 11 (1 bit)
ND44 : New data
bits : 12 - 12 (1 bit)
ND45 : New data
bits : 13 - 13 (1 bit)
ND46 : New data
bits : 14 - 14 (1 bit)
ND47 : New data
bits : 15 - 15 (1 bit)
ND48 : New data
bits : 16 - 16 (1 bit)
ND49 : New data
bits : 17 - 17 (1 bit)
ND50 : New data
bits : 18 - 18 (1 bit)
ND51 : New data
bits : 19 - 19 (1 bit)
ND52 : New data
bits : 20 - 20 (1 bit)
ND53 : New data
bits : 21 - 21 (1 bit)
ND54 : New data
bits : 22 - 22 (1 bit)
ND55 : New data
bits : 23 - 23 (1 bit)
ND56 : New data
bits : 24 - 24 (1 bit)
ND57 : New data
bits : 25 - 25 (1 bit)
ND58 : New data
bits : 26 - 26 (1 bit)
ND59 : New data
bits : 27 - 27 (1 bit)
ND60 : New data
bits : 28 - 28 (1 bit)
ND61 : New data
bits : 29 - 29 (1 bit)
ND62 : New data
bits : 30 - 30 (1 bit)
ND63 : New data
bits : 31 - 31 (1 bit)
FDCAN Rx FIFO 0 Configuration Register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
F0SA : Rx FIFO 0 Start Address
bits : 2 - 15 (14 bit)
F0S : Rx FIFO 0 Size
bits : 16 - 23 (8 bit)
F0WM : FIFO 0 Watermark
bits : 24 - 31 (8 bit)
FDCAN Rx FIFO 0 Status Register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
F0FL : Rx FIFO 0 Fill Level
bits : 0 - 6 (7 bit)
F0G : Rx FIFO 0 Get Index
bits : 8 - 13 (6 bit)
F0P : Rx FIFO 0 Put Index
bits : 16 - 21 (6 bit)
F0F : Rx FIFO 0 Full
bits : 24 - 24 (1 bit)
RF0L : Rx FIFO 0 Message Lost
bits : 25 - 25 (1 bit)
CAN Rx FIFO 0 Acknowledge Register
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FA01 : Rx FIFO 0 Acknowledge Index
bits : 0 - 5 (6 bit)
FDCAN Rx Buffer Configuration Register
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RBSA : Rx Buffer Start Address
bits : 2 - 15 (14 bit)
FDCAN Rx FIFO 1 Configuration Register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
F1SA : Rx FIFO 1 Start Address
bits : 2 - 15 (14 bit)
F1S : Rx FIFO 1 Size
bits : 16 - 22 (7 bit)
F1WM : Rx FIFO 1 Watermark
bits : 24 - 30 (7 bit)
FDCAN Rx FIFO 1 Status Register
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
F1FL : Rx FIFO 1 Fill Level
bits : 0 - 6 (7 bit)
F1GI : Rx FIFO 1 Get Index
bits : 8 - 14 (7 bit)
F1PI : Rx FIFO 1 Put Index
bits : 16 - 22 (7 bit)
F1F : Rx FIFO 1 Full
bits : 24 - 24 (1 bit)
RF1L : Rx FIFO 1 Message Lost
bits : 25 - 25 (1 bit)
DMS : Debug Message Status
bits : 30 - 31 (2 bit)
FDCAN Rx FIFO 1 Acknowledge Register
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
F1AI : Rx FIFO 1 Acknowledge Index
bits : 0 - 5 (6 bit)
FDCAN Rx Buffer Element Size Configuration Register
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
F0DS : Rx FIFO 1 Data Field Size:
bits : 0 - 2 (3 bit)
F1DS : Rx FIFO 0 Data Field Size:
bits : 4 - 6 (3 bit)
RBDS : Rx Buffer Data Field Size:
bits : 8 - 10 (3 bit)
FDCAN Data Bit Timing and Prescaler Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DSJW : Synchronization Jump Width
bits : 0 - 3 (4 bit)
DTSEG2 : Data time segment after sample point
bits : 4 - 7 (4 bit)
DTSEG1 : Data time segment after sample point
bits : 8 - 12 (5 bit)
DBRP : Data BIt Rate Prescaler
bits : 16 - 20 (5 bit)
TDC : Transceiver Delay Compensation
bits : 23 - 23 (1 bit)
FDCAN Tx Buffer Configuration Register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TBSA : Tx Buffers Start Address
bits : 2 - 15 (14 bit)
NDTB : Number of Dedicated Transmit Buffers
bits : 16 - 21 (6 bit)
TFQS : Transmit FIFO/Queue Size
bits : 24 - 29 (6 bit)
TFQM : Tx FIFO/Queue Mode
bits : 30 - 30 (1 bit)
FDCAN Tx FIFO/Queue Status Register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TFFL : Tx FIFO Free Level
bits : 0 - 5 (6 bit)
TFGI : TFGI
bits : 8 - 12 (5 bit)
TFQPI : Tx FIFO/Queue Put Index
bits : 16 - 20 (5 bit)
TFQF : Tx FIFO/Queue Full
bits : 21 - 21 (1 bit)
FDCAN Tx Buffer Element Size Configuration Register
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TBDS : Tx Buffer Data Field Size:
bits : 0 - 2 (3 bit)
FDCAN Tx Buffer Request Pending Register
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TRP : Transmission Request Pending
bits : 0 - 31 (32 bit)
FDCAN Tx Buffer Add Request Register
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AR : Add Request
bits : 0 - 31 (32 bit)
FDCAN Tx Buffer Cancellation Request Register
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CR : Cancellation Request
bits : 0 - 31 (32 bit)
FDCAN Tx Buffer Transmission Occurred Register
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TO : Transmission Occurred.
bits : 0 - 31 (32 bit)
FDCAN Tx Buffer Cancellation Finished Register
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CF : Cancellation Finished
bits : 0 - 31 (32 bit)
FDCAN Tx Buffer Transmission Interrupt Enable Register
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIE : Transmission Interrupt Enable
bits : 0 - 31 (32 bit)
FDCAN Tx Buffer Cancellation Finished Interrupt Enable Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CF : Cancellation Finished Interrupt Enable
bits : 0 - 31 (32 bit)
FDCAN Tx Event FIFO Configuration Register
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EFSA : Event FIFO Start Address
bits : 2 - 15 (14 bit)
EFS : Event FIFO Size
bits : 16 - 21 (6 bit)
EFWM : Event FIFO Watermark
bits : 24 - 29 (6 bit)
FDCAN Tx Event FIFO Status Register
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EFFL : Event FIFO Fill Level
bits : 0 - 5 (6 bit)
EFGI : Event FIFO Get Index.
bits : 8 - 12 (5 bit)
EFF : Event FIFO Full.
bits : 24 - 24 (1 bit)
TEFL : Tx Event FIFO Element Lost.
bits : 25 - 25 (1 bit)
FDCAN Tx Event FIFO Acknowledge Register
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EFAI : Event FIFO Acknowledge Index
bits : 0 - 4 (5 bit)
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