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DLYB

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x100 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CR

CFGR


CR

DLYB control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DEN SEN

DEN : Delay block enable bit
bits : 0 - 0 (1 bit)

SEN : Sampler length enable bit
bits : 1 - 1 (1 bit)


CFGR

DLYB configuration register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFGR CFGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL UNIT LNG LNGF

SEL : Select the phase for the Output clock
bits : 0 - 3 (4 bit)

UNIT : Delay Defines the delay of a Unit delay cell
bits : 8 - 14 (7 bit)

LNG : Delay line length value
bits : 16 - 27 (12 bit)

LNGF : Length valid flag
bits : 31 - 31 (1 bit)



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