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AXI

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x100000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

AXI_PERIPH_ID_4 (PERIPH_ID_4)

AXI_PERIPH_ID_0 (PERIPH_ID_0)

AXI_PERIPH_ID_1 (PERIPH_ID_1)

AXI_PERIPH_ID_2 (PERIPH_ID_2)

AXI_PERIPH_ID_3 (PERIPH_ID_3)

AXI_COMP_ID_0 (COMP_ID_0)

AXI_COMP_ID_1 (COMP_ID_1)

AXI_COMP_ID_2 (COMP_ID_2)

AXI_COMP_ID_3 (COMP_ID_3)

AXI_TARG1_FN_MOD_ISS_BM (TARG1_FN_MOD_ISS_BM)

AXI_TARG1_FN_MOD2 (TARG1_FN_MOD2)

AXI_TARG1_FN_MOD_LB (TARG1_FN_MOD_LB)

AXI_TARG1_FN_MOD (TARG1_FN_MOD)

AXI_TARG2_FN_MOD_ISS_BM (TARG2_FN_MOD_ISS_BM)

AXI_TARG2_FN_MOD2 (TARG2_FN_MOD2)

AXI_TARG2_FN_MOD_LB (TARG2_FN_MOD_LB)

AXI_TARG2_FN_MOD (TARG2_FN_MOD)

AXI_TARG3_FN_MOD_ISS_BM (TARG3_FN_MOD_ISS_BM)

AXI_INI1_FN_MOD2 (INI1_FN_MOD2)

AXI_INI1_FN_MOD_AHB (INI1_FN_MOD_AHB)

AXI_INI1_READ_QOS (INI1_READ_QOS)

AXI_INI1_WRITE_QOS (INI1_WRITE_QOS)

AXI_INI1_FN_MOD (INI1_FN_MOD)

AXI_INI2_READ_QOS (INI2_READ_QOS)

AXI_INI2_WRITE_QOS (INI2_WRITE_QOS)

AXI_INI2_FN_MOD (INI2_FN_MOD)

AXI_INI3_FN_MOD2 (INI3_FN_MOD2)

AXI_INI3_FN_MOD_AHB (INI3_FN_MOD_AHB)

AXI_INI3_READ_QOS (INI3_READ_QOS)

AXI_INI3_WRITE_QOS (INI3_WRITE_QOS)

AXI_INI3_FN_MOD (INI3_FN_MOD)

AXI_INI4_READ_QOS (INI4_READ_QOS)

AXI_INI4_WRITE_QOS (INI4_WRITE_QOS)

AXI_INI4_FN_MOD (INI4_FN_MOD)

AXI_INI5_READ_QOS (INI5_READ_QOS)

AXI_INI5_WRITE_QOS (INI5_WRITE_QOS)

AXI_INI5_FN_MOD (INI5_FN_MOD)

AXI_INI6_READ_QOS (INI6_READ_QOS)

AXI_INI6_WRITE_QOS (INI6_WRITE_QOS)

AXI_INI6_FN_MOD (INI6_FN_MOD)

AXI_TARG4_FN_MOD_ISS_BM (TARG4_FN_MOD_ISS_BM)

AXI_TARG5_FN_MOD_ISS_BM (TARG5_FN_MOD_ISS_BM)

AXI_TARG6_FN_MOD_ISS_BM (TARG6_FN_MOD_ISS_BM)

AXI_TARG7_FN_MOD_ISS_BM (TARG7_FN_MOD_ISS_BM)

AXI_TARG7_FN_MOD2 (TARG7_FN_MOD2)

AXI_TARG7_FN_MOD (TARG7_FN_MOD)


AXI_PERIPH_ID_4 (PERIPH_ID_4)

AXI interconnect - peripheral ID4 register
address_offset : 0x1FD0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

AXI_PERIPH_ID_4 AXI_PERIPH_ID_4 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JEP106CON KCOUNT4

JEP106CON : JEP106 continuation code
bits : 0 - 3 (4 bit)

KCOUNT4 : Register file size
bits : 4 - 7 (4 bit)


AXI_PERIPH_ID_0 (PERIPH_ID_0)

AXI interconnect - peripheral ID0 register
address_offset : 0x1FE0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

AXI_PERIPH_ID_0 AXI_PERIPH_ID_0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PARTNUM

PARTNUM : Peripheral part number bits 0 to 7
bits : 0 - 7 (8 bit)


AXI_PERIPH_ID_1 (PERIPH_ID_1)

AXI interconnect - peripheral ID1 register
address_offset : 0x1FE4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

AXI_PERIPH_ID_1 AXI_PERIPH_ID_1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PARTNUM JEP106I

PARTNUM : Peripheral part number bits 8 to 11
bits : 0 - 3 (4 bit)

JEP106I : JEP106 identity bits 0 to 3
bits : 4 - 7 (4 bit)


AXI_PERIPH_ID_2 (PERIPH_ID_2)

AXI interconnect - peripheral ID2 register
address_offset : 0x1FE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

AXI_PERIPH_ID_2 AXI_PERIPH_ID_2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JEP106ID JEDEC REVISION

JEP106ID : JEP106 Identity bits 4 to 6
bits : 0 - 2 (3 bit)

JEDEC : JEP106 code flag
bits : 3 - 3 (1 bit)

REVISION : Peripheral revision number
bits : 4 - 7 (4 bit)


AXI_PERIPH_ID_3 (PERIPH_ID_3)

AXI interconnect - peripheral ID3 register
address_offset : 0x1FEC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

AXI_PERIPH_ID_3 AXI_PERIPH_ID_3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CUST_MOD_NUM REV_AND

CUST_MOD_NUM : Customer modification
bits : 0 - 3 (4 bit)

REV_AND : Customer version
bits : 4 - 7 (4 bit)


AXI_COMP_ID_0 (COMP_ID_0)

AXI interconnect - component ID0 register
address_offset : 0x1FF0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

AXI_COMP_ID_0 AXI_COMP_ID_0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PREAMBLE

PREAMBLE : Preamble bits 0 to 7
bits : 0 - 7 (8 bit)


AXI_COMP_ID_1 (COMP_ID_1)

AXI interconnect - component ID1 register
address_offset : 0x1FF4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

AXI_COMP_ID_1 AXI_COMP_ID_1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PREAMBLE CLASS

PREAMBLE : Preamble bits 8 to 11
bits : 0 - 3 (4 bit)

CLASS : Component class
bits : 4 - 7 (4 bit)


AXI_COMP_ID_2 (COMP_ID_2)

AXI interconnect - component ID2 register
address_offset : 0x1FF8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

AXI_COMP_ID_2 AXI_COMP_ID_2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PREAMBLE

PREAMBLE : Preamble bits 12 to 19
bits : 0 - 7 (8 bit)


AXI_COMP_ID_3 (COMP_ID_3)

AXI interconnect - component ID3 register
address_offset : 0x1FFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

AXI_COMP_ID_3 AXI_COMP_ID_3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PREAMBLE

PREAMBLE : Preamble bits 20 to 27
bits : 0 - 7 (8 bit)


AXI_TARG1_FN_MOD_ISS_BM (TARG1_FN_MOD_ISS_BM)

AXI interconnect - TARG x bus matrix issuing functionality register
address_offset : 0x2008 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AXI_TARG1_FN_MOD_ISS_BM AXI_TARG1_FN_MOD_ISS_BM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 READ_ISS_OVERRIDE WRITE_ISS_OVERRIDE

READ_ISS_OVERRIDE : READ_ISS_OVERRIDE
bits : 0 - 0 (1 bit)

WRITE_ISS_OVERRIDE : Switch matrix write issuing override for target
bits : 1 - 1 (1 bit)


AXI_TARG1_FN_MOD2 (TARG1_FN_MOD2)

AXI interconnect - TARG x bus matrix functionality 2 register
address_offset : 0x2024 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AXI_TARG1_FN_MOD2 AXI_TARG1_FN_MOD2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BYPASS_MERGE

BYPASS_MERGE : Disable packing of beats to match the output data width
bits : 0 - 0 (1 bit)


AXI_TARG1_FN_MOD_LB (TARG1_FN_MOD_LB)

AXI interconnect - TARG x long burst functionality modification
address_offset : 0x202C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AXI_TARG1_FN_MOD_LB AXI_TARG1_FN_MOD_LB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FN_MOD_LB

FN_MOD_LB : Controls burst breaking of long bursts
bits : 0 - 0 (1 bit)


AXI_TARG1_FN_MOD (TARG1_FN_MOD)

AXI interconnect - TARG x long burst functionality modification
address_offset : 0x2108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AXI_TARG1_FN_MOD AXI_TARG1_FN_MOD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 READ_ISS_OVERRIDE WRITE_ISS_OVERRIDE

READ_ISS_OVERRIDE : Override AMIB read issuing capability
bits : 0 - 0 (1 bit)

WRITE_ISS_OVERRIDE : Override AMIB write issuing capability
bits : 1 - 1 (1 bit)


AXI_TARG2_FN_MOD_ISS_BM (TARG2_FN_MOD_ISS_BM)

AXI interconnect - TARG x bus matrix issuing functionality register
address_offset : 0x3008 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AXI_TARG2_FN_MOD_ISS_BM AXI_TARG2_FN_MOD_ISS_BM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 READ_ISS_OVERRIDE WRITE_ISS_OVERRIDE

READ_ISS_OVERRIDE : READ_ISS_OVERRIDE
bits : 0 - 0 (1 bit)

WRITE_ISS_OVERRIDE : Switch matrix write issuing override for target
bits : 1 - 1 (1 bit)


AXI_TARG2_FN_MOD2 (TARG2_FN_MOD2)

AXI interconnect - TARG x bus matrix functionality 2 register
address_offset : 0x3024 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AXI_TARG2_FN_MOD2 AXI_TARG2_FN_MOD2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BYPASS_MERGE

BYPASS_MERGE : Disable packing of beats to match the output data width
bits : 0 - 0 (1 bit)


AXI_TARG2_FN_MOD_LB (TARG2_FN_MOD_LB)

AXI interconnect - TARG x long burst functionality modification
address_offset : 0x302C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AXI_TARG2_FN_MOD_LB AXI_TARG2_FN_MOD_LB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FN_MOD_LB

FN_MOD_LB : Controls burst breaking of long bursts
bits : 0 - 0 (1 bit)


AXI_TARG2_FN_MOD (TARG2_FN_MOD)

AXI interconnect - TARG x long burst functionality modification
address_offset : 0x3108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AXI_TARG2_FN_MOD AXI_TARG2_FN_MOD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 READ_ISS_OVERRIDE WRITE_ISS_OVERRIDE

READ_ISS_OVERRIDE : Override AMIB read issuing capability
bits : 0 - 0 (1 bit)

WRITE_ISS_OVERRIDE : Override AMIB write issuing capability
bits : 1 - 1 (1 bit)


AXI_TARG3_FN_MOD_ISS_BM (TARG3_FN_MOD_ISS_BM)

AXI interconnect - TARG x bus matrix issuing functionality register
address_offset : 0x4008 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AXI_TARG3_FN_MOD_ISS_BM AXI_TARG3_FN_MOD_ISS_BM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 READ_ISS_OVERRIDE WRITE_ISS_OVERRIDE

READ_ISS_OVERRIDE : READ_ISS_OVERRIDE
bits : 0 - 0 (1 bit)

WRITE_ISS_OVERRIDE : Switch matrix write issuing override for target
bits : 1 - 1 (1 bit)


AXI_INI1_FN_MOD2 (INI1_FN_MOD2)

AXI interconnect - INI x functionality modification 2 register
address_offset : 0x42024 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AXI_INI1_FN_MOD2 AXI_INI1_FN_MOD2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BYPASS_MERGE

BYPASS_MERGE : Disables alteration of transactions by the up-sizer unless required by the protocol
bits : 0 - 0 (1 bit)


AXI_INI1_FN_MOD_AHB (INI1_FN_MOD_AHB)

AXI interconnect - INI x AHB functionality modification register
address_offset : 0x42028 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AXI_INI1_FN_MOD_AHB AXI_INI1_FN_MOD_AHB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RD_INC_OVERRIDE WR_INC_OVERRIDE

RD_INC_OVERRIDE : Converts all AHB-Lite write transactions to a series of single beat AXI
bits : 0 - 0 (1 bit)

WR_INC_OVERRIDE : Converts all AHB-Lite read transactions to a series of single beat AXI
bits : 1 - 1 (1 bit)


AXI_INI1_READ_QOS (INI1_READ_QOS)

AXI interconnect - INI x read QoS register
address_offset : 0x42100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AXI_INI1_READ_QOS AXI_INI1_READ_QOS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AR_QOS

AR_QOS : Read channel QoS setting
bits : 0 - 3 (4 bit)


AXI_INI1_WRITE_QOS (INI1_WRITE_QOS)

AXI interconnect - INI x write QoS register
address_offset : 0x42104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AXI_INI1_WRITE_QOS AXI_INI1_WRITE_QOS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AW_QOS

AW_QOS : Write channel QoS setting
bits : 0 - 3 (4 bit)


AXI_INI1_FN_MOD (INI1_FN_MOD)

AXI interconnect - INI x issuing functionality modification register
address_offset : 0x42108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AXI_INI1_FN_MOD AXI_INI1_FN_MOD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 READ_ISS_OVERRIDE WRITE_ISS_OVERRIDE

READ_ISS_OVERRIDE : Override ASIB read issuing capability
bits : 0 - 0 (1 bit)

WRITE_ISS_OVERRIDE : Override ASIB write issuing capability
bits : 1 - 1 (1 bit)


AXI_INI2_READ_QOS (INI2_READ_QOS)

AXI interconnect - INI x read QoS register
address_offset : 0x43100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AXI_INI2_READ_QOS AXI_INI2_READ_QOS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AR_QOS

AR_QOS : Read channel QoS setting
bits : 0 - 3 (4 bit)


AXI_INI2_WRITE_QOS (INI2_WRITE_QOS)

AXI interconnect - INI x write QoS register
address_offset : 0x43104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AXI_INI2_WRITE_QOS AXI_INI2_WRITE_QOS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AW_QOS

AW_QOS : Write channel QoS setting
bits : 0 - 3 (4 bit)


AXI_INI2_FN_MOD (INI2_FN_MOD)

AXI interconnect - INI x issuing functionality modification register
address_offset : 0x43108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AXI_INI2_FN_MOD AXI_INI2_FN_MOD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 READ_ISS_OVERRIDE WRITE_ISS_OVERRIDE

READ_ISS_OVERRIDE : Override ASIB read issuing capability
bits : 0 - 0 (1 bit)

WRITE_ISS_OVERRIDE : Override ASIB write issuing capability
bits : 1 - 1 (1 bit)


AXI_INI3_FN_MOD2 (INI3_FN_MOD2)

AXI interconnect - INI x functionality modification 2 register
address_offset : 0x44024 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AXI_INI3_FN_MOD2 AXI_INI3_FN_MOD2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BYPASS_MERGE

BYPASS_MERGE : Disables alteration of transactions by the up-sizer unless required by the protocol
bits : 0 - 0 (1 bit)


AXI_INI3_FN_MOD_AHB (INI3_FN_MOD_AHB)

AXI interconnect - INI x AHB functionality modification register
address_offset : 0x44028 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AXI_INI3_FN_MOD_AHB AXI_INI3_FN_MOD_AHB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RD_INC_OVERRIDE WR_INC_OVERRIDE

RD_INC_OVERRIDE : Converts all AHB-Lite write transactions to a series of single beat AXI
bits : 0 - 0 (1 bit)

WR_INC_OVERRIDE : Converts all AHB-Lite read transactions to a series of single beat AXI
bits : 1 - 1 (1 bit)


AXI_INI3_READ_QOS (INI3_READ_QOS)

AXI interconnect - INI x read QoS register
address_offset : 0x44100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AXI_INI3_READ_QOS AXI_INI3_READ_QOS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AR_QOS

AR_QOS : Read channel QoS setting
bits : 0 - 3 (4 bit)


AXI_INI3_WRITE_QOS (INI3_WRITE_QOS)

AXI interconnect - INI x write QoS register
address_offset : 0x44104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AXI_INI3_WRITE_QOS AXI_INI3_WRITE_QOS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AW_QOS

AW_QOS : Write channel QoS setting
bits : 0 - 3 (4 bit)


AXI_INI3_FN_MOD (INI3_FN_MOD)

AXI interconnect - INI x issuing functionality modification register
address_offset : 0x44108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AXI_INI3_FN_MOD AXI_INI3_FN_MOD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 READ_ISS_OVERRIDE WRITE_ISS_OVERRIDE

READ_ISS_OVERRIDE : Override ASIB read issuing capability
bits : 0 - 0 (1 bit)

WRITE_ISS_OVERRIDE : Override ASIB write issuing capability
bits : 1 - 1 (1 bit)


AXI_INI4_READ_QOS (INI4_READ_QOS)

AXI interconnect - INI x read QoS register
address_offset : 0x45100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AXI_INI4_READ_QOS AXI_INI4_READ_QOS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AR_QOS

AR_QOS : Read channel QoS setting
bits : 0 - 3 (4 bit)


AXI_INI4_WRITE_QOS (INI4_WRITE_QOS)

AXI interconnect - INI x write QoS register
address_offset : 0x45104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AXI_INI4_WRITE_QOS AXI_INI4_WRITE_QOS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AW_QOS

AW_QOS : Write channel QoS setting
bits : 0 - 3 (4 bit)


AXI_INI4_FN_MOD (INI4_FN_MOD)

AXI interconnect - INI x issuing functionality modification register
address_offset : 0x45108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AXI_INI4_FN_MOD AXI_INI4_FN_MOD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 READ_ISS_OVERRIDE WRITE_ISS_OVERRIDE

READ_ISS_OVERRIDE : Override ASIB read issuing capability
bits : 0 - 0 (1 bit)

WRITE_ISS_OVERRIDE : Override ASIB write issuing capability
bits : 1 - 1 (1 bit)


AXI_INI5_READ_QOS (INI5_READ_QOS)

AXI interconnect - INI x read QoS register
address_offset : 0x46100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AXI_INI5_READ_QOS AXI_INI5_READ_QOS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AR_QOS

AR_QOS : Read channel QoS setting
bits : 0 - 3 (4 bit)


AXI_INI5_WRITE_QOS (INI5_WRITE_QOS)

AXI interconnect - INI x write QoS register
address_offset : 0x46104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AXI_INI5_WRITE_QOS AXI_INI5_WRITE_QOS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AW_QOS

AW_QOS : Write channel QoS setting
bits : 0 - 3 (4 bit)


AXI_INI5_FN_MOD (INI5_FN_MOD)

AXI interconnect - INI x issuing functionality modification register
address_offset : 0x46108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AXI_INI5_FN_MOD AXI_INI5_FN_MOD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 READ_ISS_OVERRIDE WRITE_ISS_OVERRIDE

READ_ISS_OVERRIDE : Override ASIB read issuing capability
bits : 0 - 0 (1 bit)

WRITE_ISS_OVERRIDE : Override ASIB write issuing capability
bits : 1 - 1 (1 bit)


AXI_INI6_READ_QOS (INI6_READ_QOS)

AXI interconnect - INI x read QoS register
address_offset : 0x47100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AXI_INI6_READ_QOS AXI_INI6_READ_QOS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AR_QOS

AR_QOS : Read channel QoS setting
bits : 0 - 3 (4 bit)


AXI_INI6_WRITE_QOS (INI6_WRITE_QOS)

AXI interconnect - INI x write QoS register
address_offset : 0x47104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AXI_INI6_WRITE_QOS AXI_INI6_WRITE_QOS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AW_QOS

AW_QOS : Write channel QoS setting
bits : 0 - 3 (4 bit)


AXI_INI6_FN_MOD (INI6_FN_MOD)

AXI interconnect - INI x issuing functionality modification register
address_offset : 0x47108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AXI_INI6_FN_MOD AXI_INI6_FN_MOD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 READ_ISS_OVERRIDE WRITE_ISS_OVERRIDE

READ_ISS_OVERRIDE : Override ASIB read issuing capability
bits : 0 - 0 (1 bit)

WRITE_ISS_OVERRIDE : Override ASIB write issuing capability
bits : 1 - 1 (1 bit)


AXI_TARG4_FN_MOD_ISS_BM (TARG4_FN_MOD_ISS_BM)

AXI interconnect - TARG x bus matrix issuing functionality register
address_offset : 0x5008 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AXI_TARG4_FN_MOD_ISS_BM AXI_TARG4_FN_MOD_ISS_BM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 READ_ISS_OVERRIDE WRITE_ISS_OVERRIDE

READ_ISS_OVERRIDE : READ_ISS_OVERRIDE
bits : 0 - 0 (1 bit)

WRITE_ISS_OVERRIDE : Switch matrix write issuing override for target
bits : 1 - 1 (1 bit)


AXI_TARG5_FN_MOD_ISS_BM (TARG5_FN_MOD_ISS_BM)

AXI interconnect - TARG x bus matrix issuing functionality register
address_offset : 0x6008 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AXI_TARG5_FN_MOD_ISS_BM AXI_TARG5_FN_MOD_ISS_BM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 READ_ISS_OVERRIDE WRITE_ISS_OVERRIDE

READ_ISS_OVERRIDE : READ_ISS_OVERRIDE
bits : 0 - 0 (1 bit)

WRITE_ISS_OVERRIDE : Switch matrix write issuing override for target
bits : 1 - 1 (1 bit)


AXI_TARG6_FN_MOD_ISS_BM (TARG6_FN_MOD_ISS_BM)

AXI interconnect - TARG x bus matrix issuing functionality register
address_offset : 0x7008 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AXI_TARG6_FN_MOD_ISS_BM AXI_TARG6_FN_MOD_ISS_BM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 READ_ISS_OVERRIDE WRITE_ISS_OVERRIDE

READ_ISS_OVERRIDE : READ_ISS_OVERRIDE
bits : 0 - 0 (1 bit)

WRITE_ISS_OVERRIDE : Switch matrix write issuing override for target
bits : 1 - 1 (1 bit)


AXI_TARG7_FN_MOD_ISS_BM (TARG7_FN_MOD_ISS_BM)

AXI interconnect - TARG x bus matrix issuing functionality register
address_offset : 0x800C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AXI_TARG7_FN_MOD_ISS_BM AXI_TARG7_FN_MOD_ISS_BM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 READ_ISS_OVERRIDE WRITE_ISS_OVERRIDE

READ_ISS_OVERRIDE : READ_ISS_OVERRIDE
bits : 0 - 0 (1 bit)

WRITE_ISS_OVERRIDE : Switch matrix write issuing override for target
bits : 1 - 1 (1 bit)


AXI_TARG7_FN_MOD2 (TARG7_FN_MOD2)

AXI interconnect - TARG x bus matrix functionality 2 register
address_offset : 0x8024 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AXI_TARG7_FN_MOD2 AXI_TARG7_FN_MOD2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BYPASS_MERGE

BYPASS_MERGE : Disable packing of beats to match the output data width
bits : 0 - 0 (1 bit)


AXI_TARG7_FN_MOD (TARG7_FN_MOD)

AXI interconnect - TARG x long burst functionality modification
address_offset : 0x8108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AXI_TARG7_FN_MOD AXI_TARG7_FN_MOD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 READ_ISS_OVERRIDE WRITE_ISS_OVERRIDE

READ_ISS_OVERRIDE : Override AMIB read issuing capability
bits : 0 - 0 (1 bit)

WRITE_ISS_OVERRIDE : Override AMIB write issuing capability
bits : 1 - 1 (1 bit)



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