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DFSDM

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

DFSDM_CHCFG0R1 (CHCFG0R1)

DFSDM_CHCFG4R1 (CHCFG4R1)

DFSDM0_JDATAR

DFSDM1_JDATAR

DFSDM2_JDATAR

DFSDM3_JDATAR

DFSDM0_RDATAR

DFSDM1_RDATAR

DFSDM2_RDATAR

DFSDM3_RDATAR

DFSDM0_AWHTR

DFSDM1_AWHTR

DFSDM2_AWHTR

DFSDM3_AWHTR

DFSDM0_AWLTR

DFSDM1_AWLTR

DFSDM2_AWLTR

DFSDM3_AWLTR

DFSDM_CHCFG5R1 (CHCFG5R1)

DFSDM0_AWSR

DFSDM1_AWSR

DFSDM2_AWSR

DFSDM3_AWSR

DFSDM0_AWCFR

DFSDM1_AWCFR

DFSDM2_AWCFR

DFSDM3_AWCFR

DFSDM0_EXMAX

DFSDM1_EXMAX

DFSDM2_EXMAX

DFSDM3_EXMAX

DFSDM0_EXMIN

DFSDM1_EXMIN

DFSDM2_EXMIN

DFSDM3_EXMIN

DFSDM_CHCFG6R1 (CHCFG6R1)

DFSDM0_CNVTIMR

DFSDM1_CNVTIMR

DFSDM2_CNVTIMR

DFSDM3_CNVTIMR

DFSDM_CHCFG7R1 (CHCFG7R1)

DFSDM_CHCFG0R2 (CHCFG0R2)

DFSDM_CHCFG1R2 (CHCFG1R2)

DFSDM_CHCFG2R2 (CHCFG2R2)

DFSDM_CHCFG3R2 (CHCFG3R2)

DFSDM_CHCFG4R2 (CHCFG4R2)

DFSDM_CHCFG5R2 (CHCFG5R2)

DFSDM_CHCFG6R2 (CHCFG6R2)

DFSDM_CHCFG7R2 (CHCFG7R2)

DFSDM_CHCFG1R1 (CHCFG1R1)

DFSDM_AWSCD0R (AWSCD0R)

DFSDM_AWSCD1R (AWSCD1R)

DFSDM_AWSCD2R (AWSCD2R)

DFSDM_AWSCD3R (AWSCD3R)

DFSDM_AWSCD4R (AWSCD4R)

DFSDM_AWSCD5R (AWSCD5R)

DFSDM_AWSCD6R (AWSCD6R)

DFSDM_AWSCD7R (AWSCD7R)

DFSDM_CHWDAT0R (CHWDAT0R)

DFSDM_CHWDAT1R (CHWDAT1R)

DFSDM_CHWDAT2R (CHWDAT2R)

DFSDM_CHWDAT3R (CHWDAT3R)

DFSDM_CHWDAT4R (CHWDAT4R)

DFSDM_CHWDAT5R (CHWDAT5R)

DFSDM_CHWDAT6R (CHWDAT6R)

DFSDM_CHWDAT7R (CHWDAT7R)

DFSDM_CHCFG2R1 (CHCFG2R1)

DFSDM_CHDATIN0R (CHDATIN0R)

DFSDM_CHDATIN1R (CHDATIN1R)

DFSDM_CHDATIN2R (CHDATIN2R)

DFSDM_CHDATIN3R (CHDATIN3R)

DFSDM_CHDATIN4R (CHDATIN4R)

DFSDM_CHDATIN5R (CHDATIN5R)

DFSDM_CHDATIN6R (CHDATIN6R)

DFSDM_CHDATIN7R (CHDATIN7R)

DFSDM0_CR1

DFSDM1_CR1

DFSDM2_CR1

DFSDM3_CR1

DFSDM0_CR2

DFSDM1_CR2

DFSDM2_CR2

DFSDM3_CR2

DFSDM_CHCFG3R1 (CHCFG3R1)

DFSDM0_ISR

DFSDM1_ISR

DFSDM2_ISR

DFSDM3_ISR

DFSDM0_ICR

DFSDM1_ICR

DFSDM2_ICR

DFSDM3_ICR

DFSDM0_JCHGR

DFSDM1_JCHGR

DFSDM2_JCHGR

DFSDM3_JCHGR

DFSDM0_FCR

DFSDM1_FCR

DFSDM2_FCR

DFSDM3_FCR


DFSDM_CHCFG0R1 (CHCFG0R1)

DFSDM channel configuration 0 register 1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CHCFG0R1 DFSDM_CHCFG0R1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SITP SPICKSEL SCDEN CKABEN CHEN CHINSEL DATMPX DATPACK CKOUTDIV CKOUTSRC DFSDMEN

SITP : Serial interface type for channel 0
bits : 0 - 1 (2 bit)

SPICKSEL : SPI clock select for channel 0
bits : 2 - 3 (2 bit)

SCDEN : Short-circuit detector enable on channel 0
bits : 5 - 5 (1 bit)

CKABEN : Clock absence detector enable on channel 0
bits : 6 - 6 (1 bit)

CHEN : Channel 0 enable
bits : 7 - 7 (1 bit)

CHINSEL : Channel inputs selection
bits : 8 - 8 (1 bit)

DATMPX : Input data multiplexer for channel 0
bits : 12 - 13 (2 bit)

DATPACK : Data packing mode in DFSDM_CHDATINyR register
bits : 14 - 15 (2 bit)

CKOUTDIV : Output serial clock divider
bits : 16 - 23 (8 bit)

CKOUTSRC : Output serial clock source selection
bits : 30 - 30 (1 bit)

DFSDMEN : Global enable for DFSDM interface
bits : 31 - 31 (1 bit)


DFSDM_CHCFG4R1 (CHCFG4R1)

DFSDM channel configuration 4 register 1
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CHCFG4R1 DFSDM_CHCFG4R1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SITP SPICKSEL SCDEN CKABEN CHEN CHINSEL DATMPX DATPACK CKOUTDIV CKOUTSRC DFSDMEN

SITP : Serial interface type for channel 4
bits : 0 - 1 (2 bit)

SPICKSEL : SPI clock select for channel 4
bits : 2 - 3 (2 bit)

SCDEN : Short-circuit detector enable on channel 4
bits : 5 - 5 (1 bit)

CKABEN : Clock absence detector enable on channel 4
bits : 6 - 6 (1 bit)

CHEN : Channel 4 enable
bits : 7 - 7 (1 bit)

CHINSEL : Channel inputs selection
bits : 8 - 8 (1 bit)

DATMPX : Input data multiplexer for channel 4
bits : 12 - 13 (2 bit)

DATPACK : Data packing mode in DFSDM_CHDATINyR register
bits : 14 - 15 (2 bit)

CKOUTDIV : Output serial clock divider
bits : 16 - 23 (8 bit)

CKOUTSRC : Output serial clock source selection
bits : 30 - 30 (1 bit)

DFSDMEN : Global enable for DFSDM interface
bits : 31 - 31 (1 bit)


DFSDM0_JDATAR

DFSDM data register for injected group
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM0_JDATAR DFSDM0_JDATAR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JDATACH JDATA

JDATACH : Injected channel most recently converted
bits : 0 - 2 (3 bit)

JDATA : Injected group conversion data
bits : 8 - 31 (24 bit)


DFSDM1_JDATAR

DFSDM data register for injected group
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM1_JDATAR DFSDM1_JDATAR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JDATACH JDATA

JDATACH : Injected channel most recently converted
bits : 0 - 2 (3 bit)

JDATA : Injected group conversion data
bits : 8 - 31 (24 bit)


DFSDM2_JDATAR

DFSDM data register for injected group
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM2_JDATAR DFSDM2_JDATAR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JDATACH JDATA

JDATACH : Injected channel most recently converted
bits : 0 - 2 (3 bit)

JDATA : Injected group conversion data
bits : 8 - 31 (24 bit)


DFSDM3_JDATAR

DFSDM data register for injected group
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM3_JDATAR DFSDM3_JDATAR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JDATACH JDATA

JDATACH : Injected channel most recently converted
bits : 0 - 2 (3 bit)

JDATA : Injected group conversion data
bits : 8 - 31 (24 bit)


DFSDM0_RDATAR

DFSDM data register for the regular channel
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM0_RDATAR DFSDM0_RDATAR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDATACH RPEND RDATA

RDATACH : Regular channel most recently converted
bits : 0 - 2 (3 bit)

RPEND : Regular channel pending data
bits : 4 - 4 (1 bit)

RDATA : Regular channel conversion data
bits : 8 - 31 (24 bit)


DFSDM1_RDATAR

DFSDM data register for the regular channel
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM1_RDATAR DFSDM1_RDATAR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDATACH RPEND RDATA

RDATACH : Regular channel most recently converted
bits : 0 - 2 (3 bit)

RPEND : Regular channel pending data
bits : 4 - 4 (1 bit)

RDATA : Regular channel conversion data
bits : 8 - 31 (24 bit)


DFSDM2_RDATAR

DFSDM data register for the regular channel
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM2_RDATAR DFSDM2_RDATAR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDATACH RPEND RDATA

RDATACH : Regular channel most recently converted
bits : 0 - 2 (3 bit)

RPEND : Regular channel pending data
bits : 4 - 4 (1 bit)

RDATA : Regular channel conversion data
bits : 8 - 31 (24 bit)


DFSDM3_RDATAR

DFSDM data register for the regular channel
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM3_RDATAR DFSDM3_RDATAR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDATACH RPEND RDATA

RDATACH : Regular channel most recently converted
bits : 0 - 2 (3 bit)

RPEND : Regular channel pending data
bits : 4 - 4 (1 bit)

RDATA : Regular channel conversion data
bits : 8 - 31 (24 bit)


DFSDM0_AWHTR

DFSDM analog watchdog high threshold register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM0_AWHTR DFSDM0_AWHTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BKAWH AWHT

BKAWH : Break signal assignment to analog watchdog high threshold event
bits : 0 - 3 (4 bit)

AWHT : Analog watchdog high threshold
bits : 8 - 31 (24 bit)


DFSDM1_AWHTR

DFSDM analog watchdog high threshold register
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM1_AWHTR DFSDM1_AWHTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BKAWH AWHT

BKAWH : Break signal assignment to analog watchdog high threshold event
bits : 0 - 3 (4 bit)

AWHT : Analog watchdog high threshold
bits : 8 - 31 (24 bit)


DFSDM2_AWHTR

DFSDM analog watchdog high threshold register
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM2_AWHTR DFSDM2_AWHTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BKAWH AWHT

BKAWH : Break signal assignment to analog watchdog high threshold event
bits : 0 - 3 (4 bit)

AWHT : Analog watchdog high threshold
bits : 8 - 31 (24 bit)


DFSDM3_AWHTR

DFSDM analog watchdog high threshold register
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM3_AWHTR DFSDM3_AWHTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BKAWH AWHT

BKAWH : Break signal assignment to analog watchdog high threshold event
bits : 0 - 3 (4 bit)

AWHT : Analog watchdog high threshold
bits : 8 - 31 (24 bit)


DFSDM0_AWLTR

DFSDM analog watchdog low threshold register
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM0_AWLTR DFSDM0_AWLTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BKAWL AWLT

BKAWL : Break signal assignment to analog watchdog low threshold event
bits : 0 - 3 (4 bit)

AWLT : Analog watchdog low threshold
bits : 8 - 31 (24 bit)


DFSDM1_AWLTR

DFSDM analog watchdog low threshold register
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM1_AWLTR DFSDM1_AWLTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BKAWL AWLT

BKAWL : Break signal assignment to analog watchdog low threshold event
bits : 0 - 3 (4 bit)

AWLT : Analog watchdog low threshold
bits : 8 - 31 (24 bit)


DFSDM2_AWLTR

DFSDM analog watchdog low threshold register
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM2_AWLTR DFSDM2_AWLTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BKAWL AWLT

BKAWL : Break signal assignment to analog watchdog low threshold event
bits : 0 - 3 (4 bit)

AWLT : Analog watchdog low threshold
bits : 8 - 31 (24 bit)


DFSDM3_AWLTR

DFSDM analog watchdog low threshold register
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM3_AWLTR DFSDM3_AWLTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BKAWL AWLT

BKAWL : Break signal assignment to analog watchdog low threshold event
bits : 0 - 3 (4 bit)

AWLT : Analog watchdog low threshold
bits : 8 - 31 (24 bit)


DFSDM_CHCFG5R1 (CHCFG5R1)

DFSDM channel configuration 5 register 1
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CHCFG5R1 DFSDM_CHCFG5R1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SITP SPICKSEL SCDEN CKABEN CHEN CHINSEL DATMPX DATPACK CKOUTDIV CKOUTSRC DFSDMEN

SITP : Serial interface type for channel 5
bits : 0 - 1 (2 bit)

SPICKSEL : SPI clock select for channel 5
bits : 2 - 3 (2 bit)

SCDEN : Short-circuit detector enable on channel 5
bits : 5 - 5 (1 bit)

CKABEN : Clock absence detector enable on channel 5
bits : 6 - 6 (1 bit)

CHEN : Channel 5 enable
bits : 7 - 7 (1 bit)

CHINSEL : Channel inputs selection
bits : 8 - 8 (1 bit)

DATMPX : Input data multiplexer for channel 5
bits : 12 - 13 (2 bit)

DATPACK : Data packing mode in DFSDM_CHDATINyR register
bits : 14 - 15 (2 bit)

CKOUTDIV : Output serial clock divider
bits : 16 - 23 (8 bit)

CKOUTSRC : Output serial clock source selection
bits : 30 - 30 (1 bit)

DFSDMEN : Global enable for DFSDM interface
bits : 31 - 31 (1 bit)


DFSDM0_AWSR

DFSDM analog watchdog status register
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM0_AWSR DFSDM0_AWSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AWLTF AWHTF

AWLTF : Analog watchdog low threshold flag
bits : 0 - 7 (8 bit)

AWHTF : Analog watchdog high threshold flag
bits : 8 - 15 (8 bit)


DFSDM1_AWSR

DFSDM analog watchdog status register
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM1_AWSR DFSDM1_AWSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AWLTF AWHTF

AWLTF : Analog watchdog low threshold flag
bits : 0 - 7 (8 bit)

AWHTF : Analog watchdog high threshold flag
bits : 8 - 15 (8 bit)


DFSDM2_AWSR

DFSDM analog watchdog status register
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM2_AWSR DFSDM2_AWSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AWLTF AWHTF

AWLTF : Analog watchdog low threshold flag
bits : 0 - 7 (8 bit)

AWHTF : Analog watchdog high threshold flag
bits : 8 - 15 (8 bit)


DFSDM3_AWSR

DFSDM analog watchdog status register
address_offset : 0x14C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM3_AWSR DFSDM3_AWSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AWLTF AWHTF

AWLTF : Analog watchdog low threshold flag
bits : 0 - 7 (8 bit)

AWHTF : Analog watchdog high threshold flag
bits : 8 - 15 (8 bit)


DFSDM0_AWCFR

DFSDM analog watchdog clear flag register
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM0_AWCFR DFSDM0_AWCFR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRAWLTF CLRAWHTF

CLRAWLTF : Clear the analog watchdog low threshold flag
bits : 0 - 7 (8 bit)

CLRAWHTF : Clear the analog watchdog high threshold flag
bits : 8 - 15 (8 bit)


DFSDM1_AWCFR

DFSDM analog watchdog clear flag register
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM1_AWCFR DFSDM1_AWCFR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRAWLTF CLRAWHTF

CLRAWLTF : Clear the analog watchdog low threshold flag
bits : 0 - 7 (8 bit)

CLRAWHTF : Clear the analog watchdog high threshold flag
bits : 8 - 15 (8 bit)


DFSDM2_AWCFR

DFSDM analog watchdog clear flag register
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM2_AWCFR DFSDM2_AWCFR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRAWLTF CLRAWHTF

CLRAWLTF : Clear the analog watchdog low threshold flag
bits : 0 - 7 (8 bit)

CLRAWHTF : Clear the analog watchdog high threshold flag
bits : 8 - 15 (8 bit)


DFSDM3_AWCFR

DFSDM analog watchdog clear flag register
address_offset : 0x15C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM3_AWCFR DFSDM3_AWCFR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRAWLTF CLRAWHTF

CLRAWLTF : Clear the analog watchdog low threshold flag
bits : 0 - 7 (8 bit)

CLRAWHTF : Clear the analog watchdog high threshold flag
bits : 8 - 15 (8 bit)


DFSDM0_EXMAX

DFSDM Extremes detector maximum register
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM0_EXMAX DFSDM0_EXMAX read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXMAXCH EXMAX

EXMAXCH : Extremes detector maximum data channel
bits : 0 - 2 (3 bit)

EXMAX : Extremes detector maximum value
bits : 8 - 31 (24 bit)


DFSDM1_EXMAX

DFSDM Extremes detector maximum register
address_offset : 0x164 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM1_EXMAX DFSDM1_EXMAX read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXMAXCH EXMAX

EXMAXCH : Extremes detector maximum data channel
bits : 0 - 2 (3 bit)

EXMAX : Extremes detector maximum value
bits : 8 - 31 (24 bit)


DFSDM2_EXMAX

DFSDM Extremes detector maximum register
address_offset : 0x168 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM2_EXMAX DFSDM2_EXMAX read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXMAXCH EXMAX

EXMAXCH : Extremes detector maximum data channel
bits : 0 - 2 (3 bit)

EXMAX : Extremes detector maximum value
bits : 8 - 31 (24 bit)


DFSDM3_EXMAX

DFSDM Extremes detector maximum register
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM3_EXMAX DFSDM3_EXMAX read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXMAXCH EXMAX

EXMAXCH : Extremes detector maximum data channel
bits : 0 - 2 (3 bit)

EXMAX : Extremes detector maximum value
bits : 8 - 31 (24 bit)


DFSDM0_EXMIN

DFSDM Extremes detector minimum register
address_offset : 0x170 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM0_EXMIN DFSDM0_EXMIN read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXMINCH EXMIN

EXMINCH : Extremes detector minimum data channel
bits : 0 - 2 (3 bit)

EXMIN : Extremes detector minimum value
bits : 8 - 31 (24 bit)


DFSDM1_EXMIN

DFSDM Extremes detector minimum register
address_offset : 0x174 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM1_EXMIN DFSDM1_EXMIN read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXMINCH EXMIN

EXMINCH : Extremes detector minimum data channel
bits : 0 - 2 (3 bit)

EXMIN : Extremes detector minimum value
bits : 8 - 31 (24 bit)


DFSDM2_EXMIN

DFSDM Extremes detector minimum register
address_offset : 0x178 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM2_EXMIN DFSDM2_EXMIN read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXMINCH EXMIN

EXMINCH : Extremes detector minimum data channel
bits : 0 - 2 (3 bit)

EXMIN : Extremes detector minimum value
bits : 8 - 31 (24 bit)


DFSDM3_EXMIN

DFSDM Extremes detector minimum register
address_offset : 0x17C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM3_EXMIN DFSDM3_EXMIN read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXMINCH EXMIN

EXMINCH : Extremes detector minimum data channel
bits : 0 - 2 (3 bit)

EXMIN : Extremes detector minimum value
bits : 8 - 31 (24 bit)


DFSDM_CHCFG6R1 (CHCFG6R1)

DFSDM channel configuration 6 register 1
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CHCFG6R1 DFSDM_CHCFG6R1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SITP SPICKSEL SCDEN CKABEN CHEN CHINSEL DATMPX DATPACK CKOUTDIV CKOUTSRC DFSDMEN

SITP : Serial interface type for channel 6
bits : 0 - 1 (2 bit)

SPICKSEL : SPI clock select for channel 6
bits : 2 - 3 (2 bit)

SCDEN : Short-circuit detector enable on channel 6
bits : 5 - 5 (1 bit)

CKABEN : Clock absence detector enable on channel 6
bits : 6 - 6 (1 bit)

CHEN : Channel 6 enable
bits : 7 - 7 (1 bit)

CHINSEL : Channel inputs selection
bits : 8 - 8 (1 bit)

DATMPX : Input data multiplexer for channel 6
bits : 12 - 13 (2 bit)

DATPACK : Data packing mode in DFSDM_CHDATINyR register
bits : 14 - 15 (2 bit)

CKOUTDIV : Output serial clock divider
bits : 16 - 23 (8 bit)

CKOUTSRC : Output serial clock source selection
bits : 30 - 30 (1 bit)

DFSDMEN : Global enable for DFSDM interface
bits : 31 - 31 (1 bit)


DFSDM0_CNVTIMR

DFSDM conversion timer register
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM0_CNVTIMR DFSDM0_CNVTIMR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNVCNT

CNVCNT : 28-bit timer counting conversion time
bits : 4 - 31 (28 bit)


DFSDM1_CNVTIMR

DFSDM conversion timer register
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM1_CNVTIMR DFSDM1_CNVTIMR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNVCNT

CNVCNT : 28-bit timer counting conversion time
bits : 4 - 31 (28 bit)


DFSDM2_CNVTIMR

DFSDM conversion timer register
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM2_CNVTIMR DFSDM2_CNVTIMR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNVCNT

CNVCNT : 28-bit timer counting conversion time
bits : 4 - 31 (28 bit)


DFSDM3_CNVTIMR

DFSDM conversion timer register
address_offset : 0x18C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM3_CNVTIMR DFSDM3_CNVTIMR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNVCNT

CNVCNT : 28-bit timer counting conversion time
bits : 4 - 31 (28 bit)


DFSDM_CHCFG7R1 (CHCFG7R1)

DFSDM channel configuration 7 register 1
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CHCFG7R1 DFSDM_CHCFG7R1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SITP SPICKSEL SCDEN CKABEN CHEN CHINSEL DATMPX DATPACK CKOUTDIV CKOUTSRC DFSDMEN

SITP : Serial interface type for channel 7
bits : 0 - 1 (2 bit)

SPICKSEL : SPI clock select for channel 7
bits : 2 - 3 (2 bit)

SCDEN : Short-circuit detector enable on channel 7
bits : 5 - 5 (1 bit)

CKABEN : Clock absence detector enable on channel 7
bits : 6 - 6 (1 bit)

CHEN : Channel 7 enable
bits : 7 - 7 (1 bit)

CHINSEL : Channel inputs selection
bits : 8 - 8 (1 bit)

DATMPX : Input data multiplexer for channel 7
bits : 12 - 13 (2 bit)

DATPACK : Data packing mode in DFSDM_CHDATINyR register
bits : 14 - 15 (2 bit)

CKOUTDIV : Output serial clock divider
bits : 16 - 23 (8 bit)

CKOUTSRC : Output serial clock source selection
bits : 30 - 30 (1 bit)

DFSDMEN : Global enable for DFSDM interface
bits : 31 - 31 (1 bit)


DFSDM_CHCFG0R2 (CHCFG0R2)

DFSDM channel configuration 0 register 2
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CHCFG0R2 DFSDM_CHCFG0R2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTRBS OFFSET

DTRBS : Data right bit-shift for channel 0
bits : 3 - 7 (5 bit)

OFFSET : 24-bit calibration offset for channel 0
bits : 8 - 31 (24 bit)


DFSDM_CHCFG1R2 (CHCFG1R2)

DFSDM channel configuration 1 register 2
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CHCFG1R2 DFSDM_CHCFG1R2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTRBS OFFSET

DTRBS : Data right bit-shift for channel 1
bits : 3 - 7 (5 bit)

OFFSET : 24-bit calibration offset for channel 1
bits : 8 - 31 (24 bit)


DFSDM_CHCFG2R2 (CHCFG2R2)

DFSDM channel configuration 2 register 2
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CHCFG2R2 DFSDM_CHCFG2R2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTRBS OFFSET

DTRBS : Data right bit-shift for channel 2
bits : 3 - 7 (5 bit)

OFFSET : 24-bit calibration offset for channel 2
bits : 8 - 31 (24 bit)


DFSDM_CHCFG3R2 (CHCFG3R2)

DFSDM channel configuration 3 register 2
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CHCFG3R2 DFSDM_CHCFG3R2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTRBS OFFSET

DTRBS : Data right bit-shift for channel 3
bits : 3 - 7 (5 bit)

OFFSET : 24-bit calibration offset for channel 3
bits : 8 - 31 (24 bit)


DFSDM_CHCFG4R2 (CHCFG4R2)

DFSDM channel configuration 4 register 2
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CHCFG4R2 DFSDM_CHCFG4R2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTRBS OFFSET

DTRBS : Data right bit-shift for channel 4
bits : 3 - 7 (5 bit)

OFFSET : 24-bit calibration offset for channel 4
bits : 8 - 31 (24 bit)


DFSDM_CHCFG5R2 (CHCFG5R2)

DFSDM channel configuration 5 register 2
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CHCFG5R2 DFSDM_CHCFG5R2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTRBS OFFSET

DTRBS : Data right bit-shift for channel 5
bits : 3 - 7 (5 bit)

OFFSET : 24-bit calibration offset for channel 5
bits : 8 - 31 (24 bit)


DFSDM_CHCFG6R2 (CHCFG6R2)

DFSDM channel configuration 6 register 2
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CHCFG6R2 DFSDM_CHCFG6R2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTRBS OFFSET

DTRBS : Data right bit-shift for channel 6
bits : 3 - 7 (5 bit)

OFFSET : 24-bit calibration offset for channel 6
bits : 8 - 31 (24 bit)


DFSDM_CHCFG7R2 (CHCFG7R2)

DFSDM channel configuration 7 register 2
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CHCFG7R2 DFSDM_CHCFG7R2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTRBS OFFSET

DTRBS : Data right bit-shift for channel 7
bits : 3 - 7 (5 bit)

OFFSET : 24-bit calibration offset for channel 7
bits : 8 - 31 (24 bit)


DFSDM_CHCFG1R1 (CHCFG1R1)

DFSDM channel configuration 1 register 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CHCFG1R1 DFSDM_CHCFG1R1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SITP SPICKSEL SCDEN CKABEN CHEN CHINSEL DATMPX DATPACK CKOUTDIV CKOUTSRC DFSDMEN

SITP : Serial interface type for channel 1
bits : 0 - 1 (2 bit)

SPICKSEL : SPI clock select for channel 1
bits : 2 - 3 (2 bit)

SCDEN : Short-circuit detector enable on channel 1
bits : 5 - 5 (1 bit)

CKABEN : Clock absence detector enable on channel 1
bits : 6 - 6 (1 bit)

CHEN : Channel 1 enable
bits : 7 - 7 (1 bit)

CHINSEL : Channel inputs selection
bits : 8 - 8 (1 bit)

DATMPX : Input data multiplexer for channel 1
bits : 12 - 13 (2 bit)

DATPACK : Data packing mode in DFSDM_CHDATINyR register
bits : 14 - 15 (2 bit)

CKOUTDIV : Output serial clock divider
bits : 16 - 23 (8 bit)

CKOUTSRC : Output serial clock source selection
bits : 30 - 30 (1 bit)

DFSDMEN : Global enable for DFSDM interface
bits : 31 - 31 (1 bit)


DFSDM_AWSCD0R (AWSCD0R)

DFSDM analog watchdog and short-circuit detector register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_AWSCD0R DFSDM_AWSCD0R read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCDT BKSCD AWFOSR AWFORD

SCDT : short-circuit detector threshold for channel 0
bits : 0 - 7 (8 bit)

BKSCD : Break signal assignment for short-circuit detector on channel 0
bits : 12 - 15 (4 bit)

AWFOSR : Analog watchdog filter oversampling ratio (decimation rate) on channel 0
bits : 16 - 20 (5 bit)

AWFORD : Analog watchdog Sinc filter order on channel 0
bits : 22 - 23 (2 bit)


DFSDM_AWSCD1R (AWSCD1R)

DFSDM analog watchdog and short-circuit detector register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_AWSCD1R DFSDM_AWSCD1R read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCDT BKSCD AWFOSR AWFORD

SCDT : short-circuit detector threshold for channel 1
bits : 0 - 7 (8 bit)

BKSCD : Break signal assignment for short-circuit detector on channel 1
bits : 12 - 15 (4 bit)

AWFOSR : Analog watchdog filter oversampling ratio (decimation rate) on channel 1
bits : 16 - 20 (5 bit)

AWFORD : Analog watchdog Sinc filter order on channel 1
bits : 22 - 23 (2 bit)


DFSDM_AWSCD2R (AWSCD2R)

DFSDM analog watchdog and short-circuit detector register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_AWSCD2R DFSDM_AWSCD2R read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCDT BKSCD AWFOSR AWFORD

SCDT : short-circuit detector threshold for channel 2
bits : 0 - 7 (8 bit)

BKSCD : Break signal assignment for short-circuit detector on channel 2
bits : 12 - 15 (4 bit)

AWFOSR : Analog watchdog filter oversampling ratio (decimation rate) on channel 2
bits : 16 - 20 (5 bit)

AWFORD : Analog watchdog Sinc filter order on channel 2
bits : 22 - 23 (2 bit)


DFSDM_AWSCD3R (AWSCD3R)

DFSDM analog watchdog and short-circuit detector register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_AWSCD3R DFSDM_AWSCD3R read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCDT BKSCD AWFOSR AWFORD

SCDT : short-circuit detector threshold for channel 3
bits : 0 - 7 (8 bit)

BKSCD : Break signal assignment for short-circuit detector on channel 3
bits : 12 - 15 (4 bit)

AWFOSR : Analog watchdog filter oversampling ratio (decimation rate) on channel 3
bits : 16 - 20 (5 bit)

AWFORD : Analog watchdog Sinc filter order on channel 3
bits : 22 - 23 (2 bit)


DFSDM_AWSCD4R (AWSCD4R)

DFSDM analog watchdog and short-circuit detector register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_AWSCD4R DFSDM_AWSCD4R read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCDT BKSCD AWFOSR AWFORD

SCDT : short-circuit detector threshold for channel 4
bits : 0 - 7 (8 bit)

BKSCD : Break signal assignment for short-circuit detector on channel 4
bits : 12 - 15 (4 bit)

AWFOSR : Analog watchdog filter oversampling ratio (decimation rate) on channel 4
bits : 16 - 20 (5 bit)

AWFORD : Analog watchdog Sinc filter order on channel 4
bits : 22 - 23 (2 bit)


DFSDM_AWSCD5R (AWSCD5R)

DFSDM analog watchdog and short-circuit detector register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_AWSCD5R DFSDM_AWSCD5R read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCDT BKSCD AWFOSR AWFORD

SCDT : short-circuit detector threshold for channel 5
bits : 0 - 7 (8 bit)

BKSCD : Break signal assignment for short-circuit detector on channel 5
bits : 12 - 15 (4 bit)

AWFOSR : Analog watchdog filter oversampling ratio (decimation rate) on channel 5
bits : 16 - 20 (5 bit)

AWFORD : Analog watchdog Sinc filter order on channel 5
bits : 22 - 23 (2 bit)


DFSDM_AWSCD6R (AWSCD6R)

DFSDM analog watchdog and short-circuit detector register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_AWSCD6R DFSDM_AWSCD6R read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCDT BKSCD AWFOSR AWFORD

SCDT : short-circuit detector threshold for channel 6
bits : 0 - 7 (8 bit)

BKSCD : Break signal assignment for short-circuit detector on channel 6
bits : 12 - 15 (4 bit)

AWFOSR : Analog watchdog filter oversampling ratio (decimation rate) on channel 6
bits : 16 - 20 (5 bit)

AWFORD : Analog watchdog Sinc filter order on channel 6
bits : 22 - 23 (2 bit)


DFSDM_AWSCD7R (AWSCD7R)

DFSDM analog watchdog and short-circuit detector register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_AWSCD7R DFSDM_AWSCD7R read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCDT BKSCD AWFOSR AWFORD

SCDT : short-circuit detector threshold for channel 7
bits : 0 - 7 (8 bit)

BKSCD : Break signal assignment for short-circuit detector on channel 7
bits : 12 - 15 (4 bit)

AWFOSR : Analog watchdog filter oversampling ratio (decimation rate) on channel 7
bits : 16 - 20 (5 bit)

AWFORD : Analog watchdog Sinc filter order on channel 7
bits : 22 - 23 (2 bit)


DFSDM_CHWDAT0R (CHWDAT0R)

DFSDM channel watchdog filter data register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CHWDAT0R DFSDM_CHWDAT0R read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDATA

WDATA : Input channel y watchdog data
bits : 0 - 15 (16 bit)


DFSDM_CHWDAT1R (CHWDAT1R)

DFSDM channel watchdog filter data register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CHWDAT1R DFSDM_CHWDAT1R read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDATA

WDATA : Input channel y watchdog data
bits : 0 - 15 (16 bit)


DFSDM_CHWDAT2R (CHWDAT2R)

DFSDM channel watchdog filter data register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CHWDAT2R DFSDM_CHWDAT2R read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDATA

WDATA : Input channel y watchdog data
bits : 0 - 15 (16 bit)


DFSDM_CHWDAT3R (CHWDAT3R)

DFSDM channel watchdog filter data register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CHWDAT3R DFSDM_CHWDAT3R read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDATA

WDATA : Input channel y watchdog data
bits : 0 - 15 (16 bit)


DFSDM_CHWDAT4R (CHWDAT4R)

DFSDM channel watchdog filter data register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CHWDAT4R DFSDM_CHWDAT4R read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDATA

WDATA : Input channel y watchdog data
bits : 0 - 15 (16 bit)


DFSDM_CHWDAT5R (CHWDAT5R)

DFSDM channel watchdog filter data register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CHWDAT5R DFSDM_CHWDAT5R read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDATA

WDATA : Input channel y watchdog data
bits : 0 - 15 (16 bit)


DFSDM_CHWDAT6R (CHWDAT6R)

DFSDM channel watchdog filter data register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CHWDAT6R DFSDM_CHWDAT6R read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDATA

WDATA : Input channel y watchdog data
bits : 0 - 15 (16 bit)


DFSDM_CHWDAT7R (CHWDAT7R)

DFSDM channel watchdog filter data register
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CHWDAT7R DFSDM_CHWDAT7R read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDATA

WDATA : Input channel y watchdog data
bits : 0 - 15 (16 bit)


DFSDM_CHCFG2R1 (CHCFG2R1)

DFSDM channel configuration 2 register 1
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CHCFG2R1 DFSDM_CHCFG2R1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SITP SPICKSEL SCDEN CKABEN CHEN CHINSEL DATMPX DATPACK CKOUTDIV CKOUTSRC DFSDMEN

SITP : Serial interface type for channel 2
bits : 0 - 1 (2 bit)

SPICKSEL : SPI clock select for channel 2
bits : 2 - 3 (2 bit)

SCDEN : Short-circuit detector enable on channel 2
bits : 5 - 5 (1 bit)

CKABEN : Clock absence detector enable on channel 2
bits : 6 - 6 (1 bit)

CHEN : Channel 2 enable
bits : 7 - 7 (1 bit)

CHINSEL : Channel inputs selection
bits : 8 - 8 (1 bit)

DATMPX : Input data multiplexer for channel 2
bits : 12 - 13 (2 bit)

DATPACK : Data packing mode in DFSDM_CHDATINyR register
bits : 14 - 15 (2 bit)

CKOUTDIV : Output serial clock divider
bits : 16 - 23 (8 bit)

CKOUTSRC : Output serial clock source selection
bits : 30 - 30 (1 bit)

DFSDMEN : Global enable for DFSDM interface
bits : 31 - 31 (1 bit)


DFSDM_CHDATIN0R (CHDATIN0R)

DFSDM channel data input register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CHDATIN0R DFSDM_CHDATIN0R read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INDAT0 INDAT1

INDAT0 : Input data for channel 0
bits : 0 - 15 (16 bit)

INDAT1 : Input data for channel 1
bits : 16 - 31 (16 bit)


DFSDM_CHDATIN1R (CHDATIN1R)

DFSDM channel data input register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CHDATIN1R DFSDM_CHDATIN1R read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INDAT0 INDAT1

INDAT0 : Input data for channel 1
bits : 0 - 15 (16 bit)

INDAT1 : Input data for channel 2
bits : 16 - 31 (16 bit)


DFSDM_CHDATIN2R (CHDATIN2R)

DFSDM channel data input register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CHDATIN2R DFSDM_CHDATIN2R read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INDAT0 INDAT1

INDAT0 : Input data for channel 2
bits : 0 - 15 (16 bit)

INDAT1 : Input data for channel 3
bits : 16 - 31 (16 bit)


DFSDM_CHDATIN3R (CHDATIN3R)

DFSDM channel data input register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CHDATIN3R DFSDM_CHDATIN3R read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INDAT0 INDAT1

INDAT0 : Input data for channel 3
bits : 0 - 15 (16 bit)

INDAT1 : Input data for channel 4
bits : 16 - 31 (16 bit)


DFSDM_CHDATIN4R (CHDATIN4R)

DFSDM channel data input register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CHDATIN4R DFSDM_CHDATIN4R read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INDAT0 INDAT1

INDAT0 : Input data for channel 4
bits : 0 - 15 (16 bit)

INDAT1 : Input data for channel 5
bits : 16 - 31 (16 bit)


DFSDM_CHDATIN5R (CHDATIN5R)

DFSDM channel data input register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CHDATIN5R DFSDM_CHDATIN5R read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INDAT0 INDAT1

INDAT0 : Input data for channel 5
bits : 0 - 15 (16 bit)

INDAT1 : Input data for channel 6
bits : 16 - 31 (16 bit)


DFSDM_CHDATIN6R (CHDATIN6R)

DFSDM channel data input register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CHDATIN6R DFSDM_CHDATIN6R read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INDAT0 INDAT1

INDAT0 : Input data for channel 6
bits : 0 - 15 (16 bit)

INDAT1 : Input data for channel 7
bits : 16 - 31 (16 bit)


DFSDM_CHDATIN7R (CHDATIN7R)

DFSDM channel data input register
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CHDATIN7R DFSDM_CHDATIN7R read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INDAT0 INDAT1

INDAT0 : Input data for channel 7
bits : 0 - 15 (16 bit)

INDAT1 : Input data for channel 8
bits : 16 - 31 (16 bit)


DFSDM0_CR1

DFSDM control register 1
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM0_CR1 DFSDM0_CR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DFEN JSWSTART JSYNC JSCAN JDMAEN JEXTSEL JEXTEN RSWSTART RCONT RSYNC RDMAEN RCH FAST AWFSEL

DFEN : DFSDM enable
bits : 0 - 0 (1 bit)

JSWSTART : Start a conversion of the injected group of channels
bits : 1 - 1 (1 bit)

JSYNC : Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger
bits : 3 - 3 (1 bit)

JSCAN : Scanning conversion mode for injected conversions
bits : 4 - 4 (1 bit)

JDMAEN : DMA channel enabled to read data for the injected channel group
bits : 5 - 5 (1 bit)

JEXTSEL : Trigger signal selection for launching injected conversions
bits : 8 - 12 (5 bit)

JEXTEN : Trigger enable and trigger edge selection for injected conversions
bits : 13 - 14 (2 bit)

RSWSTART : Software start of a conversion on the regular channel
bits : 17 - 17 (1 bit)

RCONT : Continuous mode selection for regular conversions
bits : 18 - 18 (1 bit)

RSYNC : Launch regular conversion synchronously with DFSDM0
bits : 19 - 19 (1 bit)

RDMAEN : DMA channel enabled to read data for the regular conversion
bits : 21 - 21 (1 bit)

RCH : Regular channel selection
bits : 24 - 26 (3 bit)

FAST : Fast conversion mode selection for regular conversions
bits : 29 - 29 (1 bit)

AWFSEL : Analog watchdog fast mode select
bits : 30 - 30 (1 bit)


DFSDM1_CR1

DFSDM control register 1
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM1_CR1 DFSDM1_CR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DFEN JSWSTART JSYNC JSCAN JDMAEN JEXTSEL JEXTEN RSWSTART RCONT RSYNC RDMAEN RCH FAST AWFSEL

DFEN : DFSDM enable
bits : 0 - 0 (1 bit)

JSWSTART : Start a conversion of the injected group of channels
bits : 1 - 1 (1 bit)

JSYNC : Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger
bits : 3 - 3 (1 bit)

JSCAN : Scanning conversion mode for injected conversions
bits : 4 - 4 (1 bit)

JDMAEN : DMA channel enabled to read data for the injected channel group
bits : 5 - 5 (1 bit)

JEXTSEL : Trigger signal selection for launching injected conversions
bits : 8 - 12 (5 bit)

JEXTEN : Trigger enable and trigger edge selection for injected conversions
bits : 13 - 14 (2 bit)

RSWSTART : Software start of a conversion on the regular channel
bits : 17 - 17 (1 bit)

RCONT : Continuous mode selection for regular conversions
bits : 18 - 18 (1 bit)

RSYNC : Launch regular conversion synchronously with DFSDM0
bits : 19 - 19 (1 bit)

RDMAEN : DMA channel enabled to read data for the regular conversion
bits : 21 - 21 (1 bit)

RCH : Regular channel selection
bits : 24 - 26 (3 bit)

FAST : Fast conversion mode selection for regular conversions
bits : 29 - 29 (1 bit)

AWFSEL : Analog watchdog fast mode select
bits : 30 - 30 (1 bit)


DFSDM2_CR1

DFSDM control register 1
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM2_CR1 DFSDM2_CR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DFEN JSWSTART JSYNC JSCAN JDMAEN JEXTSEL JEXTEN RSWSTART RCONT RSYNC RDMAEN RCH FAST AWFSEL

DFEN : DFSDM enable
bits : 0 - 0 (1 bit)

JSWSTART : Start a conversion of the injected group of channels
bits : 1 - 1 (1 bit)

JSYNC : Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger
bits : 3 - 3 (1 bit)

JSCAN : Scanning conversion mode for injected conversions
bits : 4 - 4 (1 bit)

JDMAEN : DMA channel enabled to read data for the injected channel group
bits : 5 - 5 (1 bit)

JEXTSEL : Trigger signal selection for launching injected conversions
bits : 8 - 12 (5 bit)

JEXTEN : Trigger enable and trigger edge selection for injected conversions
bits : 13 - 14 (2 bit)

RSWSTART : Software start of a conversion on the regular channel
bits : 17 - 17 (1 bit)

RCONT : Continuous mode selection for regular conversions
bits : 18 - 18 (1 bit)

RSYNC : Launch regular conversion synchronously with DFSDM0
bits : 19 - 19 (1 bit)

RDMAEN : DMA channel enabled to read data for the regular conversion
bits : 21 - 21 (1 bit)

RCH : Regular channel selection
bits : 24 - 26 (3 bit)

FAST : Fast conversion mode selection for regular conversions
bits : 29 - 29 (1 bit)

AWFSEL : Analog watchdog fast mode select
bits : 30 - 30 (1 bit)


DFSDM3_CR1

DFSDM control register 1
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM3_CR1 DFSDM3_CR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DFEN JSWSTART JSYNC JSCAN JDMAEN JEXTSEL JEXTEN RSWSTART RCONT RSYNC RDMAEN RCH FAST AWFSEL

DFEN : DFSDM enable
bits : 0 - 0 (1 bit)

JSWSTART : Start a conversion of the injected group of channels
bits : 1 - 1 (1 bit)

JSYNC : Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger
bits : 3 - 3 (1 bit)

JSCAN : Scanning conversion mode for injected conversions
bits : 4 - 4 (1 bit)

JDMAEN : DMA channel enabled to read data for the injected channel group
bits : 5 - 5 (1 bit)

JEXTSEL : Trigger signal selection for launching injected conversions
bits : 8 - 12 (5 bit)

JEXTEN : Trigger enable and trigger edge selection for injected conversions
bits : 13 - 14 (2 bit)

RSWSTART : Software start of a conversion on the regular channel
bits : 17 - 17 (1 bit)

RCONT : Continuous mode selection for regular conversions
bits : 18 - 18 (1 bit)

RSYNC : Launch regular conversion synchronously with DFSDM0
bits : 19 - 19 (1 bit)

RDMAEN : DMA channel enabled to read data for the regular conversion
bits : 21 - 21 (1 bit)

RCH : Regular channel selection
bits : 24 - 26 (3 bit)

FAST : Fast conversion mode selection for regular conversions
bits : 29 - 29 (1 bit)

AWFSEL : Analog watchdog fast mode select
bits : 30 - 30 (1 bit)


DFSDM0_CR2

DFSDM control register 2
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM0_CR2 DFSDM0_CR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JEOCIE REOCIE JOVRIE ROVRIE AWDIE SCDIE CKABIE EXCH AWDCH

JEOCIE : Injected end of conversion interrupt enable
bits : 0 - 0 (1 bit)

REOCIE : Regular end of conversion interrupt enable
bits : 1 - 1 (1 bit)

JOVRIE : Injected data overrun interrupt enable
bits : 2 - 2 (1 bit)

ROVRIE : Regular data overrun interrupt enable
bits : 3 - 3 (1 bit)

AWDIE : Analog watchdog interrupt enable
bits : 4 - 4 (1 bit)

SCDIE : Short-circuit detector interrupt enable
bits : 5 - 5 (1 bit)

CKABIE : Clock absence interrupt enable
bits : 6 - 6 (1 bit)

EXCH : Extremes detector channel selection
bits : 8 - 15 (8 bit)

AWDCH : Analog watchdog channel selection
bits : 16 - 23 (8 bit)


DFSDM1_CR2

DFSDM control register 2
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM1_CR2 DFSDM1_CR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JEOCIE REOCIE JOVRIE ROVRIE AWDIE SCDIE CKABIE EXCH AWDCH

JEOCIE : Injected end of conversion interrupt enable
bits : 0 - 0 (1 bit)

REOCIE : Regular end of conversion interrupt enable
bits : 1 - 1 (1 bit)

JOVRIE : Injected data overrun interrupt enable
bits : 2 - 2 (1 bit)

ROVRIE : Regular data overrun interrupt enable
bits : 3 - 3 (1 bit)

AWDIE : Analog watchdog interrupt enable
bits : 4 - 4 (1 bit)

SCDIE : Short-circuit detector interrupt enable
bits : 5 - 5 (1 bit)

CKABIE : Clock absence interrupt enable
bits : 6 - 6 (1 bit)

EXCH : Extremes detector channel selection
bits : 8 - 15 (8 bit)

AWDCH : Analog watchdog channel selection
bits : 16 - 23 (8 bit)


DFSDM2_CR2

DFSDM control register 2
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM2_CR2 DFSDM2_CR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JEOCIE REOCIE JOVRIE ROVRIE AWDIE SCDIE CKABIE EXCH AWDCH

JEOCIE : Injected end of conversion interrupt enable
bits : 0 - 0 (1 bit)

REOCIE : Regular end of conversion interrupt enable
bits : 1 - 1 (1 bit)

JOVRIE : Injected data overrun interrupt enable
bits : 2 - 2 (1 bit)

ROVRIE : Regular data overrun interrupt enable
bits : 3 - 3 (1 bit)

AWDIE : Analog watchdog interrupt enable
bits : 4 - 4 (1 bit)

SCDIE : Short-circuit detector interrupt enable
bits : 5 - 5 (1 bit)

CKABIE : Clock absence interrupt enable
bits : 6 - 6 (1 bit)

EXCH : Extremes detector channel selection
bits : 8 - 15 (8 bit)

AWDCH : Analog watchdog channel selection
bits : 16 - 23 (8 bit)


DFSDM3_CR2

DFSDM control register 2
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM3_CR2 DFSDM3_CR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JEOCIE REOCIE JOVRIE ROVRIE AWDIE SCDIE CKABIE EXCH AWDCH

JEOCIE : Injected end of conversion interrupt enable
bits : 0 - 0 (1 bit)

REOCIE : Regular end of conversion interrupt enable
bits : 1 - 1 (1 bit)

JOVRIE : Injected data overrun interrupt enable
bits : 2 - 2 (1 bit)

ROVRIE : Regular data overrun interrupt enable
bits : 3 - 3 (1 bit)

AWDIE : Analog watchdog interrupt enable
bits : 4 - 4 (1 bit)

SCDIE : Short-circuit detector interrupt enable
bits : 5 - 5 (1 bit)

CKABIE : Clock absence interrupt enable
bits : 6 - 6 (1 bit)

EXCH : Extremes detector channel selection
bits : 8 - 15 (8 bit)

AWDCH : Analog watchdog channel selection
bits : 16 - 23 (8 bit)


DFSDM_CHCFG3R1 (CHCFG3R1)

DFSDM channel configuration 3 register 1
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM_CHCFG3R1 DFSDM_CHCFG3R1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SITP SPICKSEL SCDEN CKABEN CHEN CHINSEL DATMPX DATPACK CKOUTDIV CKOUTSRC DFSDMEN

SITP : Serial interface type for channel 3
bits : 0 - 1 (2 bit)

SPICKSEL : SPI clock select for channel 3
bits : 2 - 3 (2 bit)

SCDEN : Short-circuit detector enable on channel 3
bits : 5 - 5 (1 bit)

CKABEN : Clock absence detector enable on channel 3
bits : 6 - 6 (1 bit)

CHEN : Channel 3 enable
bits : 7 - 7 (1 bit)

CHINSEL : Channel inputs selection
bits : 8 - 8 (1 bit)

DATMPX : Input data multiplexer for channel 3
bits : 12 - 13 (2 bit)

DATPACK : Data packing mode in DFSDM_CHDATINyR register
bits : 14 - 15 (2 bit)

CKOUTDIV : Output serial clock divider
bits : 16 - 23 (8 bit)

CKOUTSRC : Output serial clock source selection
bits : 30 - 30 (1 bit)

DFSDMEN : Global enable for DFSDM interface
bits : 31 - 31 (1 bit)


DFSDM0_ISR

DFSDM interrupt and status register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM0_ISR DFSDM0_ISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JEOCF REOCF JOVRF ROVRF AWDF JCIP RCIP CKABF SCDF

JEOCF : End of injected conversion flag
bits : 0 - 0 (1 bit)

REOCF : End of regular conversion flag
bits : 1 - 1 (1 bit)

JOVRF : Injected conversion overrun flag
bits : 2 - 2 (1 bit)

ROVRF : Regular conversion overrun flag
bits : 3 - 3 (1 bit)

AWDF : Analog watchdog
bits : 4 - 4 (1 bit)

JCIP : Injected conversion in progress status
bits : 13 - 13 (1 bit)

RCIP : Regular conversion in progress status
bits : 14 - 14 (1 bit)

CKABF : Clock absence flag
bits : 16 - 23 (8 bit)

SCDF : short-circuit detector flag
bits : 24 - 31 (8 bit)


DFSDM1_ISR

DFSDM interrupt and status register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM1_ISR DFSDM1_ISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JEOCF REOCF JOVRF ROVRF AWDF JCIP RCIP CKABF SCDF

JEOCF : End of injected conversion flag
bits : 0 - 0 (1 bit)

REOCF : End of regular conversion flag
bits : 1 - 1 (1 bit)

JOVRF : Injected conversion overrun flag
bits : 2 - 2 (1 bit)

ROVRF : Regular conversion overrun flag
bits : 3 - 3 (1 bit)

AWDF : Analog watchdog
bits : 4 - 4 (1 bit)

JCIP : Injected conversion in progress status
bits : 13 - 13 (1 bit)

RCIP : Regular conversion in progress status
bits : 14 - 14 (1 bit)

CKABF : Clock absence flag
bits : 16 - 23 (8 bit)

SCDF : short-circuit detector flag
bits : 24 - 31 (8 bit)


DFSDM2_ISR

DFSDM interrupt and status register
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM2_ISR DFSDM2_ISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JEOCF REOCF JOVRF ROVRF AWDF JCIP RCIP CKABF SCDF

JEOCF : End of injected conversion flag
bits : 0 - 0 (1 bit)

REOCF : End of regular conversion flag
bits : 1 - 1 (1 bit)

JOVRF : Injected conversion overrun flag
bits : 2 - 2 (1 bit)

ROVRF : Regular conversion overrun flag
bits : 3 - 3 (1 bit)

AWDF : Analog watchdog
bits : 4 - 4 (1 bit)

JCIP : Injected conversion in progress status
bits : 13 - 13 (1 bit)

RCIP : Regular conversion in progress status
bits : 14 - 14 (1 bit)

CKABF : Clock absence flag
bits : 16 - 23 (8 bit)

SCDF : short-circuit detector flag
bits : 24 - 31 (8 bit)


DFSDM3_ISR

DFSDM interrupt and status register
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFSDM3_ISR DFSDM3_ISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JEOCF REOCF JOVRF ROVRF AWDF JCIP RCIP CKABF SCDF

JEOCF : End of injected conversion flag
bits : 0 - 0 (1 bit)

REOCF : End of regular conversion flag
bits : 1 - 1 (1 bit)

JOVRF : Injected conversion overrun flag
bits : 2 - 2 (1 bit)

ROVRF : Regular conversion overrun flag
bits : 3 - 3 (1 bit)

AWDF : Analog watchdog
bits : 4 - 4 (1 bit)

JCIP : Injected conversion in progress status
bits : 13 - 13 (1 bit)

RCIP : Regular conversion in progress status
bits : 14 - 14 (1 bit)

CKABF : Clock absence flag
bits : 16 - 23 (8 bit)

SCDF : short-circuit detector flag
bits : 24 - 31 (8 bit)


DFSDM0_ICR

DFSDM interrupt flag clear register
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM0_ICR DFSDM0_ICR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRJOVRF CLRROVRF CLRCKABF CLRSCDF

CLRJOVRF : Clear the injected conversion overrun flag
bits : 2 - 2 (1 bit)

CLRROVRF : Clear the regular conversion overrun flag
bits : 3 - 3 (1 bit)

CLRCKABF : Clear the clock absence flag
bits : 16 - 23 (8 bit)

CLRSCDF : Clear the short-circuit detector flag
bits : 24 - 31 (8 bit)


DFSDM1_ICR

DFSDM interrupt flag clear register
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM1_ICR DFSDM1_ICR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRJOVRF CLRROVRF CLRCKABF CLRSCDF

CLRJOVRF : Clear the injected conversion overrun flag
bits : 2 - 2 (1 bit)

CLRROVRF : Clear the regular conversion overrun flag
bits : 3 - 3 (1 bit)

CLRCKABF : Clear the clock absence flag
bits : 16 - 23 (8 bit)

CLRSCDF : Clear the short-circuit detector flag
bits : 24 - 31 (8 bit)


DFSDM2_ICR

DFSDM interrupt flag clear register
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM2_ICR DFSDM2_ICR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRJOVRF CLRROVRF CLRCKABF CLRSCDF

CLRJOVRF : Clear the injected conversion overrun flag
bits : 2 - 2 (1 bit)

CLRROVRF : Clear the regular conversion overrun flag
bits : 3 - 3 (1 bit)

CLRCKABF : Clear the clock absence flag
bits : 16 - 23 (8 bit)

CLRSCDF : Clear the short-circuit detector flag
bits : 24 - 31 (8 bit)


DFSDM3_ICR

DFSDM interrupt flag clear register
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM3_ICR DFSDM3_ICR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRJOVRF CLRROVRF CLRCKABF CLRSCDF

CLRJOVRF : Clear the injected conversion overrun flag
bits : 2 - 2 (1 bit)

CLRROVRF : Clear the regular conversion overrun flag
bits : 3 - 3 (1 bit)

CLRCKABF : Clear the clock absence flag
bits : 16 - 23 (8 bit)

CLRSCDF : Clear the short-circuit detector flag
bits : 24 - 31 (8 bit)


DFSDM0_JCHGR

DFSDM injected channel group selection register
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM0_JCHGR DFSDM0_JCHGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JCHG

JCHG : Injected channel group selection
bits : 0 - 7 (8 bit)


DFSDM1_JCHGR

DFSDM injected channel group selection register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM1_JCHGR DFSDM1_JCHGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JCHG

JCHG : Injected channel group selection
bits : 0 - 7 (8 bit)


DFSDM2_JCHGR

DFSDM injected channel group selection register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM2_JCHGR DFSDM2_JCHGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JCHG

JCHG : Injected channel group selection
bits : 0 - 7 (8 bit)


DFSDM3_JCHGR

DFSDM injected channel group selection register
address_offset : 0xEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM3_JCHGR DFSDM3_JCHGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JCHG

JCHG : Injected channel group selection
bits : 0 - 7 (8 bit)


DFSDM0_FCR

DFSDM filter control register
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM0_FCR DFSDM0_FCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IOSR FOSR FORD

IOSR : Integrator oversampling ratio (averaging length)
bits : 0 - 7 (8 bit)

FOSR : Sinc filter oversampling ratio (decimation rate)
bits : 16 - 25 (10 bit)

FORD : Sinc filter order
bits : 29 - 31 (3 bit)


DFSDM1_FCR

DFSDM filter control register
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM1_FCR DFSDM1_FCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IOSR FOSR FORD

IOSR : Integrator oversampling ratio (averaging length)
bits : 0 - 7 (8 bit)

FOSR : Sinc filter oversampling ratio (decimation rate)
bits : 16 - 25 (10 bit)

FORD : Sinc filter order
bits : 29 - 31 (3 bit)


DFSDM2_FCR

DFSDM filter control register
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM2_FCR DFSDM2_FCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IOSR FOSR FORD

IOSR : Integrator oversampling ratio (averaging length)
bits : 0 - 7 (8 bit)

FOSR : Sinc filter oversampling ratio (decimation rate)
bits : 16 - 25 (10 bit)

FORD : Sinc filter order
bits : 29 - 31 (3 bit)


DFSDM3_FCR

DFSDM filter control register
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSDM3_FCR DFSDM3_FCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IOSR FOSR FORD

IOSR : Integrator oversampling ratio (averaging length)
bits : 0 - 7 (8 bit)

FOSR : Sinc filter oversampling ratio (decimation rate)
bits : 16 - 25 (10 bit)

FORD : Sinc filter order
bits : 29 - 31 (3 bit)



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