\n

AC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1D byte (0x0)
mem_usage : registers
protection : not protected

Registers

ITCMCR

AHBSCR

ABFSR

DTCMCR

AHBPCR

CACR


ITCMCR

Instruction and Data Tightly-Coupled Memory Control Registers
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ITCMCR ITCMCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN RMW RETEN SZ

EN : EN
bits : 0 - 0 (1 bit)

RMW : RMW
bits : 1 - 1 (1 bit)

RETEN : RETEN
bits : 2 - 2 (1 bit)

SZ : SZ
bits : 3 - 6 (4 bit)


AHBSCR

AHB Slave Control register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHBSCR AHBSCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTL TPRI INITCOUNT

CTL : CTL
bits : 0 - 1 (2 bit)

TPRI : TPRI
bits : 2 - 10 (9 bit)

INITCOUNT : INITCOUNT
bits : 11 - 15 (5 bit)


ABFSR

Auxiliary Bus Fault Status register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ABFSR ABFSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ITCM DTCM AHBP AXIM EPPB AXIMTYPE

ITCM : ITCM
bits : 0 - 0 (1 bit)

DTCM : DTCM
bits : 1 - 1 (1 bit)

AHBP : AHBP
bits : 2 - 2 (1 bit)

AXIM : AXIM
bits : 3 - 3 (1 bit)

EPPB : EPPB
bits : 4 - 4 (1 bit)

AXIMTYPE : AXIMTYPE
bits : 8 - 9 (2 bit)


DTCMCR

Instruction and Data Tightly-Coupled Memory Control Registers
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DTCMCR DTCMCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN RMW RETEN SZ

EN : EN
bits : 0 - 0 (1 bit)

RMW : RMW
bits : 1 - 1 (1 bit)

RETEN : RETEN
bits : 2 - 2 (1 bit)

SZ : SZ
bits : 3 - 6 (4 bit)


AHBPCR

AHBP Control register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHBPCR AHBPCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN SZ

EN : EN
bits : 0 - 0 (1 bit)

SZ : SZ
bits : 1 - 3 (3 bit)


CACR

Auxiliary Cache Control register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CACR CACR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIWT ECCEN FORCEWT

SIWT : SIWT
bits : 0 - 0 (1 bit)

ECCEN : ECCEN
bits : 1 - 1 (1 bit)

FORCEWT : FORCEWT
bits : 2 - 2 (1 bit)



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