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RAMECC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

IER

M1CR

M1SR

M1FAR

M1FDRL

M1FDRH

M1FECR

M2CR

M2SR

M2FAR

M2FDRL

M2FDRH

M2FECR

M3CR

M3SR

M3FAR

M3FDRL

M3FDRH

M3FECR

M4CR

M4SR

M4FAR

M4FDRL

M4FDRH

M4FECR

M5CR

M5SR

M5FAR

M5FDRL

M5FDRH

M5FECR


IER

RAMECC interrupt enable register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IER IER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GIE GECCSEIE_ GECCDEIE GECCDEBWIE

GIE : Global interrupt enable
bits : 0 - 0 (1 bit)

GECCSEIE_ : Global ECC single error interrupt enable
bits : 1 - 1 (1 bit)

GECCDEIE : Global ECC double error interrupt enable
bits : 2 - 2 (1 bit)

GECCDEBWIE : Global ECC double error on byte write (BW) interrupt enable
bits : 3 - 3 (1 bit)


M1CR

RAMECC monitor x configuration register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

M1CR M1CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ECCSEIE ECCDEIE ECCDEBWIE ECCELEN

ECCSEIE : ECC single error interrupt enable
bits : 2 - 2 (1 bit)

ECCDEIE : ECC double error interrupt enable
bits : 3 - 3 (1 bit)

ECCDEBWIE : ECC double error on byte write (BW) interrupt enable
bits : 4 - 4 (1 bit)

ECCELEN : ECC error latching enable
bits : 5 - 5 (1 bit)


M1SR

RAMECC monitor x status register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

M1SR M1SR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEDCF DEDF DEBWDF

SEDCF : ECC single error detected and corrected flag
bits : 0 - 0 (1 bit)

DEDF : ECC double error detected flag
bits : 1 - 1 (1 bit)

DEBWDF : ECC double error on byte write (BW) detected flag
bits : 2 - 2 (1 bit)


M1FAR

RAMECC monitor x failing address register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

M1FAR M1FAR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FADD

FADD : ECC error failing address
bits : 0 - 31 (32 bit)


M1FDRL

RAMECC monitor x failing data low register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

M1FDRL M1FDRL read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FDATAL

FDATAL : Failing data low
bits : 0 - 31 (32 bit)


M1FDRH

RAMECC monitor x failing data high register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

M1FDRH M1FDRH read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FDATAH

FDATAH : Failing data high (64-bit memory)
bits : 0 - 31 (32 bit)


M1FECR

RAMECC monitor x failing ECC error code register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

M1FECR M1FECR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FEC

FEC : Failing error code
bits : 0 - 31 (32 bit)


M2CR

RAMECC monitor x configuration register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

M2CR M2CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ECCSEIE ECCDEIE ECCDEBWIE ECCELEN

ECCSEIE : ECC single error interrupt enable
bits : 2 - 2 (1 bit)

ECCDEIE : ECC double error interrupt enable
bits : 3 - 3 (1 bit)

ECCDEBWIE : ECC double error on byte write (BW) interrupt enable
bits : 4 - 4 (1 bit)

ECCELEN : ECC error latching enable
bits : 5 - 5 (1 bit)


M2SR

RAMECC monitor x status register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

M2SR M2SR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEDCF DEDF DEBWDF

SEDCF : ECC single error detected and corrected flag
bits : 0 - 0 (1 bit)

DEDF : ECC double error detected flag
bits : 1 - 1 (1 bit)

DEBWDF : ECC double error on byte write (BW) detected flag
bits : 2 - 2 (1 bit)


M2FAR

RAMECC monitor x failing address register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

M2FAR M2FAR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FADD

FADD : ECC error failing address
bits : 0 - 31 (32 bit)


M2FDRL

RAMECC monitor x failing data low register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

M2FDRL M2FDRL read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FDATAL

FDATAL : Failing data low
bits : 0 - 31 (32 bit)


M2FDRH

RAMECC monitor x failing data high register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

M2FDRH M2FDRH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FDATAH

FDATAH : Failing data high (64-bit memory)
bits : 0 - 31 (32 bit)


M2FECR

RAMECC monitor x failing ECC error code register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

M2FECR M2FECR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FEC

FEC : Failing error code
bits : 0 - 31 (32 bit)


M3CR

RAMECC monitor x configuration register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

M3CR M3CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ECCSEIE ECCDEIE ECCDEBWIE ECCELEN

ECCSEIE : ECC single error interrupt enable
bits : 2 - 2 (1 bit)

ECCDEIE : ECC double error interrupt enable
bits : 3 - 3 (1 bit)

ECCDEBWIE : ECC double error on byte write (BW) interrupt enable
bits : 4 - 4 (1 bit)

ECCELEN : ECC error latching enable
bits : 5 - 5 (1 bit)


M3SR

RAMECC monitor x status register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

M3SR M3SR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEDCF DEDF DEBWDF

SEDCF : ECC single error detected and corrected flag
bits : 0 - 0 (1 bit)

DEDF : ECC double error detected flag
bits : 1 - 1 (1 bit)

DEBWDF : ECC double error on byte write (BW) detected flag
bits : 2 - 2 (1 bit)


M3FAR

RAMECC monitor x failing address register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

M3FAR M3FAR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FADD

FADD : ECC error failing address
bits : 0 - 31 (32 bit)


M3FDRL

RAMECC monitor x failing data low register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

M3FDRL M3FDRL read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FDATAL

FDATAL : Failing data low
bits : 0 - 31 (32 bit)


M3FDRH

RAMECC monitor x failing data high register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

M3FDRH M3FDRH read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FDATAH

FDATAH : Failing data high (64-bit memory)
bits : 0 - 31 (32 bit)


M3FECR

RAMECC monitor x failing ECC error code register
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

M3FECR M3FECR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FEC

FEC : Failing error code
bits : 0 - 31 (32 bit)


M4CR

RAMECC monitor x configuration register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

M4CR M4CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ECCSEIE ECCDEIE ECCDEBWIE ECCELEN

ECCSEIE : ECC single error interrupt enable
bits : 2 - 2 (1 bit)

ECCDEIE : ECC double error interrupt enable
bits : 3 - 3 (1 bit)

ECCDEBWIE : ECC double error on byte write (BW) interrupt enable
bits : 4 - 4 (1 bit)

ECCELEN : ECC error latching enable
bits : 5 - 5 (1 bit)


M4SR

RAMECC monitor x status register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

M4SR M4SR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEDCF DEDF DEBWDF

SEDCF : ECC single error detected and corrected flag
bits : 0 - 0 (1 bit)

DEDF : ECC double error detected flag
bits : 1 - 1 (1 bit)

DEBWDF : ECC double error on byte write (BW) detected flag
bits : 2 - 2 (1 bit)


M4FAR

RAMECC monitor x failing address register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

M4FAR M4FAR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FADD

FADD : ECC error failing address
bits : 0 - 31 (32 bit)


M4FDRL

RAMECC monitor x failing data low register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

M4FDRL M4FDRL read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FDATAL

FDATAL : Failing data low
bits : 0 - 31 (32 bit)


M4FDRH

RAMECC monitor x failing data high register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

M4FDRH M4FDRH read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FDATAH

FDATAH : Failing data high (64-bit memory)
bits : 0 - 31 (32 bit)


M4FECR

RAMECC monitor x failing ECC error code register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : M4FDRH
reset_Mask : 0x0

M4FECR M4FECR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FEC

FEC : Failing error code
bits : 0 - 31 (32 bit)


M5CR

RAMECC monitor x configuration register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

M5CR M5CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ECCSEIE ECCDEIE ECCDEBWIE ECCELEN

ECCSEIE : ECC single error interrupt enable
bits : 2 - 2 (1 bit)

ECCDEIE : ECC double error interrupt enable
bits : 3 - 3 (1 bit)

ECCDEBWIE : ECC double error on byte write (BW) interrupt enable
bits : 4 - 4 (1 bit)

ECCELEN : ECC error latching enable
bits : 5 - 5 (1 bit)


M5SR

RAMECC monitor x status register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

M5SR M5SR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEDCF DEDF DEBWDF

SEDCF : ECC single error detected and corrected flag
bits : 0 - 0 (1 bit)

DEDF : ECC double error detected flag
bits : 1 - 1 (1 bit)

DEBWDF : ECC double error on byte write (BW) detected flag
bits : 2 - 2 (1 bit)


M5FAR

RAMECC monitor x failing address register
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

M5FAR M5FAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FADD

FADD : ECC error failing address
bits : 0 - 31 (32 bit)


M5FDRL

RAMECC monitor x failing data low register
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

M5FDRL M5FDRL read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FDATAL

FDATAL : Failing data low
bits : 0 - 31 (32 bit)


M5FDRH

RAMECC monitor x failing data high register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

M5FDRH M5FDRH read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FEC

FEC : Failing error code
bits : 0 - 31 (32 bit)


M5FECR

RAMECC monitor x failing ECC error code register
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

M5FECR M5FECR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FEC

FEC : Failing error code
bits : 0 - 31 (32 bit)



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