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address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
Control register 1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UE : USART enable
bits : 0 - 0 (1 bit)
UESM : USART enable in Stop mode
bits : 1 - 1 (1 bit)
RE : Receiver enable
bits : 2 - 2 (1 bit)
TE : Transmitter enable
bits : 3 - 3 (1 bit)
IDLEIE : IDLE interrupt enable
bits : 4 - 4 (1 bit)
RXNEIE : RXNE interrupt enable
bits : 5 - 5 (1 bit)
TCIE : Transmission complete interrupt enable
bits : 6 - 6 (1 bit)
TXEIE : interrupt enable
bits : 7 - 7 (1 bit)
PEIE : PE interrupt enable
bits : 8 - 8 (1 bit)
PS : Parity selection
bits : 9 - 9 (1 bit)
PCE : Parity control enable
bits : 10 - 10 (1 bit)
WAKE : Receiver wakeup method
bits : 11 - 11 (1 bit)
M0 : Word length
bits : 12 - 12 (1 bit)
MME : Mute mode enable
bits : 13 - 13 (1 bit)
CMIE : Character match interrupt enable
bits : 14 - 14 (1 bit)
DEDT : Driver Enable deassertion time
bits : 16 - 20 (5 bit)
DEAT : Driver Enable assertion time
bits : 21 - 25 (5 bit)
M1 : Word length
bits : 28 - 28 (1 bit)
FIFOEN : FIFO mode enable
bits : 29 - 29 (1 bit)
TXFEIE : TXFIFO empty interrupt enable
bits : 30 - 30 (1 bit)
RXFFIE : RXFIFO Full interrupt enable
bits : 31 - 31 (1 bit)
Request register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SBKRQ : Send break request
bits : 1 - 1 (1 bit)
MMRQ : Mute mode request
bits : 2 - 2 (1 bit)
RXFRQ : Receive data flush request
bits : 3 - 3 (1 bit)
TXFRQ : Transmit data flush request
bits : 4 - 4 (1 bit)
Interrupt and status register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PE : PE
bits : 0 - 0 (1 bit)
FE : FE
bits : 1 - 1 (1 bit)
NE : NE
bits : 2 - 2 (1 bit)
ORE : ORE
bits : 3 - 3 (1 bit)
IDLE : IDLE
bits : 4 - 4 (1 bit)
RXNE : RXNE
bits : 5 - 5 (1 bit)
TC : TC
bits : 6 - 6 (1 bit)
TXE : TXE
bits : 7 - 7 (1 bit)
CTSIF : CTSIF
bits : 9 - 9 (1 bit)
CTS : CTS
bits : 10 - 10 (1 bit)
BUSY : BUSY
bits : 16 - 16 (1 bit)
CMF : CMF
bits : 17 - 17 (1 bit)
SBKF : SBKF
bits : 18 - 18 (1 bit)
RWU : RWU
bits : 19 - 19 (1 bit)
WUF : WUF
bits : 20 - 20 (1 bit)
TEACK : TEACK
bits : 21 - 21 (1 bit)
REACK : REACK
bits : 22 - 22 (1 bit)
TXFE : TXFIFO Empty
bits : 23 - 23 (1 bit)
RXFF : RXFIFO Full
bits : 24 - 24 (1 bit)
RXFT : RXFIFO threshold flag
bits : 26 - 26 (1 bit)
TXFT : TXFIFO threshold flag
bits : 27 - 27 (1 bit)
Interrupt flag clear register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
PECF : Parity error clear flag
bits : 0 - 0 (1 bit)
FECF : Framing error clear flag
bits : 1 - 1 (1 bit)
NCF : Noise detected clear flag
bits : 2 - 2 (1 bit)
ORECF : Overrun error clear flag
bits : 3 - 3 (1 bit)
IDLECF : Idle line detected clear flag
bits : 4 - 4 (1 bit)
TCCF : Transmission complete clear flag
bits : 6 - 6 (1 bit)
CTSCF : CTS clear flag
bits : 9 - 9 (1 bit)
CMCF : Character match clear flag
bits : 17 - 17 (1 bit)
WUCF : Wakeup from Stop mode clear flag
bits : 20 - 20 (1 bit)
Receive data register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDR : Receive data value
bits : 0 - 8 (9 bit)
Transmit data register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDR : Transmit data value
bits : 0 - 8 (9 bit)
Prescaler register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRESCALER : Clock prescaler
bits : 0 - 3 (4 bit)
Control register 2
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDM7 : 7-bit Address Detection/4-bit Address Detection
bits : 4 - 4 (1 bit)
STOP : STOP bits
bits : 12 - 13 (2 bit)
SWAP : Swap TX/RX pins
bits : 15 - 15 (1 bit)
RXINV : RX pin active level inversion
bits : 16 - 16 (1 bit)
TXINV : TX pin active level inversion
bits : 17 - 17 (1 bit)
DATAINV : Binary data inversion
bits : 18 - 18 (1 bit)
MSBFIRST : Most significant bit first
bits : 19 - 19 (1 bit)
ADD : Address of the USART node
bits : 24 - 31 (8 bit)
Control register 3
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EIE : Error interrupt enable
bits : 0 - 0 (1 bit)
HDSEL : Half-duplex selection
bits : 3 - 3 (1 bit)
DMAR : DMA enable receiver
bits : 6 - 6 (1 bit)
DMAT : DMA enable transmitter
bits : 7 - 7 (1 bit)
RTSE : RTS enable
bits : 8 - 8 (1 bit)
CTSE : CTS enable
bits : 9 - 9 (1 bit)
CTSIE : CTS interrupt enable
bits : 10 - 10 (1 bit)
OVRDIS : Overrun Disable
bits : 12 - 12 (1 bit)
DDRE : DMA Disable on Reception Error
bits : 13 - 13 (1 bit)
DEM : Driver enable mode
bits : 14 - 14 (1 bit)
DEP : Driver enable polarity selection
bits : 15 - 15 (1 bit)
WUS : Wakeup from Stop mode interrupt flag selection
bits : 20 - 21 (2 bit)
WUFIE : Wakeup from Stop mode interrupt enable
bits : 22 - 22 (1 bit)
TXFTIE : TXFIFO threshold interrupt enable
bits : 23 - 23 (1 bit)
RXFTCFG : Receive FIFO threshold configuration
bits : 25 - 27 (3 bit)
RXFTIE : RXFIFO threshold interrupt enable
bits : 28 - 28 (1 bit)
TXFTCFG : TXFIFO threshold configuration
bits : 29 - 31 (3 bit)
Baud rate register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BRR : BRR
bits : 0 - 19 (20 bit)
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