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address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
Clock Calibration Unit Core Release Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DAY : Time Stamp Day
bits : 0 - 7 (8 bit)
MON : Time Stamp Month
bits : 8 - 15 (8 bit)
YEAR : Time Stamp Year
bits : 16 - 19 (4 bit)
SUBSTEP : Sub-step of Core Release
bits : 20 - 23 (4 bit)
STEP : Step of Core Release
bits : 24 - 27 (4 bit)
REL : Core Release
bits : 28 - 31 (4 bit)
Clock Calibration Unit Interrupt Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CWE : Calibration Watchdog Event
bits : 0 - 0 (1 bit)
CSC : Calibration State Changed
bits : 1 - 1 (1 bit)
Clock Calibration Unit Interrupt Enable Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CWEE : Calibration Watchdog Event Enable
bits : 0 - 0 (1 bit)
CSCE : Calibration State Changed Enable
bits : 1 - 1 (1 bit)
Calibration Configuration Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TQBT : Time Quanta per Bit Time
bits : 0 - 4 (5 bit)
BCC : Bypass Clock Calibration
bits : 6 - 6 (1 bit)
CFL : Calibration Field Length
bits : 7 - 7 (1 bit)
OCPM : Oscillator Clock Periods Minimum
bits : 8 - 15 (8 bit)
CDIV : Clock Divider
bits : 16 - 19 (4 bit)
SWR : Software Reset
bits : 31 - 31 (1 bit)
Calibration Status Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
OCPC : Oscillator Clock Period Counter
bits : 0 - 17 (18 bit)
TQC : Time Quanta Counter
bits : 18 - 28 (11 bit)
CALS : Calibration State
bits : 30 - 31 (2 bit)
Calibration Watchdog Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDC : WDC
bits : 0 - 15 (16 bit)
access : read-write
WDV : WDV
bits : 16 - 31 (16 bit)
access : read-only
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